CN109144848A - A kind of Verilog HDL code white-box testing assistance platform and its course of work - Google Patents
A kind of Verilog HDL code white-box testing assistance platform and its course of work Download PDFInfo
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Abstract
The invention discloses a kind of Verilog HDL code white-box testing assistance platforms, including document management module, source code display module, information extraction modules, processing information display module and association process and weight analysis module, the analysis of grammer and the retrieval of keyword are carried out to read source code, thus all input and output and the intermediate variable in the code segment are obtained, and obtains the mathematics relational expression between intermediate variable simultaneously；According to acquired relational expression, all intermediate variables and associated input and output are associated, and the weight coefficient of each intermediate variable is calculated by mathematical formulae, and then determine key node, to observe the selection of intermediate variable when carrying out white-box testing to source code.The present invention can rapidly and accurately find out crucial intermediate variable, and associated with intermediate variable and input by exporting, and improve the efficiency tested Verilog HDL code.
Description
Technical field
The present invention relates to software test platform designing techniques, and in particular to a kind of Verilog HDL code white-box testing is auxiliary
Help platform and its course of work.
Background technique
FPGA as programmable logic device, be by way of programming (such as HDL) by general-purpose chip be configured to user need
The hardware digital circuit wanted.FPGA and software systems have similar structure and development scheme, and HDL and software are all human brain thinkings
The product of logic has similar grammer and failure mechanism.White-box testing passes through the logical construction for checking software inhouse, to software
In logical path carry out coverage test；Checkpoint is set up in program different places, checks the state of program, to determine practical fortune
Whether row state is consistent with expecting state.
The compilation run for Verilog HDL language and debugging can be completed with ISE software at present, for given source
Code, ISE can automatically generate test file, need to only add again upper test case with minor modifications in the test file of generation
(given input and necessary clock control), can run to obtain the waveform diagram of input and output, can also be the intermediate variable of appearance
Choose out the waveform diagram also formed with input and clock variation, for tester observe with judge inside code whether with expection
Unanimously, this can be considered the white-box testing for Verilog HDL code.For simple code, the intermediate variable of appearance
Number is less, can by whole choose out and observe.But once code internal structure is complicated, and intermediate variable number will sharply increase
Add, the key point in intermediate variable that this method can not rapidly and accurately be found out, and can not will output and intermediate variable and defeated
Enter associated, testing efficiency is low.
Summary of the invention
The purpose of the invention is to provide a kind of Verilog HDL code white-box testing assistance platforms and its worked
Journey quickly can reasonably accurate find out crucial intermediate variable, and can not will export associated with intermediate variable and input
The problems such as, improve the efficiency of test.
The technical solution for realizing the aim of the invention is as follows: a kind of Verilog HDL code white-box testing assistance platform, packet
Include document management module, source code display module, information extraction modules, processing information display module and association process and weight point
Analyse module, in which:
Document management module, the output after being completed for the responsible opening containing source code file and information extraction processing
The preservation of file, and connect by signal file_path with source code display module；
Code in source file is shown to the display control of calling for calling display control by source code display module
On, and connect by signal req with information extraction modules；
Information extraction modules are extracted in source code out for the source code for having shown that be read and handled
Key message obtains the mathematics relational expression between each variable including all input and output and intermediate variable in code,
And it is connect by signal ini with processing information display module；
Information display module is handled, for calling display control, the output information after the completion of information extraction is shown to tune
On display control, which shows that control is parallel with source code, for comparing, and passes through signal save_path and text
Output content is saved in selected file by the connection of part management module；
Association process and weight analysis module, for by intermediate variable and all relevant input and output inside code into
Row association, is calculated the weight coefficient of intermediate variable, determines key node, and pass through signal save_path and file management
Module is connected with processing information display module.
A kind of course of work of Verilog HDL code white-box testing assistance platform, includes the following steps:
Step 1 chooses the file path containing source code, and signal file_path is sent to source code display module；
When step 2, signal file_path are not sky, source code display module obtains source file, and reads in therein
Hold, the code in the file under the path is shown in display control；
Step 3 is read and is handled to the source code for having shown that out, and the key message in source code is extracted,
Including all input and output and intermediate variable in code, and obtain the mathematics relational expression between each variable；
Processing file after progress information extraction is shown control and source file Concurrent Display by another by step 4,
And select that storing path will treated that content is saved in consults analysis after specified path supplies；
Intermediate variable inside code is associated by step 5 to all relevant input and output, calculates intermediate variable
Weight coefficient determines key node, to observe the selection of intermediate variable when carrying out white-box testing to source code.
Compared with prior art, the present invention its remarkable advantage are as follows: the present invention is designed by reasonable procedure and is laid out about
Beam, stringent logical relation, has built a Verilog HDL code white-box testing assistance platform between each signal of communication,
Crucial intermediate variable can be rapidly and accurately found out, and will export associated with intermediate variable and input, is improved pair
The efficiency that Verilog HDL code is tested.
Detailed description of the invention
The structure chart of Fig. 1 Verilog HDL code white-box testing assistance platform of the present invention.
The work flow diagram of Fig. 2 information extraction modules of the present invention.
Specific embodiment
Below by drawings and examples, technical solution of the present invention is further described.
As shown in Figure 1, a kind of Verilog HDL code white-box testing assistance platform, including document management module, source code
Display module, information extraction modules, processing information display module and association process and weight analysis module, in which:
Document management module, the output after being completed for the responsible opening containing source code file and information extraction processing
The preservation of file, and connect by signal file_path with source code display module；
Code in source file is shown to the display control of calling for calling display control by source code display module
On, and connect by signal req with information extraction modules；
Information extraction modules are extracted in source code out for the source code for having shown that be read and handled
Key message obtains the mathematics relational expression between each variable including all input and output and intermediate variable in code,
And it is connect by signal ini with processing information display module；
Information display module is handled, for calling display control, the output information after the completion of information extraction is shown to tune
On display control, which shows that control is parallel with source code, for comparing, and passes through signal save_path and text
Output content is saved in selected file by the connection of part management module；
Association process and weight analysis module, for by intermediate variable and all relevant input and output inside code into
Row association, is calculated the weight coefficient of intermediate variable, determines key node (the big intermediate variable of weight coefficient), and pass through letter
Number save_path is connect with document management module and processing information display module.
As a kind of specific embodiment, the source code display module has been selected when signal file_path is not sky
Surely file path is opened, obtains the signal, and the file under the signal specified path is opened into text in read-only mode, if should
File content is sky, then directly returns, and if not empty, reads entire contents by readall function and is stored in memory, and will
Content is shown in control.
As a kind of specific embodiment, as shown in Fig. 2, the information extraction modules send signal req when display module
=1 give information extraction modules when, to the source code in display module with function split with newline "/n " be separate carry out line by line
It reads, for hardware description language Verilog HDL, keyword can all occur in all variable statements, by source generation
The code analysis of grammer and the retrieval of keyword, obtain all input and output and the intermediate variable in the code segment, and simultaneously
Obtain the mathematics relational expression between variable.
As a kind of more specific embodiment, when the information extraction modules handle source code, a letter is defined
Number be isFindSubmodule (iFSm), when reading line by line, if in content include function or task, enable iFSm=1,
To the row and next the every a line read is all without processing, until there is " endfunction " in new a line of reading
Or " endtask ", after being disposed to entire source code, if it is 1 that value, which occurred, in signal iFSm, exporting content most
Write-in " there are submodules, and it is correct to default submodule function " afterwards；Likewise, define a signal isFindIgn (iFI), when by
When including annotation symbol " // " in the content of row reading, iFI=1 is enabled, annotation is accorded with and subsequent annotated language by erase function
Sentence is all deleted.
As a kind of specific embodiment, the association process is defeated according to the input extracted with weight analysis module
Intermediate variable, is expressed as 0/1 combination by relationship out and between intermediate variable and variable, method particularly includes: set all inputs
Being combined into an input vector is X (x1,x2,x3…xm), the number of input is m, and all intermediate variable groups are combined into a centre
Vector is Y (y1,y2,y3…yn), intermediate variable number is n, and it is Z (z that all output, which is combined into an output vector,1,z2,
z3…zj), the number of output is j, according to the relational expression between variable, if intermediate variable yaWith input xbIt is related, then set 1, it is unrelated
0 is then set, such words intermediate variable ynIt is indicated by the combined output Z of the combined input X expression in the position 0/1 m or the position 0/1 j,
(0,1,1 ‥ ‥ ‥ 1) X can be such as expressed as.In this way, intermediate variable just associates with all input and output.
As a kind of more specific embodiment, the association process and weight analysis module are by 0/1 group of the position m of intermediate variable
After the combined output Z in the input position 0/1 X and j of conjunction, y is obtained by the number that calculating wherein sets 11With a1Position input, b1Position output
It is related, likewise, ynWith anPosition input, bnPosition output is related, and intermediate variable y has been calculated by following formulaiWeight system
Number (i.e. significant coefficient):
Wherein, aiWith biFor with intermediate variable yiThe number of relevant input and output, and(all intermediate variables
Weight coefficient add up to 1).
A kind of course of work of Verilog HDL code white-box testing assistance platform, includes the following steps:
Step 1 chooses the file path containing source code, and signal file_path is sent to source code display module；
When step 2, signal file_path are not sky, source code display module obtains source file, and reads in therein
Hold, the code in the file under the path is shown in display control；
Step 3 is read and is handled to the source code for having shown that out, and the key message in source code is extracted,
Including all input and output and intermediate variable in code, and obtain the mathematics relational expression between each variable；
Processing file after progress information extraction is shown control and source file Concurrent Display by another by step 4,
And select that storing path will treated that content is saved in consults analysis after specified path supplies；
Intermediate variable inside code is associated by step 5 to all relevant input and output, calculates intermediate variable
Weight coefficient determines key node, to observe the selection of intermediate variable when carrying out white-box testing to source code.
The present invention solves and quickly can not reasonably accurate find out crucial intermediate variable, Er Qiewu in current test process
The problems such as method will export with intermediate variable and associated input, improves the efficiency to the test of Verilog HDL code.
Embodiment 1
In order to verify effectiveness of the invention, the embodiment of the present invention carries out following white-box testing test, detailed process are as follows:
Step 1 reads one section of Verilog HDL source code to be measured for realizing certain function, which at least wraps
Containing a program block.
Step 2, to read source code carry out grammer analysis and keyword retrieval, thus obtain the code segment
In all input and output and intermediate variable, and obtain the mathematics relational expression between intermediate variable simultaneously.
Step 3, according to acquired relational expression, all intermediate variables have been associated with associated input and output
Come, and the weight coefficient (i.e. significance level) of each intermediate variable is calculated by mathematical formulae.
Step 4 is called the variation checked, and judge the variable to intermediate variable important in code in ISE
Journey whether with it is desired consistent, to judge whether the Verilog HDL code to be measured qualified.
If being expected for some output in step 5, code and design is different, pass through being associated with for intermediate variable and input and output
The intermediate variable that can obtain influencing the output, the part that mistake is generated in code can quickly be oriented by checking to it.
In the present embodiment, can all have keyword " input " before all inputs, and also all can before all output
Have " output ", and for variable, common types of variables is " reg, wire, integer, tri " etc., in reading line by line
When depositing middle, in the content of reading, when including these keywords, the corresponding value of index index_flag assignment of definition is respectively as follows:
Index_reg, index_wire, index_input etc..When target variable index_flag value is empty, in a line of reading
Hold without processing, directly returns and read next line.And when index becomes specified value, then to the useful letter after keyword
Breath extracts.
The present embodiment, will be for realizing certain function by the document management module in designed white-box testing assistance platform
The Verilog HDL code of energy is read in.In this implementation column, code should contain at least one program block, wherein program block is structure
At the basic unit of software under testing.It is the unit module test carried out software early period, the program block of source code based on white-box testing
In should not include submodule as far as possible, otherwise submodule will be unable to be detected and be judged, it is correct that its function can only be defaulted.
It will wherein be weighed in the present embodiment by the weight coefficient for each intermediate variable that Platform Analysis calculates
The big intermediate variable of weight coefficient calls out in composing software ISE, observes it with input and the change procedure of clock, and with
Change procedure desired by Code Design compares, if unanimously, it is believed that intermediate process involved in the intermediate variable is just
Really, otherwise it is assumed that its mistake.Tester, which can set a qualification parameters, may be designed as 90% in the present embodiment.Pass through
It is observed and judges to by the intermediate variable of the big minispread of weight coefficient, if the weight coefficient of the intermediate variable of mistake is greater than
10%, i.e., it is believed that the program code does not meet design requirement.
If some output of code and desired difference, the intermediate variable having an impact to it can be checked by calling
(also being arranged by weight coefficient) can be improved without observing all input and intermediate variable and generate position positioning to mistake
Efficiency, save a large amount of manpower and material resources.
Claims (7)
1. a kind of Verilog HDL code white-box testing assistance platform, which is characterized in that including document management module, source code
Display module, information extraction modules, processing information display module and association process and weight analysis module, in which:
Document management module, the output file after being completed for the responsible opening containing source code file and information extraction processing
Preservation, and connect with source code display module by signal file_path；
Code in source file is shown on the display control of calling by source code display module for calling display control, and
It is connect by signal req with information extraction modules；
Information extraction modules extract the key in source code for the source code for having shown that out to be read and handled
Information obtains the mathematics relational expression between each variable, and lead to including all input and output and intermediate variable in code
Signal ini is crossed to connect with processing information display module；
Information display module is handled, for calling display control, the output information after the completion of information extraction is shown to calling
It shows on control, which shows that control is parallel with source code, for comparing, and passes through signal save_path and file pipe
Module connection is managed, output content is saved in selected file；
Association process and weight analysis module, for closing the intermediate variable inside code to all relevant input and output
Connection, is calculated the weight coefficient of intermediate variable, determines key node, and pass through signal save_path and document management module
It is connected with processing information display module.
2. Verilog HDL code white-box testing assistance platform according to claim 1, which is characterized in that the source generation
Code display module select opening file path, has obtained the signal when signal file_path is not sky, and by the signal
File under specified path opens text in read-only mode, if this document content is sky, directly returns, and if not empty, leads to
It crosses readall function reading entire contents to be stored in memory, and content is shown in control.
3. Verilog HDL code white-box testing assistance platform according to claim 1, which is characterized in that the information
Extraction module is when display module sends signal req=1 to information extraction modules, to the source code function in display module
Split is to separate to be read line by line with newline "/n ", for hardware description language Verilog HDL, all changes
Keyword can all occur in amount statement, by the retrieval of analysis and keyword to source code syntax, obtain in the code segment
All input and output and intermediate variable, and the mathematics relational expression between variable is obtained simultaneously.
4. Verilog HDL code white-box testing assistance platform according to claim 3, which is characterized in that the information
When extraction module handles source code, defining a signal is iFSm, when reading line by line, if in content including function
Or task, then iFSm=1 is enabled, the every a line to the row and next read is all without processing, until new a line of reading
Middle appearance " endfunction " or " endtask ", after being disposed to entire source code, if value occurred in signal iFSm
It is 1, then is ultimately written " there are submodules, and it is correct to default submodule function " in output content；Likewise, defining a signal
IFI enables iFI=1 when in the content read line by line comprising annotation symbol " // ", by erase function by annotation symbol and thereafter
Comment statement all delete.
5. Verilog HDL code white-box testing assistance platform according to claim 1, which is characterized in that the association
Processing and weight analysis module are according to relationship between the input and output and intermediate variable and variable extracted, by intermediate variable
It is expressed as 0/1 combination, method particularly includes: it sets all inputs and is combined into an input vector as X (x1, x2, x3…xm), it is defeated
The number entered is m, and it is Y (y that all intermediate variable groups, which are combined into an intermediate vector,1, y2, y3…yn), intermediate variable number is n,
It is Z (z that all output, which is combined into an output vector,1, z2, z3…zj), the number of output is j, according to the relationship between variable
Formula, if intermediate variable yaWith input xbIt is related, then set 1, it is unrelated, 0 is set, such words intermediate variable ynIt is combined by the position m 0/1
Inputting the output Z that X is indicated or the position 0/1 j is combined indicates, in this way, intermediate variable just associates with all input and output.
6. Verilog HDL code white-box testing assistance platform according to claim 5, which is characterized in that the association
After handling the combined output Z in the input position 0/1 X and j for combining intermediate variable with the position m 0/1 with weight analysis module, pass through calculating
The number for wherein setting 1 obtains y1With a1Position input, b1Position output is related, likewise, ynWith anPosition input, bnPosition output is related, leads to
It crosses following formula and intermediate variable y has been calculatediWeight coefficient:
Wherein, aiWith biFor with intermediate variable yiThe number of relevant input and output, and
7. a kind of course of work of Verilog HDL code white-box testing assistance platform, which comprises the steps of:
Step 1 chooses the file path containing source code, and signal file_path is sent to source code display module；
When step 2, signal file_path are not sky, source code display module obtains source file, and reads content therein, will
The code in file under the path is shown in display control；
Step 3 is read and is handled to the source code for having shown that out, and the key message in source code is extracted, including
All input and output and intermediate variable in code, and obtain the mathematics relational expression between each variable；
Processing file after progress information extraction is shown control and source file Concurrent Display by another, and selected by step 4
Selecting storing path, content is saved in access analysis after specified path supplies by treated；
Intermediate variable inside code is associated by step 5 to all relevant input and output, calculates the weight of intermediate variable
Coefficient determines key node, to observe the selection of intermediate variable when carrying out white-box testing to source code.
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| CN110990263A (en) * | 2019-11-09 | 2020-04-10 | 上海集成电路研发中心有限公司 | Automatic generator and generation method for test case set |
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| CN110990263A (en) * | 2019-11-09 | 2020-04-10 | 上海集成电路研发中心有限公司 | Automatic generator and generation method for test case set |
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| US20230005558A1 (en) * | 2021-07-02 | 2023-01-05 | Changxin Memory Technologies, Inc. | Signal generation circuit and method, and semiconductor memory |
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