CN109104260B - The synchronous method of plate card type multichannel data acquisition system - Google Patents
The synchronous method of plate card type multichannel data acquisition system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
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Abstract
The invention discloses a kind of synchronous method of plate card type multichannel data acquisition system, clock network is designed first, then according to the clock of module each in plate card type multichannel data acquisition system to master, it is designed from clock source chip, and critical clock paths PCB is designed, it constructs two-stage and is fanned out to Clock Tree, it is led in system initialization, it is synchronized from the synchronization of clock source and from clock source output clock, and front end is set in analog input card and transmits adjustment cache module, data are set in information processing mainboard and store FIFO, to realize that acquisition data are synchronous.The present invention is by arranging clock line, clock generates and initial method improves, and improves the net synchronization capability of multichannel collecting data.
Description
Technical field
The invention belongs to multichannel data acquisition system technical fields, more specifically, are related to a kind of plate card type multi-pass
The synchronous method of track data acquisition system.
Background technique
In existing digital multi-channel acquisition system, part electrographic recording instrument system possesses reply multiregion signal acquisition
Function, the specific signal that acquires may relate to temperature, strain, frequency, logic, the capture of the analog signals such as Current Voltage.?
Industry should carry out the interaction of data, individual acquisition to different acquisition targets often by design isolation analog input card and host
Card is to positioned at single card slot.Therefore the synchronization accuracy of card slot becomes one that such system designs just like index and difficult point,
Accuracy often requires that more than nanosecond.
As the technology of domestic digital electrographic recording instrument develops, the bandwidth of acquisition system is also higher and higher, and port number is also got over
Come more, and multiple channels must just bring the mutual asynchronous problem of each interchannel.It is domestic at present on the market based on multichannel
Synchronous acquisition feasible scheme of the multichannel data acquisition system of converter under the measurement environment of degree of precision is still less.
In the existing technology for solving high-speed multiple channel synchronous acquisition, has and pass through generation using the method for path control
One correcting signal with triggering edge deviates sampling number to calculate the theoretical of each acquisition channel, passes through control offset display
Mode carries out the reproduction and correction of waveform.It is portable good that the advantages of above-mentioned technical method, is, can cope with different asynchronous
Collecting mechanism synchronizes data and shows, but is merely and sets out the angle of asynchronous phenomenon result to solve asynchronous technology
Problem.
Solve high-speed digital system another multi channel signals synchronous method be after calculating each path delay deviation,
Prolonged each from receiving data path other receiving paths in addition to primary path according to each delay distortion for receiving data path
It is synchronized on the primary path late.To realize the delay compensation and the operation of data simultaneous display of interchannel.The advantages of the method, exists
It will not be limited by FIFO depth in the delay compensation for being directed to each channel, avoid the different problem of data path delay,
But it must be taken into consideration that fpga logic resource meets situation and data lose a situation when coping with the system of multichannel in the design.
It is found after the research to domestic and international multi-channel high-accuracy Design of Synchronization Technology, the synchronous elder generation of multichannel collecting system
Certainly condition be positioned at the shake of clock it is synchronous with transmission clock whether.
In conclusion lack in the prior art it is a kind of guarantee data it is reliable under the premise of from the angle of clock scheme
Processing multichannel data phase is asynchronous, and saves the solution of more logical resources.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of plate card type multichannel data acquisition systems
Synchronous method, by arranging to clock line, clock generates and initial method improves, and improves the same of multichannel collecting data
Walk performance.
In order to realize the above goal of the invention, the synchronous method of plate card type multichannel data acquisition system of the present invention includes following
Step:
S1: master clock source is set in the signal processing mainboard of plate card type multichannel data acquisition system, in each acquisition
Setting is from clock source in board, and building obtains clock network in the following ways:
Master clock source generates reference clock signal CLK_MOUT, is divided into the road N+1, and N indicates plate card type multi-channel data acquisition
Number of channels in system, wherein the road N reference clock signal exports N number of card slot data processing list into signal processing mainboard
Member, when 1 road reference clock signal exports data processing synchronization of the rear end FPGA into signal processing mainboard as rear end FPGA
Clock；Each card slot data processing unit carries out clock transfer with the high-speed interface device in corresponding analog input card, and reference clock is believed
Number CLK_MOUT is transmitted to the slave clock source in corresponding analog input card；
In each analog input card, from clock source using reference clock signal CLK_MOUT as input, H is generatednWhen+2 tunnel
Clock signal CLK_SOUT, HnIndicate the quantity of ADC in n-th of analog input card, HnRoad clock exports the H into analog input card respectivelyn
Piece ADC is as acquisition reference clock, and 1 road clock is as transmission time domain reference clock, and 1 tunnel is as analog input card to signal processing master
The data transmission synchronization clock of plate；
S2: remember that reference clock frequency needed for ADC is f in N number of analog input cardADC_n, n=1,2 ..., N, analog input card arrives
The data transmission synchronization clock frequency of signal processing mainboard is fM_SYNC, the data processing of rear end FPGA is same in signal processing mainboard
Step clock is fSYS, then the frequency f of reference clock signal CLK_MOUTREFCalculation formula is as follows:
fREF≥max{fADC_1,fADC_2,…,fADC_N,fM_SYNC,fSYS}
The output frequency f of master clock source chipout, output number K should meet following relationship:
fout≥fREF
K≥N+1
N number of analog input card is used with model from clock source chip, clock output number L, clock input frequency fS_in, when
Clock output frequency fS_outFollowing relationship should be met:
L≥max{H1,H2,…,HN}+2
fS_in≥fREF
fS_out≥max{fADC_1,fADC_2,…,fADC_N}
Master and slave clock source parameter is determined according to above method, generates the control instruction of master and slave clock source；
S3: when information processing mainboard carries out PCB design, need to enable the transmission of the road N+1 reference clock signal CLK_MOUT
Line is isometric, enables the biography of the data line and reference clock signal CLK_MOUT between N number of analog input card and information processing mainboard
Defeated line is isometric；
When N number of analog input card carries out PCB design, need to enable the H exported in each analog input card from clock source chipn+2
Road clock signal clk _ SOUT transmission line and HnThe data line of a ADC to high quick access mouthpart is isometric；
S4: when plate card type multichannel data acquisition system is initialized, master and slave clock source is synchronized, first
Establish the clock-reset link T of a N+2 fork treeCLOCK_RST, i.e., by tree root control terminal RSTNmainThe two class leaves control of control
Hold RSTNMaster、RSTNslave_nReset link, tree root control terminal RSTNmainIt is directly controlled by system host computer, leaf
Control terminal RSTNMasterAnd RSTNslave_nThe reseting port of master and slave clock source chip is controlled respectively, wherein RSTNMasterControl master
The chip reset of clock source, N number of RSTNslave_nControl chip reset of the road N from clock source；It is then based on tree-shaped clock-reset chain
Road carries out master and slave clock source and synchronizes, and specific steps include:
S4.1: PC control RSTNMasterPrimary reset is executed to master clock source chip to operate；
S4.2: host computer carries out master clock source chip register according to step S2 master clock source control instruction generated
Configuration；
S4.3: the master clock source control instruction that host computer is generated according to step S2 synchronizes behaviour to master clock source chip
Make, waits for a period of time until the road the K clock output of master clock source is synchronous, subsequently into step S4.4；
S4.4: host computer passes through N number of RSTNslave_nSlave clock chip in N number of acquisition slot is carried out while resetting behaviour
Make；
S4.5: host computer carries out simultaneously according to the slave clock source control instruction that step S2 is generated to from clock chip register
Configuration；
S4.6: host computer synchronizes operation to from clock chip according to the slave clock source control instruction that step S2 is generated,
It waits for a period of time until synchronous from the road the L clock output of clock source, master and slave clock synchronously completes；
S5: same to being carried out from the output clock of clock source when plate card type multichannel data acquisition system is initialized
Step, the ADC for initially setting up a L fork tree reset link TADC_RST, acquired by the ADC that the reset link transmission host computer is sent
Synchronous reset signal, ADC reset link TADC_RSTTree root control terminal RSTNADCBy PC control, L pitches the N of leaf control terminal
A reset signal RSTNADC_nThe ADC synchronous acquisition port in N number of analog input card is forwarded to by synchronously control special purpose interface；So
It resets link based on the ADC afterwards synchronize from clock source output clock, specific steps include:
S5.1: after waiting master and slave clock synchronism stability to export, believed by the reset terminal of the N number of analog input card of PC control
Number RSTNADC_n, complete once to reset operation for the concentration of N number of analog input card；
S5.2: host computer synchronizes operation to ADC according to the preset method of synchronization, waits for a period of time until all
ADC completes to synchronize；
S6: a front end being arranged before the high-speed interface device of analog input card and transmits adjustment cache module, more in plate card type
When channel data acquisition system carries out data acquisition, before data are uploaded to signal processing mainboard from analog input card, by front end
Transmission adjustment cache module carries out cross clock domain conversion to data, and data clock is converted to data transmission synchronization clock；
S7: configuration data storage FIFO carries out the data that analog input card uploads in the rear end FPGA of signal processing mainboard
Caching is received, the read-write clock of data storage FIFO is the data processing synchronised clock of rear end FPGA, and data store FIFO's
Read-write Catrol end by rear end FPGA and host computer DMA transfer mechanism control, host computer using DMA mechanism from data store FIFO
The middle simultaneous display for reading data and carrying out waveform.
The synchronous method of plate card type multichannel data acquisition system of the present invention, is first designed clock network, then
Master and slave clock source chip is designed according to the clock of module each in plate card type multichannel data acquisition system, and to key
Clock path PCB is designed, and is constructed two-stage and is fanned out to Clock Tree, and the synchronization of master and slave clock source is carried out in system initialization
And it is synchronous from clock source output clock, and front end is set in analog input card and transmits adjustment cache module, in information processing master
Data are set in plate and store FIFO, to realize that acquisition data are synchronous.
The invention has the following advantages:
1) present invention acquires generated time domain phase in data transmission procedure by clock design and hardware setting, processing
Error is synchronous to reach acquisition data-signal；
2) present invention is directed to plate card type multichannel data acquisition system, from hardware point of view, card slot isolation transmission data
With clock chain circuit so that individually the applicable a plurality of types of capture cards of card slot to complete multi pass acquisition system data synchronization work
Make；
3) simultaneously, with the increase of Measurement channel number and ADC sampling precision, data bit width increases, must disappear in FPGA
More resources are consumed to handle such problem, are compared and ensure that data transmission is reliable with other Channel Synchronous methods, the present invention
Under the premise of without the additional more FPGA hardware logical resources of consumption, have more cost advantage.
Detailed description of the invention
Fig. 1 is the specific embodiment flow chart of the synchronous method of plate card type multichannel data acquisition system of the present invention；
Fig. 2 is the structure chart of existing plate card type multichannel data acquisition system；
Fig. 3 is that the plate card type multichannel data acquisition system based on existing synchronous method believes the acquisition of first group of signal source
Number display figure；
Fig. 4 is that the plate card type multichannel data acquisition system based on existing synchronous method believes the acquisition of second group of signal source
Number display figure；
Fig. 5 is that the plate card type multichannel data acquisition system based on existing synchronous method believes the acquisition of third group signal source
Number display figure；
Fig. 6 is shown based on the acquisition signal of plate card type multichannel data acquisition system of the invention to first group of signal source
Figure；
Fig. 7 is shown based on the acquisition signal of plate card type multichannel data acquisition system of the invention to second group of signal source
Figure；
Fig. 8 is shown based on the acquisition signal of plate card type multichannel data acquisition system of the invention to third group signal source
Figure.
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Embodiment
Fig. 1 is the specific embodiment flow chart of the synchronous method of plate card type multichannel data acquisition system of the present invention.Such as
Shown in Fig. 1, the specific steps of the synchronous method of plate card type multichannel data acquisition system of the present invention include:
S101: clock network building:
Fig. 2 is the structure chart of existing plate card type multichannel data acquisition system.As shown in Fig. 2, multi-pass in the prior art
Track data acquisition system includes multiple analog input cards, signal processing mainboard, host computer, display screen, wherein each analog input card pair
A channel is answered, the clock in analog input card is that the clock from clock, signal processing mainboard is master clock.In each collection plate
In card, analog signal carries out ADC module after signal conditioning module improves and is acquired, and input front end FPGA is pre-processed
Afterwards, signal processing mainboard is sent to by high-speed interface device.In signal processing mainboard, a card is configured to each analog input card
Slot data processing unit receives the data that analog input card uploads and is transmitted to rear end FPGA, and rear end FPGA is further processed
Host computer is sent to by high-speed communication interface afterwards to be processed and displayed.
In order to realize the synchronization of plate card type multichannel data acquisition system, master clock source is set in signal processing mainboard,
Setting is from clock source in each analog input card, and building obtains clock network in the following ways:
Master clock source generates reference clock signal CLK_MOUT, is divided into the road N+1, and N indicates plate card type multi-channel data acquisition
Number of channels in system, wherein the road N reference clock signal exports N number of card slot data processing list into signal processing mainboard
Member, when 1 road reference clock signal exports data processing synchronization of the rear end FPGA into signal processing mainboard as rear end FPGA
Clock.Each card slot data processing unit carries out clock transfer with the high-speed interface device in corresponding analog input card, and reference clock is believed
Number CLK_MOUT is transmitted to the slave clock source in corresponding analog input card.
In each analog input card, from clock source using reference clock signal CLK_MOUT as input, H is generatednWhen+2 tunnel
Clock signal CLK_SOUT, HnIndicate the quantity of ADC in n-th of analog input card, HnRoad clock exports the H into analog input card respectivelyn
Piece ADC is as acquisition reference clock, and 1 road clock is as transmission time domain reference clock, and 1 tunnel is as analog input card to signal processing master
The data transmission synchronization clock of plate.
S102: clock design:
Remember that reference clock frequency needed for ADC is f in N number of analog input cardADC_n, n=1,2 ..., N, analog input card to signal
The data transmission synchronization clock frequency of processing main plate is fM_SYNC, when the data processing of rear end FPGA is synchronous in signal processing mainboard
Clock is fSYS, then the frequency f of reference clock signal CLK_MOUTREFCalculation formula is as follows:
fREF≥max{fADC_1,fADC_2,…,fADC_N,fM_SYNC,fSYS}
Therefore the output frequency f of master clock source chipout, output number K should meet following relationship:
fout≥fREF
K≥N+1
N number of analog input card is used with model from clock source chip, clock output number L, clock input frequency fS_in, when
Clock output frequency fS_outFollowing relationship should be met:
L≥max{H1,H2,…,HN}+2
fS_in≥fREF
fS_out≥max{fADC_1,fADC_2,…,fADC_N}
Wherein, HnIndicate the quantity of ADC in n-th of analog input card.
In general, master and slave clock source chip should also have multipath clock output phase to adjust, dynamic delay is arranged, is defeated
The functions such as synchronous setting out.
Master and slave clock source parameter is determined according to above method, generates the control instruction of master and slave clock source.Except above-mentioned parameter
Other parameters in addition can be obtained by inquiry clock chip databook.
S103: critical clock paths PCB design:
When information processing mainboard carries out PCB design, need to enable the transmission line etc. of the road N+1 reference clock signal CLK_MOUT
It is long, enable the transmission line of the data line and reference clock signal CLK_MOUT between N number of analog input card and information processing mainboard
It is isometric.
When N number of analog input card carries out PCB design, need to enable the H exported in each analog input card from clock source chipn+2
Road clock signal clk _ SOUT transmission line and HnThe data line of a ADC to high quick access mouthpart is isometric.
When carrying out physical transmission line equal length treatment, the error of the long transmission lines such as every group should be kept in a certain range,
Error information can be obtained according to experiment.
S104: master and slave clock source is synchronous:
When plate card type multichannel data acquisition system is initialized, need to synchronize master and slave clock source.First
Need to establish the clock-reset link T of a N+2 fork treeCLOCK_RST, i.e., by tree root control terminal RSTNmainTwo class leaves of control
Control terminal RSTNMaster、RSTNslave_nReset link, tree root control terminal RSTNmainDirectly controlled by system host computer,
Leaf control terminal RSTNMasterAnd RSTNslave_nThe reseting port of master and slave clock source chip is controlled respectively, wherein RSTNMasterControl
The chip reset of master clock source processed, N number of RSTNslave_nControl chip reset of the road N from clock source.It is multiple to be then based on tree-shaped clock
Position link carries out master and slave clock source and synchronizes, and specific steps include:
S4.1: PC control RSTNMasterPrimary reset is executed to master clock source chip to operate.
S4.2: host computer according to step S102 master clock source control instruction generated to master clock source chip register into
Row configuration.
S4.3: the master clock source control instruction that host computer is generated according to step S102 synchronizes behaviour to master clock source chip
Make, waits for a period of time until the road the K clock output synchronization of master clock source, then carry out step S4.4.Waiting time can root
It is configured according to needs.
S4.4: host computer passes through N number of RSTNslave_nSlave clock chip in N number of acquisition slot is carried out while resetting behaviour
Make.
S4.5: the slave clock source control instruction that host computer is generated according to step S102 is same to carrying out from clock chip register
When configure.
S4.6: host computer synchronizes behaviour to from clock chip according to the slave clock source control instruction that step S102 is generated
Make, waits for a period of time until synchronous from the road the L clock output of clock source, master and slave clock synchronously completes.
S105: synchronous from clock source output clock:
When plate card type multichannel data acquisition system is initialized, need same to being carried out from the output clock of clock source
Step.The ADC for establishing a L fork tree resets link TADC_RST, acquired and synchronized by the ADC that the reset link transmission host computer is sent
Reset signal, ADC reset link TADC_RSTTree root control terminal RSTNADCBy PC control, L pitches the N number of multiple of leaf control terminal
Position signal RSTNADC_nThe ADC synchronous acquisition port in N number of analog input card is forwarded to by synchronously control special purpose interface.Then base
It resets link in the ADC synchronize from clock source output clock, specific steps include:
S5.1: after waiting master and slave clock synchronism stability to export, believed by the reset terminal of the N number of analog input card of PC control
Number RSTNADC_n, complete once to reset operation for the concentration of N number of analog input card.
S5.2: host computer synchronizes operation to ADC according to the preset method of synchronization, waits for a period of time until all
ADC completes to synchronize.
S106: acquisition data buffer storage:
One front end is set before the high-speed interface device of analog input card and transmits adjustment cache module, in plate card type multichannel
When data collection system carries out data acquisition, before data are uploaded to signal processing mainboard from analog input card, transmitted by front end
It adjusts cache module and cross clock domain conversion is carried out to data, data clock is converted to data transmission synchronization clock.
S107: the synchronous of data back-end receives and shows:
The data that configuration data storage FIFO uploads analog input card in the rear end FPGA of signal processing mainboard connect
Caching is received, the read-write clock of data storage FIFO is the data processing synchronised clock of rear end FPGA, and data store the reading of FIFO
Control terminal is write by the DMA transfer mechanism control of rear end FPGA and host computer, host computer is using DMA mechanism from data storage FIFO
Read the simultaneous display that data carry out waveform.
Technical solution in order to better illustrate the present invention, using specific plate card type multi-channel data acquisition shown in Fig. 2
System is illustrated.Plate card type multichannel data acquisition system in the present embodiment includes 8 analog input cards, i.e. N=8.
Each analog input card include a signal conditioning module, 2 ADC, front end FPGA, from clock source, interface unit.First, in accordance with step
Method in S101 carries out clock network building, designs followed by clock.
Maximum reference clock frequency needed for ADC in the present embodiment in 8 analog input cards is 100MHz, and analog input card arrives
The data transmission synchronization clock frequency of signal processing mainboard is the clock frequency 200M in high-speed transmission interface, signal processing mainboard
The data processing synchronised clock of middle rear end FPGA is 100MHz, then the frequency of reference clock signal CLK_MOUT is according to fREFMeter
Formula is calculated to seek that f can be obtainedREF=200M.Therefore master clock source chip exports the clock that 9 tunnel frequencies are 200MHz in the present embodiment
CLK_MOUT。
It include 2 ADC by each analog input card in this present embodiment, therefore from the output number L=4 of clock source chip,
From the frequency f of clock source chip input clock CLK_MOUTs_in=200M, the frequency f of the clock CLK_SOUT of outputs_out=
100M。
According to requirements above, selects master clock source and the model from clock source is respectively LMK04806 and LMK01010.
Critical clock paths PCB design is carried out according to the method in step S103, even 9 tunnels is enabled to join in information processing mainboard
Examine that clock signal clk _ MOUT transmission line is isometric, enable data line between 8 analog input cards and information processing mainboard with
The transmission line of reference clock signal CLK_MOUT is isometric.
When N number of analog input card carries out PCB design, need to enable in each analog input card from 4 tunnels that clock source chip exports
Clock signal clk _ SOUT transmission line and the data line of 2 ADC to interface units are isometric.
After the booting of plate card type multichannel data acquisition system, the front end FPGA success loading procedure in acquisition module is waited
Afterwards, to carry out master and slave clock source using step S104 and the two-stage tree-shaped clock-reset link in step S105 synchronous and from clock
It is synchronous that source exports clock.Then the initialization for carrying out system modules, controls each shelves by way of host computer traversal queries
External signal, is processed into the signal for meeting ADC range by the decaying and gain of position by signal conditioning module.In the present embodiment
In, the synchronizing channel number is 128, analog-digital converter model AD96XX used, and analog acquisition channel is 2, according to Working mould
The demand of formula configures ADC, and ADC is waited to complete synchronous acquisition work.
After the completion of waiting the acquisition of multi pass acquisition board data, data flow needs to carry out data by High Speed Data Transfer Protocol
Move.The present invention is to be the data flow for enabling the road N high-speed ADC export in output to the purpose of the clock design of analog input card
Data time domain afterwards needs to be synchronized under the fast clock of High Speed Data Transfer Protocol used and the time domain of slow clock.In the present embodiment
It is middle that rate is selected to transmit for SERDES (1:4DDR200Mhz mode) agreement of 3.2Gbps to the data flow of channel ADC,.
Front end before entering high-speed interface device as acquisition data using a FIFO stack in the present embodiment passes
Defeated adjustment cache module carries out cross clock domain conversion to data, data clock is converted to data transfer clock.The present embodiment
In, the resolution ratio of ADC is 16bits, and it is 32bits that twin-channel veneer, which integrates output stream, therefore front end transmission adjustment is slow
Buffer module uses storage depth for the asynchronous FIFO of 32bits*1K, is flowed into using the FIFO to a large amount of and high speed adc data
Workspace cache and synchronous adjustment caching under line asynchronous time domain.The operating mode of above-mentioned FIFO is configured to read while write, is inputted
Output bit wide is 32bit, and the read-write clock end for configuring FIFO is the timing parameter of value not same area together.In the present embodiment, FIFO
Data write the acquisition reference clock that clock selecting is ADC output, the data of FIFO read clock selecting and transmit time domain reference clock,
The frequency of two clocks is all 100Mhz, and the output stream handled by asynchronous FIFO is made in entire transmission process
Fast clock is the 1 circuit-switched data transmission clock that clock source exports in step S1, as used in data stream transmitting in this present embodiment
SERDES agreement uses speed clock, therefore data transfer clock needs to handle through locking phase, and enabling its frequency is 200Mhz.
Finally when data back-end is received and is shown, it is synchronous that clock is carried out using the method in step S108.
In order to illustrate technical effect of the invention, 4 analog input cards are configured in plate card type multichannel data acquisition system,
Verifying comparison is carried out to the technology using 3 groups of signals of homologous output based on existing synchronous method and synchronous method of the present invention, wherein
First group of square wave display figure acquired simultaneously by 4 analoglike channels respectively for the different homologous output signal in 4 tunnels of amplitude, second group
Figure is shown by the sine wave that 4 analoglike channels acquire simultaneously respectively for the different homologous output signal in 4 tunnels of amplitude, third group is pair
Second group of acquisition signal carries out the signal acquisition effect picture of more high bandwidth.
Fig. 3 is that the plate card type multichannel data acquisition system based on existing synchronous method believes the acquisition of first group of signal source
Number display figure.Fig. 4 is acquisition of the plate card type multichannel data acquisition system based on existing synchronous method to second group of signal source
Signal display figure.Fig. 5 is that the plate card type multichannel data acquisition system based on existing synchronous method adopts third group signal source
Collect signal display figure.
Fig. 6 is shown based on the acquisition signal of plate card type multichannel data acquisition system of the invention to first group of signal source
Figure.Fig. 7 is the acquisition signal display figure based on plate card type multichannel data acquisition system of the invention to second group of signal source.Figure
8 be the acquisition signal display figure based on plate card type multichannel data acquisition system of the invention to third group signal source.
Display figure is corresponded to Fig. 3 to Fig. 8 to be compared it is found that the present invention is equal for different frequency, different types of signal
With good net synchronization capability, synchronization accuracy, which complies fully with, develops index Design precision.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (1)
1. a kind of synchronous method of plate card type multichannel data acquisition system, which comprises the following steps:
S1: master clock source is set in the signal processing mainboard of plate card type multichannel data acquisition system, in each analog input card
Middle setting is from clock source, and building obtains clock network in the following ways:
Master clock source generates reference clock signal CLK_MOUT, is divided into the road N+1, and N indicates plate card type multichannel data acquisition system
In number of channels, wherein the road N reference clock signal exports N number of card slot data processing unit into signal processing mainboard, 1 tunnel
Reference clock signal exports data processing synchronised clock of the rear end FPGA into signal processing mainboard as rear end FPGA；Each
Card slot data processing unit carries out clock transfer with the high-speed interface device in corresponding analog input card, by reference clock signal CLK_
MOUT is transmitted to the slave clock source in corresponding analog input card；
In each analog input card, from clock source using reference clock signal CLK_MOUT as input, H is generatedn+ 2 tunnel clock signals
CLK_SOUT, HnIndicate the quantity of ADC in n-th of analog input card, HnRoad clock exports the H into analog input card respectivelynPiece ADC
As acquisition reference clock, 1 road clock is as transmission time domain reference clock, and 1 tunnel is as analog input card to signal processing mainboard
Data transmission synchronization clock；
S2: remember that reference clock frequency needed for ADC is f in N number of analog input cardADC_n, n=1,2 ..., N, analog input card to signal
The data transmission synchronization clock frequency of processing main plate is fM_SYNC, when the data processing of rear end FPGA is synchronous in signal processing mainboard
Clock is fSYS, then the frequency f of reference clock signal CLK_MOUTREFCalculation formula is as follows:
fREF≥max{fADC_1,fADC_2,…,fADC_N,fM_SYNC,fSYS}
The output frequency f of master clock source chipout, output number K should meet following relationship:
fout≥fREF
K≥N+1
N number of analog input card is used with model from clock source chip, clock output number L, clock input frequency fS_in, clock it is defeated
Frequency f outS_outFollowing relationship should be met:
L≥max{H1,H2,…,HN}+2
fS_in≥fREF
fS_out≥max{fADC_1,fADC_2,…,fADC_N}
Master and slave clock source parameter is determined according to above method, generates the control instruction of master and slave clock source；
S3: when information processing mainboard carries out PCB design, need to enable the transmission line etc. of the road N+1 reference clock signal CLK_MOUT
It is long, enable the transmission line of the data line and reference clock signal CLK_MOUT between N number of analog input card and information processing mainboard
It is isometric；
When N number of analog input card carries out PCB design, need to enable the H exported in each analog input card from clock source chipnWhen+2 tunnel
The transmission line and H of clock signal CLK_SOUTnThe data line of a ADC to high quick access mouthpart is isometric；
S4: when plate card type multichannel data acquisition system is initialized, master and slave clock source is synchronized, is initially set up
The clock-reset link T of one N+2 fork treeCLOCK_RST, i.e., by tree root control terminal RSTNmainTwo class leaf control terminals of control
RSTNMaster、RSTNslave_nReset link, tree root control terminal RSTNmainIt is directly controlled by system host computer, leaf control
End RSTN processedMasterAnd RSTNslave_nThe reseting port of master and slave clock source chip is controlled respectively, wherein RSTNMasterWhen controlling main
The chip reset of Zhong Yuan, N number of RSTNslave_nControl chip reset of the road N from clock source；It is then based on tree-shaped clock-reset link
It is synchronous to carry out master and slave clock source, specific steps include:
S4.1: PC control RSTNMasterPrimary reset is executed to master clock source chip to operate；
S4.2: host computer matches master clock source chip register according to step S2 master clock source control instruction generated
It sets；
S4.3: the master clock source control instruction that host computer is generated according to step S2 synchronizes operation to master clock source chip, etc.
To a period of time until the road the K clock output of master clock source is synchronous, subsequently into step S4.4；
S4.4: host computer passes through N number of RSTNslave_nSlave clock chip in N number of acquisition slot is carried out while resetting operation；
S4.5: the slave clock source control instruction that host computer is generated according to step S2 carries out while matching to from clock chip register
It sets；
S4.6: host computer synchronizes operation to from clock chip according to the slave clock source control instruction that step S2 is generated, and waits
A period of time, master and slave clock synchronously completed until synchronous from the road the L clock output of clock source；
S5: when plate card type multichannel data acquisition system is initialized, synchronizing to from the output clock of clock source, first
The ADC for first establishing a L fork tree resets link TADC_RST, acquired and synchronized by the ADC that the reset link transmission host computer is sent
Reset signal, ADC reset link TADC_RSTTree root control terminal RSTNADCBy PC control, L pitches the N number of multiple of leaf control terminal
Position signal RSTNADC_nThe ADC synchronous acquisition port in N number of analog input card is forwarded to by synchronously control special purpose interface；Then base
It resets link in the ADC synchronize from clock source output clock, specific steps include:
S5.1: after waiting master and slave clock synchronism stability to export, pass through the reset end signal of the N number of analog input card of PC control
RSTNADC_n, complete once to reset operation for the concentration of N number of analog input card；
S5.2: host computer synchronizes operation to ADC according to the preset method of synchronization, waits for a period of time until all ADC are complete
At synchronization；
S6: a front end is set before the high-speed interface device of analog input card and transmits adjustment cache module, in plate card type multichannel
When data collection system carries out data acquisition, before data are uploaded to signal processing mainboard from analog input card, transmitted by front end
It adjusts cache module and cross clock domain conversion is carried out to data, data clock is converted to data transmission synchronization clock；
S7: the data that configuration data storage FIFO uploads analog input card in the rear end FPGA of signal processing mainboard receive
The read-write clock of caching, data storage FIFO is the data processing synchronised clock of rear end FPGA, and data store the read-write of FIFO
Control terminal by rear end FPGA and host computer DMA transfer mechanism control, host computer using DMA mechanism from data storage FIFO in read
Access is according to the simultaneous display for carrying out waveform.
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| CN110543121A (en) * | 2019-08-30 | 2019-12-06 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Instruction synchronous distribution control device of full-digital phased array system |
| CN111077498A (en) * | 2019-11-28 | 2020-04-28 | 北京航天控制仪器研究所 | Synchronous signal acquisition and processing device based on optical fiber hydrophone array |
| CN111865467A (en) * | 2020-07-20 | 2020-10-30 | 深圳市风云实业有限公司 | Clock synchronization system and method between distributed chassis board cards for time delay test |
| CN113472969B (en) * | 2021-06-08 | 2022-05-10 | 苏州华兴源创科技股份有限公司 | Multichannel link synchronization control method and device and video image processing equipment |
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| CN206711081U (en) * | 2017-04-07 | 2017-12-05 | 华中师范大学 | A kind of multi-channel high-speed serial data collection system based on simultaneous techniques |
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