CN109062858A - A kind of FPGA accelerator card based on Xilinx XCVU37P chip - Google Patents
A kind of FPGA accelerator card based on Xilinx XCVU37P chip Download PDFInfo
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- CN109062858A CN109062858A CN201810861508.9A CN201810861508A CN109062858A CN 109062858 A CN109062858 A CN 109062858A CN 201810861508 A CN201810861508 A CN 201810861508A CN 109062858 A CN109062858 A CN 109062858A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention provides a kind of FPGA accelerator cards, comprising: Xilinx XCVU37P chip, built-in chip type HBM；And it is external in the external high-speed memory of Xilinx XCVU37P chip；Wherein the data from CPU are transferred to Xilinx XCVU37P chip by PCIE and synchronize caching and format conversion, and data are stored in HBM and external high-speed memory；Then data are transferred back into CPU through PCIE again to carry out subsequent processing.The memory access bandwidth of FPGA accelerator card of the invention not will receive the limitation of device I/O pin number, also avoids buffering access and the consistency problem of big power consumption, reduces the delay of read-write, so that reading and writing data speed is faster.
Description
Technical field
Present invention relates in general to field of computer technology, and are based on Xilinx more particularly, to one kind
The FPGA accelerator card of XCVU37P chip.
Background technique
Nowadays the operations such as coding and decoding, data compression and storage, encryption become increasingly complex, and need the processing capacity of processor
It is higher and higher.Conventional processors itself have been unable to satisfy the performance requirement of high-performance calculation (HPC) application software, cause demand and
Occur notch between performance, improving processor performance is not the unique method for solving application demand, using application specific processor come
Extensible processor is always the reliable approach for solving performance bottleneck.FPGA (Field Programmable Gate Array, it is existing
Field programmable gate array) basis as co-processor design, have significantly in price, performance, ease for use and power consumption
Advantage.
The patent of application number 201510672954 proposes a kind of FPGA accelerator card high-speed memory system, including PCIE
(Peripheral Component Interconnect Express, high speed serialization device interconnection) stone module, FPGA
Module and DDR3 (Double-Data-Rate SDRAM, Double Data Rate synchronous DRAM) memory module；Wherein,
The FPGA module is used to synchronizing data to be stored into caching and format is converted, and will be described in data to be stored deposit
DDR3 memory module, the DDR3 memory module are high-speed high capacity caching；The PCIE stone module passes through I/O interface and institute
The interface for stating DDR3 memory module is connected, in a manner of direct memory access by the data to be stored high-speed uploading to being
In system memory, to carry out subsequent processing.The present invention, as control centre, is realized by FPGA with the PCIE stone provided in FPGA
High speed DMA (Direct Memory Access, direct memory access) read-write, while using DDR3 as large capacity cache, have
Higher data bandwidth and good performance.
But the above method is limited in that, stores equipment relative to DDR4, DDR3 store equipment consume more power consumptions,
Running frequency is lower, capacity is also restricted.In addition, the storage equipment of FPGA leans on external memory, the access bandwidth of memory entirely
It will receive the limitation of device I/O quantity, can also consume part power consumption and go to solve buffering access and consistency.
Summary of the invention
In view of above-mentioned purpose, the purpose of the embodiment of the present invention is to propose that a kind of FPGA accelerator card, the accelerator card are selected
Xilinx XCVU37P chip caches (HBM) by the high bandwidth of the built-in chip type, solves the access bandwidth receiver of memory
The problem of part I/O quantity limits.
Based on above-mentioned purpose, the embodiment of the invention provides a kind of FPGA accelerator cards, comprising:
Xilinx XCVU37P chip, Xilinx XCVU37P built-in chip type HBM (the High Bandwidth
Memory, high bandwidth video memory)；And
External high-speed memory, the external memory are external in the Xilinx XCVU37P chip；
Wherein, the data from CPU (Central Processing Unit, central processing unit) are transferred to by PCIE
The Xilinx XCVU37P chip synchronizes caching and format and converts, and the data are stored in the HBM and described outer
Portion's high-speed memory；Then the data are transferred back into the CPU through the PCIE again to carry out subsequent processing.
In some embodiments, the external high-speed memory is DDR4 SDRAM.
In some embodiments, the DDR4 SDRAM in external 3 channel of the Xilinx XCVU37P chip, each
There is the DDR4 SDRAM of 5 16Gb in the channel.
In some embodiments, the FPGA accelerator card further includes 2 QSFP28+, and 2 QSFP28+ can make 2 pieces
It is interacted between the FPGA accelerator card, to realize that one of FPGA accelerator card carries out that another FPGA is assisted to add
The operation of speed card.
In some embodiments, 2 QSFP28+ pass through QSFP (Quad Small Form-factor
Pluggable, four-way small pluggable interface) agreement carries out acceleration interaction.
In some embodiments, the DDR4 SDRAM reaches 80bit Data+ECC structure, and wherein 72bit is for counting
According to transmission, 8bit is used for ECC (error checking and correction).
In some embodiments, the FPGA accelerator card further includes 2 QSPI FLASH, to configure the Xilinx
The initial configuration information of XCVU37P chip pin.
In some embodiments, the FPGA accelerator card based on Xilinx XCVU37P chip is designed in half long overall height
Standard PCIe card on.
In some embodiments, the FPGA accelerator card based on Xilinx XCVU37P chip is designed in overall length overall height
Standard PCIe card on.
In some embodiments, the external high-speed memory is memory bar.
The present invention has following advantageous effects: the FPGA provided by the invention based on Xilinx XCVU37P chip adds
Speed card selects Xilinx XCVU37P as main chip, using the built-in high bandwidth video memory (HBM) of XCVU37P itself, so that
The memory access bandwidth of coprocessor not will receive the limitation of device I/O pin number, and memory and arithmetic logic are tight
Close combination needs not move through external high-speed memory buffering, also avoids buffering access and the consistency problem of big power consumption in this way；
External connection high-speed memory realizes that optimal storage and memory capacity maximize；And by QSFP28+, realize FPGA it
Between high speed interconnection, improve the computing capability of FPGA.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of the FPGA accelerator card according to the present invention based on Xilinx XCVU37P chip；
Fig. 2 is to realize the schematic diagram interconnected between 2 pieces of FPGA accelerator cards by QSFP28+.
Specific embodiment
The following describe embodiment of the disclosure.It should be appreciated, however, that the disclosed embodiments are only example, and
Other embodiments can take various alternative forms.The drawings are not necessarily drawn to scale；Certain functions may be exaggerated or minimum
Change the details to show particular elements.Therefore, specific structure and function details disclosed herein are not necessarily to be construed as restrictive,
And it is merely possible to for instructing those skilled in the art to use representative basis of the invention in various ways.As this field is general
It is logical the skilled person will understand that, the various features with reference to shown or described by any one attached drawing can with it is one or more other
Feature shown in the drawings is combined to produce the embodiment for not being explicitly illustrated or describing.The group of shown feature is combined into typical case
Provide representative embodiment.However, the various combinations and modification of the feature consistent with the introduction of the disclosure are for certain spies
Fixed application or embodiment may be desired.
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
The embodiment of the present invention is further described in attached drawing.
In order to solve the access that storage equipment in FPGA accelerator card in the prior art leans on external memory, memory entirely
The problem of bandwidth is limited by device I/O quantity proposes a kind of FPGA accelerator card based on Xilinx XCVU37P chip.
Xilinx XCVU37P chip is a FPGA device of Xilinx company of U.S. exploitation, supports full speed 460Gbytes/sec's
Bandwidth communication, its resource are as follows: 2852K system logic unit；9Mbits BRAM resource；The UltraRAM of 270Mbits is provided
Source；9024 DSP48E2 slices；Integrated 8GB HBM DRAM；96Gbps and 32.75Gbps GTY SerDes transceiver.
There is apparent advantage on basis of the FPGA as co-processor design in price, performance, ease for use and power consumption.The present invention
The crucial processing function needed in the dedicated hardware-accelerated various applications of realization is provided；Co-processor design is very clever in performance
It is living, using assembly line and parallel organization, keep up with the changes in demand of performance；Coprocessor can be primary processor and system storage
Broadband, low latency interface are provided.
As shown in Figure 1, providing FPGA accelerator card according to an embodiment of the invention, Xilinx is selected
XCVU37P chip, this built-in chip type high bandwidth video memory (HBM), capacity is up to 64Gb.The internal memory of FPGA also has very big
Performance advantage, the memory access bandwidth of coprocessor not will receive the limitation of device I/O pin number, and memory and fortune
It calculates logic to combine closely, needs not move through external high-speed memory buffering, also avoid the buffering access and one of big power consumption in this way
Cause property problem, reduces the delay of read-write, so that reading and writing data speed is faster.
In addition, according to some embodiments of the present invention, on the FPGA accelerator card, Xilinx XCVU37P chip external 3
The DDR4 SDRAM in channel is as external high-speed memory.In some embodiments, there are 5 16Gb DDR4 in each channel
SDRAM, 15 DDR4 SDRAM, memory capacity can reach 30GB in total.
In some embodiments, external DDR4 SDRAM can reach 80bit Data+ECC structure, and wherein 72bit is used for
Data transmission, 8bit are used for ECC.High-speed memory can be improved FPGA computing capability outside the DDR4 SDRAM, assist FPGA
Accelerate operation.
According to some embodiments of the present invention, the FPGA accelerator card further includes 2 QSPI FLASH, for configuring
The initial configuration information of Xilinx XCVU37P chip pin is to start Xilinx XCVU37P chip.Wherein from CPU's
Data are transferred to Xilinx XCVU37P chip by PCIE and synchronize caching and format conversion, and the data are stored in HBM
With external high-speed memory；Then the data are transferred back into CPU through PCIE again to carry out subsequent processing.
According to one embodiment of present invention, FPGA accelerator card further includes 2 QSFP 28+, as shown in Fig. 2, this 2
QSFP 28+ passes through QSFP agreement, it can be achieved that the high speed between two pieces of FPGA accelerator cards is interconnected to interact.Two are used in this way
Block FPGA accelerator card, one of FPGA assist another FPGA to carry out operation.Through actually detected, in this double FPGA accelerator card
Embodiment in, integral operation ability is significantly improved.
FPGA accelerator card according to the present invention can design on the standard PCIe card of half long overall height, occupy minimum space
Maximized memory technology is realized simultaneously and accelerates application.Certainly meeting other hardware settings of the invention is also possible, example
As FPGA accelerator card of the invention can design on the standard PCIe card of overall length overall height, DDR4 SDRAM is changed to memory bar side
Case, etc..
Technically in feasible situation, it can be combined with each other above in relation to technical characteristic cited by different embodiments,
Or change, add and omit etc., to form the additional embodiment in the scope of the invention.
From above-described embodiment as can be seen that the embodiment of the invention provides the FPGA based on Xilinx XCVU37P chip to add
Speed card, this built-in chip type high bandwidth video memory (HBM), capacity is up to 64Gb, and memory access bandwidth not will receive device I/O at this time
The limitation of pin number, and memory and arithmetic logic are combined closely, and need not move through external high-speed memory buffering, in this way
Buffering access and the consistency problem for also avoiding big power consumption, reduce the delay of read-write, so that reading and writing data speed is faster；Separately
Outside, using external high-speed memory, FPGA computing capability is improved, auxiliary FPGA accelerates operation；Separately there are 2 QSFP 28+, it can be real
High speed interconnection between existing two pieces of FPGA boards.FPGA accelerator card according to the present invention is realized maximum while occupying minimum space
The memory technology and acceleration application of change.
It should be understood by those ordinary skilled in the art that: the discussion of any of the above embodiment is exemplary only, not
It is intended to imply that range disclosed by the embodiments of the present invention (including claim) is limited to these examples；In the think of of the embodiment of the present invention
Under road, it can also be combined between the technical characteristic in above embodiments or different embodiments, and exist as described above
Many other variations of the different aspect of the embodiment of the present invention, for simplicity, they are not provided in details.Therefore, all at this
Within the spirit and principle of inventive embodiments, any omission, modification, equivalent replacement, improvement for being made etc. should be included in this hair
Within the protection scope of bright embodiment.
It should be understood that it is used in the present context, unless the context clearly supports exceptions, singular " one
It is a " it is intended to also include plural form.It is to be further understood that "and/or" used herein refers to including one or one
Any and all possible combinations of a above project listed in association.The embodiments of the present invention disclose embodiment sequence number only
Only for description, do not represent the advantages or disadvantages of the embodiments.
In addition, the present disclosure is not limited to so retouch although having been described and illustrating the specific embodiment of the disclosure
The concrete form or arrangement for the part stated and illustrated.The scope of the present disclosure is by the attached claims, this paper and different
Any jus futurum requirement submitted in application and its equivalency range limit.
Claims (10)
1. a kind of FPGA accelerator card, comprising:
Xilinx XCVU37P chip, the Xilinx XCVU37P built-in chip type HBM；And
External high-speed memory, the external memory are external in the Xilinx XCVU37P chip；
Wherein, the data from CPU are transferred to the Xilinx XCVU37P chip by PCIE and synchronize caching and format
Conversion, and the data are stored in the HBM and the external high-speed memory；Then the data are transmitted through the PCIE again
The CPU is returned to carry out subsequent processing.
2. FPGA accelerator card according to claim 1, which is characterized in that the external high-speed memory is DDR4
SDRAM。
3. FPGA accelerator card according to claim 2, which is characterized in that the Xilinx XCVU37P chip external 3 is logical
There is the DDR4 SDRAM of 5 16Gb in the DDR4 SDRAM in road, each channel.
4. FPGA accelerator card according to claim 1, which is characterized in that the FPGA accelerator card further includes 2 QSFP28
+, 2 QSFP28+ can make to interact between 2 pieces of FPGA accelerator cards, to realize that one of FPGA accelerates
Card assists the operation of another FPGA accelerator card.
5. FPGA accelerator card according to claim 4, which is characterized in that 2 QSFP28+ are carried out by QSFP agreement
Accelerate interaction.
6. FPGA accelerator card according to claim 3, which is characterized in that the DDR4 SDRAM reaches 80bit Data+
ECC structure, wherein 72bit is transmitted for data, and 8bit is used for ECC.
7. FPGA accelerator card according to claim 1, which is characterized in that the FPGA accelerator card further includes 2 QSPI
FLASH, to configure the initial configuration information of the Xilinx XCVU37P chip pin.
8. FPGA accelerator card according to claim 1, which is characterized in that described based on Xilinx XCVU37P chip
FPGA accelerator card designs on the standard PCIe card of half long overall height.
9. FPGA accelerator card according to claim 1, which is characterized in that described based on Xilinx XCVU37P chip
FPGA accelerator card designs on the standard PCIe card of overall length overall height.
10. FPGA accelerator card according to claim 1, which is characterized in that the external high-speed memory is memory bar.
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