CN109039487B - Short wave prognosis selector internal self-checking system - Google Patents
Short wave prognosis selector internal self-checking system Download PDFInfo
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- CN109039487B CN109039487B CN201811052332.9A CN201811052332A CN109039487B CN 109039487 B CN109039487 B CN 109039487B CN 201811052332 A CN201811052332 A CN 201811052332A CN 109039487 B CN109039487 B CN 109039487B
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- 238000004393 prognosis Methods 0.000 title claims abstract description 22
- 238000006243 chemical reaction Methods 0.000 claims abstract description 75
- 238000012360 testing method Methods 0.000 claims abstract description 47
- 238000007493 shaping process Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 22
- 230000005540 biological transmission Effects 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 238000013461 design Methods 0.000 abstract description 7
- 238000001514 detection method Methods 0.000 description 19
- 238000002955 isolation Methods 0.000 description 10
- 238000001914 filtration Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
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- 239000000463 material Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/15—Performance testing
- H04B17/19—Self-testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/713—Spread spectrum techniques using frequency hopping
- H04B1/7136—Arrangements for generation of hop frequencies, e.g. using a bank of frequency sources, using continuous tuning or using a transform
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
- H04B17/29—Performance testing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K5/00—Casings, cabinets or drawers for electric apparatus
- H05K5/04—Metal casings
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Abstract
The invention relates to an internal self-checking system of a short-wave prognosis selector, which comprises an FPGA control circuit and a pre/post selector filter circuit electrically connected with the FPGA control circuit; the FPGA control circuit is electrically connected with the external short-wave radio station main control unit through a control interface; the method is characterized in that: the self-checking system further comprises a self-checking signal shaping circuit, a conversion circuit and a self-checking signal testing circuit which are electrically connected with the FPGA control circuit. The internal self-checking system of the short wave pre/post selector has the advantages of simple and reasonable structural design, small volume, low cost, high speed, high reliability, high frequency hopping speed, low power consumption, low noise, good frequency selectivity, stable and reliable operation and capability of effectively improving the technical index and the electromagnetic compatibility of a short wave radio station.
Description
Technical Field
The invention belongs to the technical fields of automatic control, quality detection, isolation technology, frequency hopping and spread spectrum in a modern short wave communication system, and particularly relates to an internal self-checking system of a short wave pre/post selector.
Background
Today electromagnetic signals are increasingly dense and complex, and the demands on the anti-interference capability of communication countermeasure devices are increasing. The short wave frequency hopping radio station is used as a new generation of communication countermeasure equipment, has stronger anti-interference and anti-interception capability, and has great superiority in modern electronic warfare. Short wave pre/post-selectors are key elements developed for new generation communication countermeasure equipment. Wherein: the preselector is arranged at the front end of the radio receiver, and is used for filtering useless signals outside the working frequency band and improving the signal-to-noise ratio; the post selector is arranged at the front end of the power amplifier of the transmitter, filters out harmonic waves outside the working frequency band and reduces the radiation interference. An important component of the short wave pre/post-selector is a digitally tuned frequency hopping filter. The digital tuning frequency hopping filter comprises 136 resonant circuits, 750 filter channels are formed, the quality of each channel of the filter is directly related to the quality of communication, and a self-checking circuit is added in the design of products, so that problems can be found in time, and faults can be removed. Therefore, the method has very important significance.
Testing of filters has been largely dependent on vector network analyzers. The vector network analyzer can accurately test various technical indexes of the filter, but has the advantages of high price, huge volume and inconvenient carrying, and particularly, the filter needs to be disconnected from a link for measurement and cannot be used for real-time fault detection of the filter.
Disclosure of Invention
Aiming at the problems in the background technology, the invention provides the short wave prognosis selector internal self-checking system which has the advantages of simple and reasonable structural design, real-time fault detection capability, small volume, low cost, high speed and strong anti-interference capability, can effectively realize the rapid checking and accurate analysis of the performance of each channel of the pre/post selector, and has important significance for timely locking the fault channel.
The technical scheme of the invention is as follows:
the internal self-checking system of the short-wave prognosis selector comprises an FPGA control circuit and a pre/post selector filter circuit electrically connected with the FPGA control circuit; the FPGA control circuit is electrically connected with the external short-wave radio station main control unit through a control interface; the self-checking system further comprises a self-checking signal shaping circuit, a conversion circuit and a self-checking signal testing circuit which are electrically connected with the FPGA control circuit;
the self-checking signal shaping circuit comprises a voltage reducing circuit, a radio follower and a n-type network; the input end of the voltage reduction circuit is electrically connected with the output end of the FPGA control circuit, and the output end of the voltage reduction circuit is electrically connected with the input end of the emitter follower; the output end of the emitter follower is electrically connected with the input end of the pi-shaped network, and the output end of the pi-shaped network is electrically connected with the conversion circuit;
the conversion circuit comprises a first conversion circuit and a second conversion circuit which are identical in structure; the first conversion circuit and the second conversion circuit are electrically connected with the FPGA control circuit; the first conversion circuit is also electrically connected with the output end of the pi-type network, the radio frequency input end of the preselector and the input end of the pre/post selector filter circuit respectively; the second conversion circuit is also electrically connected with the output end of the pre/post selector filter circuit, the radio frequency output end of the pre-selector and the self-checking signal testing circuit respectively;
the self-checking signal testing circuit comprises an RF logarithmic detector and a voltage comparator; the input end of the RF logarithmic detector is electrically connected with the second conversion circuit, and the output end of the RF logarithmic detector is electrically connected with the input end of the voltage comparator; and the output end of the voltage comparator is electrically connected with the FPGA control circuit.
The inside self-checking system of short wave prognosis selector, wherein: the FPGA control circuit receives serial data instructions sent by the short-wave radio station main control unit and converts the serial data instructions into 13-bit parallel control code instructions, the pre/post selector filter circuit is controlled by 10-bit frequency control codes respectively, the self-checking function of the pre/post selector, the pre-selector and the conversion among the post-selector are controlled by 3-bit control codes, so that the transmission of carrier signals of different frequency points is realized, the carrier frequency of useful signals is rapidly switched, and the self-checking function is realized; the FPGA control circuit is an XC3S200A circuit, and after receiving a serial control command of the control device, the FPGA control circuit converts a serial data command into 13-bit parallel codes P0-P9 and K1-K3, wherein P0-P9 are frequency control codes, and K1-K3 are receiving-transmitting and self-checking control codes.
The inside self-checking system of short wave prognosis selector, wherein: the first conversion circuit and the second conversion circuit are controlled by control ends K2 and K3 of the FPGA control circuit; the first conversion circuit is electrically connected with the output end of the pi-type network through a pin 8, is electrically connected with the radio frequency input end of the preselector through a pin 5, is electrically connected with the control end K2 of the FPGA control circuit through a pin 2, is electrically connected with the control end K3 of the FPGA control circuit through a pin 4, and is electrically connected with the input end of the pre/post selector filter circuit through a pin 3; the second conversion circuit is electrically connected with the output end of the pre/post selector filter circuit through a pin No. 3, is electrically connected with the radio frequency output end of the pre-selector through a pin No. 5, is electrically connected with the control end K2 of the FPGA control circuit through a pin No. 2, is electrically connected with the control end K3 of the FPGA control circuit through a pin No. 4, and is electrically connected with the input end of the RF logarithmic detector through a pin No. 8.
The inside self-checking system of short wave prognosis selector, wherein: the pre/post selector filter circuit is controlled by control codes P0-P9 and K1 of the FPGA control circuit; the FPGA control circuit controls the selection of a pre-selector receiving channel and a post-selector sending channel of the pre-selector/post-selector filter circuit through a K1 control end, namely, when the control end K1 of the FPGA control circuit is at a high level, the pre-selector filter circuit is connected, and when the control end K1 of the FPGA control circuit is at a low level, the post-selector filter circuit is connected.
The inside self-checking system of short wave prognosis selector, wherein: the pre/post selector filter circuit comprises a digital tuning frequency hopping filter, a first transceiver conversion circuit, a second transceiver conversion circuit and an amplifying circuit; the preselector and the post selector share the digital tuning frequency hopping filter; the frequency hopping speed of the digital tuning frequency hopping filter is less than or equal to 1000 mu s, the self-checking test time is about 1.2s, and the signal input end of the digital tuning frequency hopping filter is connected with the output end of the first transceiver conversion circuit; the signal output end of the digital tuning frequency hopping filter is connected with the input end of the second transceiver conversion circuit; the output end of the second transceiver converting circuit is connected with the No. 3 pin of the second converting circuit, the input end of the first transceiver converting circuit is connected with the output end of the amplifying circuit, and the input end of the amplifying circuit is connected with the No. 3 pin of the first converting circuit.
The inside self-checking system of short wave prognosis selector, wherein: the first transceiver conversion circuit and the second transceiver conversion circuit are SPDT radio frequency switches; the digital tuning frequency hopping filter comprises 136 resonant circuits, and 750 filters are formed.
The inside self-checking system of short wave prognosis selector, wherein: the input end of the RF logarithmic detector is electrically connected with the No. 8 pin of the second conversion circuit; the output end of the voltage comparator is electrically connected with the control end K4 of the FPGA control circuit; the RF logarithmic detector is formed by connecting a detector AD8318, capacitors C1-C2 and resistors R1-R3, the voltage comparator is formed by connecting an operational amplifier MAX4122, a capacitor C3 and resistors R4-R6, and the resistor R5 is an adjustable resistor; one end of the capacitor C1 is connected with the No. 8 pin of the second conversion circuit, and the other end of the capacitor C1 is connected with the pin INHI of the detector AD 8318; one end of the capacitor C2 is connected with the resistor R1 and is connected with the No. 8 pin of the second conversion circuit through the resistor R1, and the other end of the capacitor C2 is connected with the pin INLO of the detector AD 8318; one end of the resistor R2 is connected with a pin VSET of the detector AD8318, and the other end of the resistor R2 is connected with the resistor R3 and is connected with the inverting input end of the operational amplifier MAX4122 through the resistor R3; the pin VOUT of the detector AD8318 is connected to the connection point of the resistor R2 and the resistor R3; one end of the capacitor C3 is grounded, and the other end of the capacitor C is connected with the inverting input end of the operational amplifier MAX 4122; one end of the resistor R4 is connected with a power supply +VCC, and the other end of the resistor R4 is connected with the resistor R5 and grounded through the resistor R5; the non-inverting input end of the operational amplifier MAX4122 is connected to the connection point of the resistor R4 and the resistor R5; one end of the resistor R6 is connected with the output end of the operational amplifier MAX4122, and the other end of the resistor R6 is connected with the control end K4 of the FPGA control circuit.
The inside self-checking system of short wave prognosis selector, wherein: the first conversion circuit and the second conversion circuit both adopt SPDT radio frequency switches.
The inside self-checking system of short wave prognosis selector, wherein: the self-test system is shown mounted integrally with the short wave pre/post selector and together within a housing of a metallic, thermally conductive material.
The beneficial effects are that:
the internal self-checking system of the short-wave prognosis selector has the advantages of simple and reasonable structural design, small volume, low cost, high speed, high reliability, good frequency selectivity, stable and reliable operation and capability of effectively improving the technical index and electromagnetic compatibility of a short-wave radio station; the frequency hopping speed is high, namely, a digital tuning frequency hopping filter is adopted, the frequency hopping speed is less than or equal to 1000 mu s, and the self-checking test time is about 1.2s; the power consumption is low, and three wave band hopping filters are not supplied with power simultaneously, namely: when the gating work is performed, power supply is performed, so that the power consumption of a product can be reduced, and the signal interference among all wave bands can be reduced; the system clock of the FPGA control circuit is utilized, the hardware is simple, a crystal oscillator circuit is not needed, and the influence on the noise at the bottom of the pre/post selector is small.
The invention discloses a self-checking circuit built based on technologies such as an XC3S200A circuit, a detector AD8318 and the like; firstly, generating a frequency group which can cover all resonant circuits by an FPGA PLL module of an FPGA control circuit as a self-checking signal, and then sending the self-checking signal passing through a pre/post selector to an RF logarithmic detector to check whether the gain of the self-checking signal reaches the standard; experimental results show that the invention can effectively realize the rapid test and accurate analysis of the performance of each channel of the pre/post selector, and has important significance for locking the fault channel in time.
The invention can accurately carry out quick self-check on the performance of each channel of the pre/post selector, is also applicable to the measurement of the insertion loss or gain of other filter devices, and realizes the test on the performance of the pre/post selector by using a computer and software in production, thus having strong practical value; the conversion circuit adopts multiple technologies such as high-isolation SPDT switch, radio frequency signal switching design technique and the like, so that weak carrier wave leaked to other channels reaches the ground, the isolation between channels is improved, and the isolation can reach more than 60 dB.
According to the invention, serial data instructions are sent to an FPGA control circuit according to an external short-wave radio main control unit, the FPGA control circuit is converted into 13-bit parallel code instructions, and the 10-bit frequency control code is used for controlling 750 radio frequency filter circuits, and the 3-bit control code is used for controlling the receiving and transmitting as well as the self-checking radio frequency channel conversion, so that the transmission of carrier signals at different frequency points is realized, the carrier frequencies of useful signals are rapidly switched, and the anti-interference capability of the short-wave radio is improved; secondly, realize the self-checking function, have real-time fault detection ability.
The invention is integrated with the original short wave pre/post selector and is arranged in the shell of the metal heat conduction material, has good grounding and heat conduction performance as the original short wave pre/post selector, and has the capability of effectively reducing electromagnetic interference between internal electronic elements.
Drawings
FIG. 1 is a schematic diagram of a self-test scheme of a self-test system inside a short-wave prognosis selector of the present invention;
FIG. 2 is a schematic block diagram of a self-test circuit of the internal self-test system of the short-wave prognosis selector of the present invention;
FIG. 3 is a schematic block diagram of a pre/post selector filter circuit of the short wave prognostic selector internal self-test system of the present invention;
FIG. 4 is a circuit diagram of a self-test signal testing circuit of the self-test system inside the short-wave prognosis selector of the present invention.
Detailed Description
As shown in fig. 1 to 4, the internal self-checking system of the short-wave pre-selector of the present invention is installed integrally with the original short-wave pre/post-selector and is installed in a housing of a metal heat conductive material; the internal self-checking system of the short-wave prognosis selector comprises an FPGA control circuit 1, a self-checking signal shaping circuit 2, a conversion circuit 3, a pre/post selector filter circuit 4 and a self-checking signal testing circuit 5.
The FPGA control circuit 1 is electrically connected with an external short-wave radio station main control unit through a control interface, and the FPGA control circuit 1 is further electrically connected with a self-checking signal shaping circuit 2, a conversion circuit 3, a pre-selector filter circuit 4 and a self-checking signal testing circuit 5 respectively.
The FPGA control circuit 1 is used for receiving and transmitting data instructions and generating clocks for self-checking, namely: (1) an FPGA PLL module in the FPGA control circuit 1 generates a clock signal group which can cover all resonant circuits as a self-checking signal; (2) receiving the self-checking result and returning to the main control unit of the radio station; (3) and outputting a parallel control code consisting of high and low levels according to the serial data command sent by the short-wave radio station main control unit, controlling the pre/post selector or the self-checking work, or the pre-selector or the post selector to work, and sending back the data command. The FPGA PLL module in the FPGA control circuit 1 sequentially generates self-checking clock signals containing all resonant circuits, the self-checking result is received by the FPGA control circuit 1, and finally the self-checking result is sent back to the electric station main control unit. The self-checking clock signal group generated by the FPGA PLL module is used for covering each component in the product so as to ensure that all resonant circuits are at least in a working state for 1 time.
The FPGA control circuit 1 receives serial data instructions sent by a short-wave radio main control unit and converts the serial data instructions into 13-bit parallel control code instructions, the 10-bit frequency control code controls the pre/post selector filter circuit 4, the 3-bit control code controls the self-checking function of the pre/post selector (the control code is K1, K2 and K3, the pre/post selector is determined to be in a self-checking working state, a pre-selector working state or a post selector working state according to the instructions, one state works, the other two states do not work), and the pre-selector and the post selector are converted, so that the transmission of carrier signals at different frequency points is realized, the carrier frequency of the useful signals is rapidly switched, the self-checking function is realized, the anti-interference capability of the short-wave radio is improved, and the real-time fault detection capability is realized. The FPGA control circuit 1 is an XC3S200A circuit, and after receiving a serial control command of a radio station main control unit, serial data instructions are converted into 13-bit parallel codes P0-P9 and K1-K3, wherein P0-P9 are frequency control codes, and K1-K3 are receiving-transmitting and self-checking control codes.
The control relation of the self-checking and receiving control codes of the FPGA control circuit 1 is shown in the following table 1:
the FPGA control circuit 1 controls the selection of the receive (pre-selector) and transmit (post-selector) channels of the pre/post-selector filter circuit 4 via the K1 control terminal.
The self-checking signal shaping circuit 2 comprises a voltage reducing circuit 21, a radio follower 22 and a n-type network 23; the input end of the voltage reducing circuit 21 is electrically connected with the output end of an FPGA PLL module in the FPGA control circuit 1, and the output end of the voltage reducing circuit 21 is electrically connected with the input end of the follower 22; the output end of the emitter follower 22 is electrically connected with the input end of the pi-shaped network 23, and the output end of the pi-shaped network 23 is electrically connected with the conversion circuit 3.
The switching circuit 3 adopts an SPDT radio frequency switch with high isolation, and comprises a first switching circuit 31 and a second switching circuit 32 which have the same structure; the first conversion circuit 31 and the second conversion circuit 32 are electrically connected to the FPGA control circuit 1 and controlled by the control terminals K2 and K3 of the FPGA control circuit 1. The first conversion circuit 31 is electrically connected to the output end of the pi-type network 23 of the self-checking signal shaping circuit 2 through a pin No. 8, to the radio frequency input end of the pre-selector through a pin No. 5, to the FPGA control circuit 1 through a pin No. 2 and a pin No. 4, and to the input end of the pre/post-selector filter circuit 4 through a pin No. 3. The second conversion circuit 32 is electrically connected to the output end of the pre/post selector filter circuit 4 through a pin No. 3, to the radio frequency output end of the pre-selector through a pin No. 5, to the FPGA control circuit 1 through a pin No. 2 and a pin No. 4, and to the self-test signal test circuit 5 through a pin No. 8. The first conversion circuit 31 and the second conversion circuit 32 include three modes of operation: (1) when the control end K1 of the FPGA control circuit 1 is at a high level and the control ends K2 and K3 of the FPGA control circuit 1 are both at a low level, the short wave pre/post selector internal self-checking system works, a pre-selector filtering channel is in a conducting state, but a pre-selector input/output port is disconnected and grounded, so that weak signals leaked to the pre-selector input/output port are grounded, and the inter-channel isolation index is improved; (2) when the control ends K1 and K2 of the FPGA control circuit 1 are both in high level and the control end K3 of the FPGA control circuit 1 is in low level, the pre-selector circuit works, and the self-detection output port is disconnected and grounded, so that weak signals leaked to the self-detection output port are grounded, and the inter-channel isolation index is improved; (3) when the control end K1 of the FPGA control circuit 1 is at a low level and the control ends K2 and K3 of the FPGA control circuit 1 are at a high level, the preselector and the self-checking input and output ports are both disconnected and grounded, so that weak signals leaked to the preselector and the self-checking input and output ports are both grounded, and the inter-channel isolation index is improved.
As shown in fig. 3, the pre/post-selector filter circuit 4 includes a digital tuning frequency hopping filter 41, a first transception converting circuit 42, a second transception converting circuit 43, and an amplifying circuit 44; the frequency hopping speed of the digital tuning frequency hopping filter 41 is less than or equal to 1000 mu s, the self-checking test time is about 1.2s, the signal input end of the digital tuning frequency hopping filter 41 is connected with the output end of the first transceiver converting circuit 42, the signal output end of the digital tuning frequency hopping filter 41 is connected with the input end of the second transceiver converting circuit 43, the output end of the second transceiver converting circuit 43 is connected with the No. 3 pin of the second converting circuit 32 of the converting circuit 3, the input end of the first transceiver converting circuit 42 is connected with the output end of the amplifying circuit 44, and the input end of the amplifying circuit 44 is connected with the No. 3 pin of the first converting circuit 31 of the converting circuit 3.
The filtering circuits of the preselector and the post-selector are shared, that is, the preselector and the post-selector share the digital tuning frequency hopping filter 41, the first transceiver switching circuit 42 and the second transceiver switching circuit 43 are all SPDT (single pole double throw) radio frequency switches, and the detected filtering circuits of the preselector are equivalent to the detected filtering circuits of the post-selector, so that the filtering circuits of the post-selector in the short wave pre/post-selector with self-detection are not detailed herein; the digitally tuned frequency hopping filter 41 comprises 136 resonant circuits, constituting 750 filters. The pre/post selector filter circuit 4 is controlled by control codes P0-P9 and K1 of the FPGA control circuit 1, wherein when the control end K1 of the FPGA control circuit 1 is at a high level, the pre selector filter circuit is connected; when the control end K1 of the FPGA control circuit 1 is at a low level, the post-selector filter circuit is switched on.
The control principle of the digital tuning frequency hopping filter 41 is that P8 and P9 are band selection control codes, the working frequency range of the short wave pre/post selector is 1.6MHz to 30MHz, and the frequency ranges are divided into three bands; addresses P0-P7 are 8-bit parallel binary codes, namely: tuning a control code in a wave band; all 0 corresponds to the lowest frequency of the local wave band, and FAH corresponds to the highest frequency of the local wave band; and (3) calculating the address codes in the wave bands:
f 0 : a center frequency to be tuned;
f low : the lowest frequency of the frequency band;
f high : the highest frequency of the frequency band.
The frequency groups which can cover all the resonant circuits are analyzed and calculated to obtain the least common multiple, and proper fundamental frequency, namely the frequency of the external clock crystal oscillator of the FPGA is selected; and then according to the characteristics of integer frequency multiplication and even frequency division of the FPGA PLL module, all self-checking frequencies are calculated.
The method for generating the self-checking frequency signal is to control the system clock of the circuit 1 by using the FPGA, and has the advantages of simple hardware, no crystal oscillator circuit and small influence on the noise at the bottom of the pre/post selector.
The self-checking signal testing circuit 5 is used for converting the radio frequency signal into a digital signal which can be recognized by the FPGA control circuit 1, and comprises an RF logarithmic detector 51 and a voltage comparator 52. Wherein, the input end of the RF logarithmic detector 51 is electrically connected with the No. 8 pin of the second conversion circuit 32 of the conversion circuit 3, and the output end is electrically connected with the input end of the voltage comparator 52; the output end of the voltage comparator 52 is electrically connected to the control end K4 of the FPGA control circuit 1.
As shown in fig. 4, the RF logarithmic detector 51 is composed of a detector AD8318, capacitors C1 to C2, and resistors R1 to R3 connected to each other, the voltage comparator 52 is composed of an operational amplifier MAX4122, a capacitor C3, and resistors R4 to R6 connected to each other, and the resistor R5 is an adjustable resistor. One end of the capacitor C1 (via the RF self-detection signal input of the pre/post selector filter circuit 4) is connected to pin 8 of the second conversion circuit 32 of the conversion circuit 3, and the other end is connected to pin INHI of the detector AD 8318; one end of the capacitor C2 is connected to the resistor R1 and connected (via the RF self-test signal input of the pre/post selector filter circuit 4) to pin 8 of the second conversion circuit 32 of the conversion circuit 3, and the other end is connected to pin INLO of the detector AD 8318; one end of the resistor R2 is connected with a pin VSET of the detector AD8318, and the other end of the resistor R2 is connected with a resistor R3 and is connected with an inverting input end (self-checking signal output) of the operational amplifier MAX4122 of the voltage comparator 52 through the resistor R3; the pin VOUT of the detector AD8318 is connected to the connection point of the resistor R2 and the resistor R3; one end of the capacitor C3 is grounded, and the other end of the capacitor C is connected with the inverting input end of the operational amplifier MAX 4122; one end of the resistor R4 is connected with a power supply +VCC, and the other end of the resistor R4 is connected with the resistor R5 and grounded through the resistor R5; the non-inverting input end of the operational amplifier MAX4122 is connected with the connection point of the resistor R4 and the resistor R5; one end of the resistor R6 is connected to the output end of the operational amplifier MAX4122, and the other end (self-checking voltage output) is connected to the control end K4 of the FPGA control circuit 1.
The voltage comparator 52 is fixed with reference voltage, but can be adjusted according to actual conditions; the RF logarithmic detector 51 converts the RF self-test input signal into a corresponding dB-scale output voltage, and then sends the voltage to the voltage comparator 52 for comparison with a fixed reference voltage, and outputs a dc voltage through the comparison of the voltages at both input terminals, and only when the output dc voltage is high, the pre/post selector operates normally, otherwise the pre/post selector fails.
The automatic test of the self-checking system in the short-wave prognosis selector is mainly realized through FPGA programming, and the specific test flow is as follows: the FPGA PLL module of the FPGA control circuit 1 generates a first self-checking clock signal, and the first detection result is sent back to the FPGA control circuit 1 through the signal shaping circuit, the pre/post selector filter circuit 4, the RF logarithmic detector 51 and the voltage comparator 52 to finish the first frequency signal detection; then, the FPGA control circuit 1 sends out a second self-checking clock signal, the detection result is sent back to the FPGA control circuit 1 to finish the second detection, and so on until all preset frequency signals are detected, and finally the detection result is sent to the main control unit of the radio station to be processed, and the result is displayed on the display panel of the main control unit of the radio station; the FPGA control circuit 1 can report to the short-wave radio station which frequency or certain frequency section or other circuit faults are specific through the transmitted frequency and the received fault level signal.
Meanwhile, in the self-checking working mode of the internal self-checking system of the short wave pre-post selector, the FPGA PLL module of the FPGA control circuit 1 generates clock signals which can cover all resonant circuits, the clock signals pass through the pre-post selector filter circuit 4 after sequentially passing through the shaping circuit and then are sent to the RF logarithmic detector 51 to convert radio frequency signals (gain) into voltage values, then a direct-current high level (representing normal working) or a direct-current low level (representing abnormal working) is output through the voltage comparator 52, the output result is directly sent back to the FPGA control circuit 1, the FPGA control circuit 1 is sent back to the radio station main control unit, and the radio station main control unit judges whether the pre-post selector has faults or not according to the sent self-checking signals and the self-checking test return result and displays the results on the radio station display panel; in the working mode of the preselector or the postselector, the carrier frequency in the short wave radio station is used for suppressing the useless signal through the preselector/postselector filter circuit 4, transmitting the useful signal and rapidly switching the carrier frequency of the useful signal; the main control unit of the radio station judges whether the pre/post selector receives the normal or the error according to the data instruction sent back by the FPGA control circuit 1, so as to finish a complete modem control handshake process.
The working process of the self-detection system in the shortwave prognosis selector comprises the following steps:
the output end of the FPGA PLL module in the FPGA control circuit 1 is connected with the input end of the voltage reducing circuit 21, the output end of the voltage reducing circuit 21 is connected with the input end of the follower 22, the output end of the follower 22 is connected with the input end of the pi-shaped network 23, the output end of the pi-shaped network 23 is connected with the No. 8 pin of the first conversion circuit 31, the No. 3 pin of the first conversion circuit 31 is connected with the input end of the pre/post selector filter circuit 4, the output end of the pre/post selector filter circuit 4 is connected with the No. 3 pin of the second conversion circuit 32, the No. 8 pin of the second conversion circuit 32 is connected with the input end of the RF logarithmic detector 51, the output end of the RF logarithmic detector 51 is connected with the input end of the voltage comparator 52, and the output end of the voltage comparator 52 is connected with the control end K4 of the FPGA control circuit 1, so as to finish the output and test work of a self-test signal. And then, the FPGA PLL module in the FPGA control circuit 1 sends out a second self-checking clock signal, the detection result is sent back to the FPGA circuit to finish the detection of the second self-checking signal, and so on until all preset frequency signals are detected, finally, the detection result is transmitted to the main control unit of the station to be processed, and the result is displayed on the display panel of the main control unit of the station, so that the whole self-checking work is finished. The internal self-checking system of the short wave pre/post selector performs self-checking after starting up, and the self-checking test time is about 1.2s.
The internal self-checking system of the short wave pre-selector and the original short wave pre-selector are integrally designed and arranged in the shell of the metal heat-conducting material, and the internal self-checking system has good grounding and heat-conducting performance as the original short wave pre-selector and the original short wave pre-selector, and the capacity of effectively reducing electromagnetic interference among internal electronic elements.
According to the circuit division of the short-wave radio station, the circuit of the short-wave pre/post selector and the radio station main control circuit are two circuit units in the short-wave radio station, and the radio station main control circuit and the short-wave pre/post selector are not in one unit, so that the short-wave pre/post selector is not numbered.
The internal self-checking system of the short wave prognosis selector has simple and reasonable structural design, small volume, low cost and high speed, can effectively realize the rapid detection and accurate analysis of the performance of each channel of the pre/post selector, has important significance for timely locking fault channels, wherein a conversion circuit utilizes various technologies such as SPDT switches with high isolation, radio frequency signal switching design skills and the like to enable weak carriers leaked to other channels to reach the ground, improves the isolation between channels, and has the advantages of high reliability, high frequency hopping speed, low power consumption, small noise, good frequency selectivity, stable and reliable operation and capability of effectively improving the technical index and electromagnetic compatibility of a short wave radio station through test and use.
Claims (9)
1. An internal self-checking system of a short-wave prognosis selector comprises an FPGA control circuit and a pre/post selector filter circuit electrically connected with the FPGA control circuit; the FPGA control circuit is electrically connected with the external short-wave radio station main control unit through a control interface; the method is characterized in that: the self-checking system further comprises a self-checking signal shaping circuit, a conversion circuit and a self-checking signal testing circuit which are electrically connected with the FPGA control circuit;
the self-checking signal shaping circuit comprises a voltage reducing circuit, a radio follower and a n-type network; the input end of the voltage reduction circuit is electrically connected with the output end of the FPGA control circuit, and the output end of the voltage reduction circuit is electrically connected with the input end of the emitter follower; the output end of the emitter follower is electrically connected with the input end of the pi-shaped network, and the output end of the pi-shaped network is electrically connected with the conversion circuit;
the conversion circuit comprises a first conversion circuit and a second conversion circuit which are identical in structure; the first conversion circuit and the second conversion circuit are electrically connected with the FPGA control circuit; the first conversion circuit is also electrically connected with the output end of the pi-type network, the radio frequency input end of the preselector and the input end of the pre/post selector filter circuit respectively; the second conversion circuit is also electrically connected with the output end of the pre/post selector filter circuit, the radio frequency output end of the pre-selector and the self-checking signal testing circuit respectively;
the self-checking signal testing circuit comprises an RF logarithmic detector and a voltage comparator; the input end of the RF logarithmic detector is electrically connected with the second conversion circuit, and the output end of the RF logarithmic detector is electrically connected with the input end of the voltage comparator; and the output end of the voltage comparator is electrically connected with the FPGA control circuit.
2. The short wave prognostic selector internal self-test system according to claim 1, wherein: the FPGA control circuit receives serial data instructions sent by the short-wave radio station main control unit and converts the serial data instructions into 13-bit parallel control code instructions, the pre/post selector filter circuit is controlled by 10-bit frequency control codes respectively, the self-checking function of the pre/post selector, the pre-selector and the conversion among the post-selector are controlled by 3-bit control codes, so that the transmission of carrier signals of different frequency points is realized, the carrier frequency of useful signals is rapidly switched, and the self-checking function is realized;
the FPGA control circuit is an XC3S200A circuit, and after receiving a serial control command of the control device, the FPGA control circuit converts a serial data command into 13-bit parallel codes P0-P9 and K1-K3, wherein P0-P9 are frequency control codes, and K1-K3 are receiving-transmitting and self-checking control codes.
3. The short wave prognostic selector internal self-test system according to claim 2, wherein: the first conversion circuit and the second conversion circuit are controlled by control ends K2 and K3 of the FPGA control circuit;
the first conversion circuit is electrically connected with the output end of the pi-type network through a pin 8, is electrically connected with the radio frequency input end of the preselector through a pin 5, is electrically connected with the control end K2 of the FPGA control circuit through a pin 2, is electrically connected with the control end K3 of the FPGA control circuit through a pin 4, and is electrically connected with the input end of the pre/post selector filter circuit through a pin 3;
the second conversion circuit is electrically connected with the output end of the pre/post selector filter circuit through a pin No. 3, is electrically connected with the radio frequency output end of the pre-selector through a pin No. 5, is electrically connected with the control end K2 of the FPGA control circuit through a pin No. 2, is electrically connected with the control end K3 of the FPGA control circuit through a pin No. 4, and is electrically connected with the input end of the RF logarithmic detector through a pin No. 8.
4. The short wave prognostic selector internal self-test system according to claim 2, wherein: the pre/post selector filter circuit is controlled by control codes P0-P9 and K1 of the FPGA control circuit; the FPGA control circuit controls the selection of a pre-selector receiving channel and a post-selector sending channel of the pre-selector/post-selector filter circuit through a K1 control end, namely, when the control end K1 of the FPGA control circuit is at a high level, the pre-selector filter circuit is connected, and when the control end K1 of the FPGA control circuit is at a low level, the post-selector filter circuit is connected.
5. The short wave prognostic selector internal self-test system according to claim 1 or 4, wherein: the pre/post selector filter circuit comprises a digital tuning frequency hopping filter, a first transceiver conversion circuit, a second transceiver conversion circuit and an amplifying circuit; the preselector and the post selector share the digital tuning frequency hopping filter; the frequency hopping speed of the digital tuning frequency hopping filter is less than or equal to 1000 mu s, the self-checking test time is about 1.2s, and the signal input end of the digital tuning frequency hopping filter is connected with the output end of the first transceiver conversion circuit; the signal output end of the digital tuning frequency hopping filter is connected with the input end of the second transceiver conversion circuit; the output end of the second transceiver converting circuit is connected with the No. 3 pin of the second converting circuit, the input end of the first transceiver converting circuit is connected with the output end of the amplifying circuit, and the input end of the amplifying circuit is connected with the No. 3 pin of the first converting circuit.
6. The short wave prognostic selector internal self-test system according to claim 5, wherein: the first transceiver conversion circuit and the second transceiver conversion circuit are SPDT radio frequency switches; the digital tuning frequency hopping filter comprises 136 resonant circuits, and 750 filters are formed.
7. The short wave prognostic selector internal self-test system according to claim 2, wherein: the input end of the RF logarithmic detector is electrically connected with the No. 8 pin of the second conversion circuit; the output end of the voltage comparator is electrically connected with the control end K4 of the FPGA control circuit;
the RF logarithmic detector is formed by connecting a detector AD8318, capacitors C1-C2 and resistors R1-R3, the voltage comparator is formed by connecting an operational amplifier MAX4122, a capacitor C3 and resistors R4-R6, and the resistor R5 is an adjustable resistor; one end of the capacitor C1 is connected with the No. 8 pin of the second conversion circuit, and the other end of the capacitor C1 is connected with the pin INHI of the detector AD 8318; one end of the capacitor C2 is connected with the resistor R1 and is connected with the No. 8 pin of the second conversion circuit through the resistor R1, and the other end of the capacitor C2 is connected with the pin INLO of the detector AD 8318; one end of the resistor R2 is connected with a pin VSET of the detector AD8318, and the other end of the resistor R2 is connected with the resistor R3 and is connected with the inverting input end of the operational amplifier MAX4122 through the resistor R3; the pin VOUT of the detector AD8318 is connected to the connection point of the resistor R2 and the resistor R3; one end of the capacitor C3 is grounded, and the other end of the capacitor C is connected with the inverting input end of the operational amplifier MAX 4122; one end of the resistor R4 is connected with a power supply +VCC, and the other end of the resistor R4 is connected with the resistor R5 and grounded through the resistor R5; the non-inverting input end of the operational amplifier MAX4122 is connected to the connection point of the resistor R4 and the resistor R5; one end of the resistor R6 is connected with the output end of the operational amplifier MAX4122, and the other end of the resistor R6 is connected with the control end K4 of the FPGA control circuit.
8. The short wave prognostic selector internal self-test system according to claim 1, wherein: the first conversion circuit and the second conversion circuit both adopt SPDT radio frequency switches.
9. The short wave prognostic selector internal self-test system according to claim 1, wherein: the self-test system is shown mounted integrally with the short wave pre/post selector and together within a housing of a metallic, thermally conductive material.
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| CN110988931B (en) * | 2019-10-31 | 2022-03-04 | 北京遥测技术研究所 | Clock self-checking circuit based on AD8310 detector |
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