CN108958757A - The upgrade method of complicated embedded device and complicated embedded device - Google Patents
The upgrade method of complicated embedded device and complicated embedded device Download PDFInfo
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Abstract
The present invention provides a kind of upgrade method of complicated embedded device and complicated embedded devices, wherein, this method comprises: after multiple CPU of complicated embedded device complete upgrading, the corresponding operation version area flag of each CPU is modified accordingly, it is subsequent after equipment is restarted, master cpu determines whether each CPU completes upgrading by the way that whether the operation version area flag that detects each CPU is identical, if there is different situation, then illustrate that device upgrade fails, master cpu controls each CPU and reuses old version system.By adopting the above technical scheme, it avoids in complicated embedded device escalation process in the related technology, it is possible that since the version between multiple CPU is inconsistent, and the problem of causing the certain functions of system not to be available or can not normally start, complicated embedded device is realized in the case where upgrading failure, each CPU can use legacy version normally to start.
Description
Technical field
The present invention relates to the communications fields, embedding in particular to the upgrade method and complexity of a kind of complicated embedded device
Enter formula equipment.
Background technique
In the related art, complicated embedded device is that have in an equipment comprising two or more CPU, each CPU
The memory and storage firmware and other peripheral equipments composition of oneself.The version of CPU is stored in embedded device storage firmware
On, include machine instruction, realizes the binary file of functions of the equipments.In general, embedded device upgraded version is by webpage, net
For the modes such as pipe download version to embedded device, embedded device updates original version being stored on firmware again.
But when updating the version being stored on firmware, it may appear that unexpected power down causes the version on firmware endless
Whole, system can not normally start.
For in the related technology, in complicated embedded device escalation process, it is possible that due to the version between multiple CPU
This is inconsistent, and the problem of cause system not start normally, there is presently no effective solution schemes.
Summary of the invention
The embodiment of the invention provides a kind of upgrade method of complicated embedded device and complicated embedded devices, at least
It solves in complicated embedded device escalation process in the related technology, it is possible that since the version between multiple CPU is inconsistent,
And the problem of causing the certain functions of system not to be available or can not normally start.
According to one embodiment of present invention, a kind of upgrade method of complicated embedded device is provided, comprising:
Master central processor CPU obtains the system update version of the corresponding system of multiple CPU, wherein described more
A CPU includes the master cpu, and the multiple CPU configuration, in embedded device, two systems are respectively configured in each CPU
Version storage region；The master cpu stores the system update version of the multiple CPU respectively to the multiple CPU
Corresponding the first system version storage region, so that the multiple CPU is respectively according to corresponding the first system
The system update version stored in version storage region carries out upgrading update, wherein the first system version memory block
Domain is the system version currently run of not stored CPU in described two system version storage regions corresponding with each CPU
Version region.
Optionally, the master cpu stores the system update version of the multiple CPU respectively to the multiple
After the corresponding the first system version storage region of CPU, the master cpu is by the operation version region of the multiple CPU
Mark is updated to the first system version storage region respectively, wherein the operation version area flag is used to indicate CPU and works as
The system version storage region that preceding run system version is stored.
Optionally, the master cpu the operation version area flag for having updated other CPU in the multiple CPU it
Afterwards, the operation version area flag of itself is updated.
Optionally, the operation version area flag of the multiple CPU is updated to first system by the master cpu respectively
After version storage region of uniting, the embedded device is restarted, the master cpu detects the operation version of the master cpu
One's respective area indicates whether the operation version area flag corresponding with the multiple CPU is consistent；In the master cpu
The operation version area flag of the operation version area flag and at least one CPU in the multiple CPU is inconsistent
In the case of, the master cpu modifies the operation version field of the operation version identifier and the master cpu of at least one CPU
Domain mark is identical, and sends a notification message to webpage and/or network management upgrading medium, and the notification message is for notifying the insertion
Formula device upgrade failure.
Optionally, master cpu obtains the system update version of the corresponding system of multiple CPU, comprising: the master control
CPU obtains version updating packet, includes in the version updating packet: the system update version corresponding with the multiple CPU
Sheet and version head；Wherein, offset corresponding with each CPU is carried in the version head, wherein the offset is used for
Indicate storage location of the system update version of each CPU in the version updating packet；The master cpu is according to described in
Offset obtains the corresponding system update version of the multiple CPU from the version updating packet.
Optionally, the version updating packet also carries check code, and the master cpu passes through described in check code verifying
Whether version updating packet is complete.
Optionally, the master cpu is connected to the multiple CPU by remote procedure call.
According to another embodiment of the invention, a kind of complicated embedded device is additionally provided, comprising: multiple CPU, it is described
It include main control CPU in multiple CPU, and two systems version storage region is respectively configured in each CPU；The embedded device is also
Include:
Communication device, for obtaining the system update version of the corresponding system of the multiple CPU；
The master cpu, for being stored the system update version of the multiple CPU respectively to the multiple CPU
Corresponding the first system version storage region, so that the multiple CPU is respectively according to corresponding the first system
The system update version stored in version storage region carries out upgrading update, wherein the first system version memory block
The system version that domain is currently run for not stored CPU in at least two system versions storage region corresponding with each CPU
This version region.
Optionally, the master cpu, be also used to by the system update version of the multiple CPU store respectively to
After the multiple corresponding the first system version storage region of CPU, by the operation version area flag of the multiple CPU
It is updated to the first system version storage region respectively, wherein the operation version area flag is used to indicate the current institute of CPU
The system version storage region that the system version of operation is stored.
Optionally, the master cpu is also used to, in the master cpu by the operation version area flag of the multiple CPU
It is updated to after the first system version storage region respectively, restarts the embedded device, and detect the master cpu
Whether the operation version area flag operation version area flag corresponding with the multiple CPU is consistent；
The master cpu is also used to, in the operation version area flag and the multiple CPU of the master cpu
In the case that the operation version area flag of at least one CPU is inconsistent, the operation version of at least one CPU is modified
Mark is identical as the operation version area flag of the master cpu, and sends notice to webpage and/or network management upgrading medium and disappear
Breath, the notification message is for notifying the embedded device upgrading failure.
Optionally, the communication device is also used to, and obtains version updating packet, includes in the version updating packet: with it is described
The corresponding system update version of multiple CPU and version head；Wherein, it is carried and each CPU pairs in the version head
The offset answered, wherein the offset is used to indicate the system update version of each CPU in the version updating packet
Storage location；The master cpu is also used to, and obtains the multiple CPU from the version updating packet according to the offset
Corresponding system update version.
According to still another embodiment of the invention, a kind of storage medium is additionally provided.The storage medium is set as storage and uses
In the program code for executing following steps:
Master central processor CPU obtains the system update version of the corresponding system of multiple CPU, wherein described more
A CPU includes the master cpu, and the multiple CPU configuration, in embedded device, two systems are respectively configured in each CPU
Version storage region；
It is respectively right to the multiple CPU that the master cpu stores the system update version of the multiple CPU respectively
The first system version storage region answered, so that the multiple CPU is deposited according to corresponding the first system version respectively
The system update version stored in storage area domain carries out upgrading update, wherein the first system version storage region be with
The version for the system version that not stored CPU is currently run in the corresponding at least two system versions storage region of each CPU
One's respective area.
Through the invention, in the escalation process of complicated embedded device, master cpu by the corresponding system of each CPU more
New version is stored in the not currently used version region each CPU, rather than the system version before replacing, so that each
CPU possesses new version and legacy version simultaneously, in this case, if causing certain CPU not complete by emergency cases such as power-off
At update, legacy version is can be used also to complete to start in all CPU in the equipment, and upgrading updates again for subsequent progress.In version
This upgrading final step, switching master cpu run version area flag；After edition upgrading, by " binary method ", judge each
Whether the version of CPU is consistent, such as inconsistent, and it is abnormal to illustrate that escalation process occurs, and master cpu switches from CPU version area flag,
Make all CPU in the equipment using legacy version, prepares for subsequent progress again upgrading.By adopting the above technical scheme, it avoids
In the related technology in complicated embedded device escalation process, it is possible that since the version between multiple CPU is inconsistent, and
The problem of causing the certain functions of system not to be available or can not normally start, realizes complicated embedded device and fails in upgrading
In the case where, can normally it start.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart of the upgrade method of complicated embedded device according to an embodiment of the present invention；
Fig. 2 is the structure chart of the double version software and hardwares of dual processors according to the preferred embodiment of the invention；
Fig. 3 is the double version composite structural diagrams of dual processors according to the preferred embodiment of the invention；
Fig. 4 is the double edition upgrading flow charts of dual processors according to the preferred embodiment of the invention.
Specific embodiment
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and in combination with Examples.It should be noted that not conflicting
In the case of, the features in the embodiments and the embodiments of the present application can be combined with each other.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.
Embodiment one
Technical solution in present specification can run on complicated embedded device, that is, include the insertion of multiple CPU
Formula equipment can be two CPU, be certainly not limited to two CPU in a preferred embodiment of the invention.
A kind of upgrading of multi -CPU embedded device for running on complicated embedded device, Fig. 1 are provided in the present embodiment
It is the flow chart of the upgrade method of complicated embedded device according to an embodiment of the present invention, as shown in Figure 1, the process includes as follows
Step:
Step S102, master central processor CPU obtain the system update version of the corresponding system of multiple CPU,
In, multiple CPU includes the master cpu, and multiple CPU configuration, in embedded device, each CPU is respectively configured two and is
System version storage region；
Step S104, the master cpu store the system update version of multiple CPU respectively to multiple CPU respectively
Corresponding the first system version storage region, so that multiple CPU is stored according to corresponding the first system version respectively
The system update version stored in region carries out upgrading update, wherein the first system version storage region be and each CPU
The version region for the system version that not stored CPU is currently run in the corresponding at least two system versions storage region.
It should be noted that the binary method in present specification refers to through setting the first system version region or the second system
Whether the mark in version region of uniting identifies the upgrade-system of multiple CPU in current device.For example, complete in system update
Bi Hou, if detecting that the operation version area flag of some CPU is designated as second system version region, the fortune with other CPU
Row version area flag is the first system version region, it is determined that device upgrade failure, all CPU run old system version.
Through the above steps, in the escalation process of complicated embedded device, master cpu is by the corresponding system of each CPU
More new version is stored in the not currently used version region each CPU, rather than the system version before replacing, so that each
CPU possesses new version and legacy version simultaneously, in this case, if causing certain CPU not complete by emergency cases such as power-off
At update, legacy version is can be used also to complete to start in all CPU in the equipment, and upgrading updates again for subsequent progress.In version
This upgrading final step, switching master cpu run version area flag；After edition upgrading, by " binary method ", judge each
Whether the version of CPU is consistent, such as inconsistent, and it is abnormal to illustrate that escalation process occurs, and master cpu switches from CPU version area flag,
Make all CPU in the equipment using legacy version, prepares for subsequent progress again upgrading.By adopting the above technical scheme, it avoids
In the related technology in complicated embedded device escalation process, it is possible that since the version between multiple CPU is inconsistent, and
The problem of causing system not start normally, realizes complicated embedded device in the case where upgrading failure, can normally open
It is dynamic.
Optionally, which stores the system update version of multiple CPU respectively right to multiple CPU respectively
After the first system version storage region answered, which is updated to the operation version area flag of multiple CPU respectively
The first system version storage region, wherein the operation version area flag is used to indicate the system version that CPU is currently run
The system version storage region stored.
Optionally, the master cpu is after having updated the operation version area flag of other CPU in multiple CPU, more
The newly operation version area flag of itself.
Optionally, which is updated to the first system version for the operation version area flag of multiple CPU respectively
After storage region, the embedded device is restarted, which detects the operation version area flag of the master cpu and be somebody's turn to do
Whether the corresponding operation version area flag of multiple CPU is consistent；The master cpu the operation version area flag with
In the case that the operation version area flag of at least one CPU is inconsistent in multiple CPU, which modifies this at least
The operation version identifier of one CPU is identical as the operation version area flag of the master cpu, and to webpage and/or network management upgrading
Medium sends a notification message, and the notification message is for notifying embedded device upgrading failure.
Optionally, master cpu obtains the system update version of the corresponding system of multiple CPU, comprising: the master cpu
Version updating packet is obtained, includes in the version updating packet: the system update version corresponding with multiple CPU and version
Head；Wherein, offset corresponding with each CPU is carried in the version head, wherein the offset is used to indicate each CPU's
Storage location of the system update version in the version updating packet；The master cpu is according to the offset from the version updating packet
It is middle to obtain multiple corresponding system update version of CPU.
Optionally, which also carries check code, which verifies the version updating by the check code
It whether complete wraps.
Optionally, which is connected to multiple CPU by remote procedure call.
Below in conjunction with a preferred embodiment of the present invention will be described in detail.
The technical problem to be solved is that provide a kind of complicated embedded device of solution to upgrade for the preferred embodiment of the present invention
Occur powering off at any time in journey, causes complicated embedded device not start normally or version starts, complicated embedded device dual processors
The software solution method of version inconsistence problems.
The specific solution technical problem used in this preferred embodiment can be following three kinds of situations:
1) it when upgrading master cpu version half, powers off suddenly, causes master cpu version that can not start
2) it when upgrading is from CPU version half, powers off suddenly, causes not starting from CPU version
3) upgrade when, master cpu and from CPU edition upgrading success, master cpu switching from CPU run version area flag
Success powers off suddenly, and master cpu self-operating version area flag can not switch, after leading to system reboot, version between dual processors
This is inconsistent, and then causes certain under master cpu not being available from cpu function.
The preferred embodiment of the present invention includes following technical scheme:
1) embedded device master cpu passes through remote procedure call (Remote procedure call, referred to as RPC)
The end client, using network interface access from the end server of the RPC (Remote procedure call) of CPU, utilize from
The control of definition and state application interface C SAPI (control and status API) order are controlled from CPU version liter
Grade updates from CPU and runs version area flag.
2) master cpu directly acquires the double versions of dual processors, includes host CPU version in the double version production of the dual processors, from CPU editions
Sheet and version head.CRC check in version head ensure that the integrality of double versions.Host CPU offset in version head and from CPU
Offset located position of the master-slave cpu version in the double versions of dual processors.
3) webpage, when network management upgrading medium updating apparatus, master cpu is responsible for downloading the double versions of dual processors；Master cpu is responsible for
The double versions of dual processors are parsed, decomposite host CPU version and from CPU version；Master-slave cpu is respective edition upgrading to the another of FLASH
An outer subregion, avoids power down from causing system that can not start；After upgrading successfully, updates marked from the operation version region of CPU first
Will, then update the operation version area flag of master cpu；
4) the operation version area flag of each CPU is identical value when equipment is dispatched from the factory, and only A and B two values, i.e.,
Dual processors version synchronization is carried out using binary method in this preferred embodiment.After version is restarted, judge that master-slave cpu runs version region
Mark, if master cpu operation version area flag and inconsistent, operation of the correction from CPU from CPU operation version area flag
Version area flag.It avoids powering off when updating master-slave cpu operation version area flag, dual processors version is inconsistent to be caused
Complicated embedded device cisco unity malfunction.
5) occur above-mentioned operation version area flag it is inconsistent in the case where, determine upgrading failure, inform webpage and/or
Network management upgrading medium, by webpage, network management upgrading medium is responsible for re-starting upgrading.
6) above-mentioned steps mainly includes following part: double version production, includes host CPU version in double versions, from CPU editions
Sheet and version head；Master cpu is responsible for parsing double versions, isolates host CPU version and from CPU version；Master cpu is responsible for host CPU
Version and from CPU edition upgrading；Master cpu is responsible for switching and runs version area flag and master cpu operation version region from CPU
Mark；After restarting, master cpu is responsible for synchronous dual processors version using binary method, guarantees version consistency；Upgrading failure, starting are fixed
When device, inform webpage, network management upgrading medium；Webpage, network management upgrading medium are responsible for re-starting upgrading.
It is the specific embodiment of the preferred embodiment of the present invention below
The preferred embodiment of the present invention is that edition upgrading is successful under dual processors to be realized and can guarantee the side of operation version consistency
Method.Since the device upgrade requirement in existing net is very high, once upgrading failure will face equipment and can not normally start, and for
More stringent requirements are proposed for the edition upgrading of dual processors, not only to upgrade successfully, but also to guarantee the consistency of dual processors version, institute
With the double edition upgrading software approach of invention dual processors.
Fig. 2 is the structure chart of the double version software and hardwares of dual processors according to the preferred embodiment of the invention, as shown in Fig. 2, each
CPU will have the FLASH of oneself, each FLASH that will have the area FLASH A, and the area FLASH B, operation version area flag is (independently
In the area A of FLASH and another FLASH subregion in the area B)；Master cpu controls the network interface from CPU, based on RPC's
The order of CSAPI.Operation version area flag indicates that version is started from the area A of FLASH or the area B of FLASH.
Fig. 3 is the double version composite structural diagrams of dual processors according to the preferred embodiment of the invention, as shown in figure 3, this dual processors is double
Version includes unreal head, master cpu version head, from CPU version head, master cpu version, from CPU version.Version head is main
For confirming principal and subordinate's version offset, version verification, version number.
The double edition upgrading processes of the dual processors of the preferred embodiment of the present invention, include the following steps:
Step 1: embedded device BOOT starting is resetted from CPU.2 are gone to step later.
Step 2: the Boot of master cpu obtains operation version area flag (area A that default value is FLASH), selects FLASH
The area A (or the area B) version starting, version starting after, start CSAPI RPC client；Operation version is obtained from the Boot of CPU
Area flag (area A that default value is FLASH), selects the area A (or the area the B) version of FLASH to start, after version starting, starting
CSAPI RPC server.3 are gone to step later.
Step 3: by CSAPI order, master cpu is obtained to be indicated from the operation area CPU；Master cpu obtains host CPU operation
Area flag.Compare master-slave cpu operation version area flag, master cpu runs version area flag and runs version field from CPU
Domain mark is consistent, and version operates normally, and goes to step 4 later；Master cpu runs version area flag and runs version field from CPU
Domain mark is inconsistent, illustrates that equipment carried out upgraded version, but exception occur, and master cpu needs to switch by CSAPI order
Version area flag is run from CPU, keeps master-slave cpu operation version area flag consistent.It is updated from CPU according to master cpu order
Run version area flag.Step 13 is gone to later.
Step 4: webpage, network management upgrading medium updating apparatus, the double versions of device downloads dual processors, the double versions downloadings of dual processors at
Function goes to step 5 later；The double version failed downloads of dual processors, go to step 13.
Step 5: the double version verifications of dual processors, the double version CRC check successes of dual processors go to step 6 later；The double versions of dual processors
Verification failure, goes to step 13.
Step 6: master cpu using the double versions of dual processors version head, by host CPU offset in version head and from CPU
Offset located position of the master-slave cpu version in the double versions of dual processors, parse host CPU version and from CPU version.Turn later
Step 7.
Step 7: master cpu obtains current master cpu and runs FLASH subregion.If current partition is the area A, master cpu
With the area B of itself FLASH of host CPU version updating.If current partition is the area B, master cpu host CPU version updating itself
The area A of FLASH.8 are gone to step later.
Step 8: updating the success of master control FLASH version, go to step 9 later；The failure of master control FLASH version is updated, step is gone to
Rapid 13.
Step 9: master cpu obtains from CPU and runs FLASH subregion.If current partition is the area A, master cpu with from
CPU version updating is from the area B of the FLASH of CPU；If current partition is the area B, master cpu is with from CPU version updating from CPU
FLASH the area A.Upgrade the area A or the area B from CPU according to master cpu upgrade command, goes to step 10 later.
Step 10: updating from the success of the FLASH version of CPU, go to step 11 later；It updates and is lost from the FLASH version of CPU
It loses, goes to step 13.
Step 11: master cpu, which is updated from CPU, runs version area flag.It is updated and is run according to master cpu order from CPU
Version area flag.
Step 12: master cpu updates self-operating version area flag.Terminate.
Step 13: notice webpage, network management upgrading medium, while master cpu starts 10s timer.If webpage, network management liter
Grade medium continues updating apparatus, closes 10s timer, goes to step 4 later；If webpage, network management upgrading medium does not upgrade again
Equipment, timer time arrive, restarting equipment.Terminate.
Fig. 4 is the double edition upgrading flow charts of dual processors according to the preferred embodiment of the invention, and Fig. 4 illustrates the double versions of dual processors
Upgrade process, Fig. 4 illustrates more detailed process in above-mentioned 13 steps.
Through the above description of the embodiments, those skilled in the art can be understood that according to above-mentioned implementation
The method of example can be realized by means of software and necessary general hardware platform, naturally it is also possible to by hardware, but it is very much
In the case of the former be more preferably embodiment.Based on this understanding, technical solution of the present invention is substantially in other words to existing
The part that technology contributes can be embodied in the form of software products, which is stored in a storage
In medium (such as ROM/RAM, magnetic disk, CD), including some instructions are used so that a terminal device (can be mobile phone, calculate
Machine, server or network equipment etc.) execute method described in each embodiment of the present invention.
Embodiment two
According to another embodiment of the invention, a kind of embedded device is additionally provided, comprising: multiple CPU, it is multiple
It include main control CPU in CPU, and two systems version storage region is respectively configured in each CPU；The embedded device further include:
Communication device, for obtaining the system update version of the corresponding system of multiple CPU；
The master cpu is respectively corresponded to for being stored the system update version of multiple CPU respectively to multiple CPU
The first system version storage region so that multiple CPU is respectively according to corresponding the first system version storage region
The system update version of middle storage carries out upgrading update, wherein the first system version storage region is corresponding with each CPU
At least two system versions storage region in the version region of system version that is currently run not stored CPU.
Optionally, the master cpu is also used to be stored respectively by the system update version of multiple CPU to multiple
After the corresponding the first system version storage region of CPU, the operation version area flag of multiple CPU is updated to respectively
The first system version storage region, wherein the operation version area flag is used to indicate the system version that CPU is currently run
The system version storage region stored.
Optionally, which is also used to, and distinguishes the operation version area flag of multiple CPU more in the master cpu
It is newly to restart the embedded device, and detect the operation version field of the master cpu after the first system version storage region
Domain indicates whether the operation version area flag corresponding with multiple CPU is consistent；
The master cpu is also used to, in the operation version area flag and at least one in multiple CPU of the master cpu
In the case that the operation version area flag of CPU is inconsistent, operation version identifier and the master control of at least one CPU are modified
The operation version area flag of CPU is identical, and sends a notification message to webpage and/or network management upgrading medium, which uses
Fail in notifying that the embedded device upgrades.
Optionally, which is also used to, and obtains version updating packet, includes in the version updating packet: with multiple CPU
The corresponding system update version and version head；Wherein, offset corresponding with each CPU is carried in the version head,
Wherein, which is used to indicate storage location of the system update version of each CPU in the version updating packet；The master control
CPU is also used to, and obtains the corresponding system update version of multiple CPU from the version updating packet according to the offset.
Embodiment three
The embodiments of the present invention also provide a kind of storage mediums.Optionally, in the present embodiment, above-mentioned storage medium can
To be arranged to store the program code for executing following steps:
S1, master central processor CPU obtain the system update version of the corresponding system of multiple CPU, wherein this is more
A CPU includes the master cpu, and multiple CPU configuration, in embedded device, at least two systems are respectively configured in each CPU
Version storage region；
S2, the master cpu store the system update version of multiple CPU corresponding to multiple CPU respectively
The first system version storage region, so that multiple CPU is respectively according in corresponding the first system version storage region
The system update version of storage carries out upgrading update, wherein the first system version storage region is corresponding with each CPU
The version region for the system version that not stored CPU is currently run in at least two system versions storage region.
Optionally, in the present embodiment, above-mentioned storage medium can include but is not limited to: USB flash disk, read-only memory (ROM,
Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or
The various media that can store program code such as CD.
Optionally, in the present embodiment, processor executes above-mentioned implementation according to program code stored in storage medium
Method and step in example.
Optionally, the specific example in the present embodiment can be with reference to described in above-described embodiment and optional embodiment
Example, details are not described herein for the present embodiment.
Obviously, those skilled in the art should be understood that each module of the above invention or each step can be with general
Computing device realize that they can be concentrated on a single computing device, or be distributed in multiple computing devices and formed
Network on, optionally, they can be realized with the program code that computing device can perform, it is thus possible to which they are stored
It is performed by computing device in the storage device, and in some cases, it can be to be different from shown in sequence execution herein
Out or description the step of, perhaps they are fabricated to each integrated circuit modules or by them multiple modules or
Step is fabricated to single integrated circuit module to realize.In this way, the present invention is not limited to any specific hardware and softwares to combine.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of upgrade method of complexity embedded device characterized by comprising
Multiple CPUs difference of the master cpu according to equipment where master cpu described in the multiple system update edition upgradings obtained in advance
Corresponding system, and the operation version area flag of the multiple CPU is updated to the first system version storage region respectively
Mark, wherein the system update version is stored in the first system version storage region, the multiple CPU includes institute
State master cpu, what the operation version area flag was used to indicate that equipment restarts that the system version that rear CPU is run stored is
System version storage region；
After restarting the equipment, the master cpu detect the operation version area flag of the master cpu with it is the multiple
Whether the corresponding operation version area flag of CPU consistent, the operation version area flag that detects the master cpu with
In the case that the operation version area flag of at least one CPU is inconsistent in the multiple CPU, described in the master cpu switching
The operation version area identification of multiple CPU is the mark of second system version storage region, wherein the second system version is deposited
Storage area domain is stored with the system version before this upgrading.
2. the method according to claim 1, wherein the operation version area flag of the multiple CPU is distinguished
It is updated to the mark of the first system version storage region, comprising:
The master cpu updates itself after having updated the operation version area flag of other CPU in the multiple CPU
Operation version area flag.
3. the method according to claim 1, wherein master cpu is according to the multiple system update versions obtained in advance
The corresponding system of multiple CPU of equipment where this upgrades the master cpu, comprising:
The master cpu stores the system update version of the multiple CPU corresponding to the multiple CPU respectively
The first system version storage region, so that the multiple CPU is deposited according to corresponding the first system version respectively
The system update version stored in storage area domain carries out upgrading update, wherein each CPU is respectively configured two systems version and deposits
Storage area domain, the first system version storage region be described two system version storage regions corresponding with each CPU in not
The version region for the system version that storage CPU is currently run.
4. the method according to claim 1, wherein the master cpu switches the operation version of the multiple CPU
After area identification is the mark of second system version storage region, the method also includes:
It sends a notification message to webpage and/or network management upgrading medium, the notification message is for notifying the complexity is embedded to set
Standby upgrading failure.
5. the method according to claim 1, wherein the master cpu obtains the mode packet of system update version
It includes:
The master cpu obtains version updating packet, includes in the version updating packet: institute corresponding with the multiple CPU
State system update version and version head；Wherein, offset corresponding with each CPU is carried in the version head, wherein institute
It states offset and is used to indicate storage location of the system update version of each CPU in the version updating packet；
The master cpu obtains the corresponding system of the multiple CPU according to the offset from the version updating packet
More new version.
6. according to the method described in claim 5, it is characterized in that, the version updating packet also carries check code, the master
It is whether complete by the check code verifying version updating packet to control CPU.
7. the method according to claim 1, wherein the method also includes:
The master cpu accesses the multiple CPU by remote procedure call.
8. a kind of complexity embedded device characterized by comprising include master cpu in multiple CPU, the multiple CPU；Institute
State embedded device further include:
Master cpu obtains the corresponding system of multiple multiple CPU of system update edition upgrading, the master for foundation in advance
The operation version area flag of the multiple CPU is updated to the mark of the first system version storage region by control CPU respectively,
In, the system update version is stored in the first system version storage region, the operation version area flag is used for
Indicating equipment restarts the system version storage region that the system version that rear CPU is run is stored；
The master cpu is also used to after restarting the embedded device, detects the operation version region of the master cpu
Indicate whether operation version area flag corresponding with the multiple CPU is consistent, in the operation for detecting the master cpu
In the case that the operation version area flag of at least one CPU is inconsistent in version area flag and the multiple CPU, the master
The operation version area identification that control CPU switches the multiple CPU is the mark of second system version storage region, wherein described
Second system version storage region is stored with the system version before this upgrading.
9. complexity embedded device according to claim 8, which is characterized in that
The master cpu is also used to, after having updated the operation version area flag of other CPU in the multiple CPU, more
The newly operation version area flag of itself.
10. complexity embedded device according to claim 8, which is characterized in that
The master cpu is also used to store the multiple system update version respectively to the corresponding institute of the multiple CPU
The first system version storage region is stated, so that the multiple CPU is stored according to corresponding the first system version respectively
The system update version stored in region carries out upgrading update, wherein the storage of two systems version is respectively configured in each CPU
Region, the first system version storage region are not deposit in described two system version storage regions corresponding with each CPU
The version region for the system version that storage CPU is currently run.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114675902A (en) * | 2022-03-11 | 2022-06-28 | 潍柴动力股份有限公司 | Software version management method and management device based on embedded equipment |
| CN114741119A (en) * | 2022-03-22 | 2022-07-12 | 深圳数马电子技术有限公司 | System starting method and device, computer equipment and storage medium |
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2017
- 2017-05-22 CN CN201710368655.8A patent/CN108958757A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114675902A (en) * | 2022-03-11 | 2022-06-28 | 潍柴动力股份有限公司 | Software version management method and management device based on embedded equipment |
| CN114675902B (en) * | 2022-03-11 | 2023-08-18 | 潍柴动力股份有限公司 | Management method and management device for software version based on embedded equipment |
| CN114741119A (en) * | 2022-03-22 | 2022-07-12 | 深圳数马电子技术有限公司 | System starting method and device, computer equipment and storage medium |
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