CN108933607B

CN108933607B - Radio frequency transmitter

Info

Publication number: CN108933607B
Application number: CN201710375446.6A
Authority: CN
Inventors: 冯泽民; 侯晨龙
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-05-24
Filing date: 2017-05-24
Publication date: 2020-08-25
Anticipated expiration: 2037-05-24
Also published as: CN108933607A; US10917127B2; US20200091946A1; WO2018214454A1

Abstract

The application discloses radio frequency transmitter belongs to the technical field of communication. The radio frequency transmitter includes: the device comprises a digital-to-analog converter, a passive network, two buffers, a mixer and a power amplifier; two output ends of the digital-to-analog converter are connected with two input nodes of the passive network one by one, and two output ends of the digital-to-analog converter are connected with input ends of the two buffers one by one; the output ends of the two buffers are connected with the two input ends of the frequency mixer one by one; the output end of the mixer is connected with the input end of the power amplifier; the output end of the power amplifier is connected with the antenna; the passive network is used for filtering an input current signal and converting the current signal into a voltage signal. The trans-impedance amplifier in the related technology is replaced by the passive network and the two buffers, so that the noise level and the bandwidth of the radio frequency transmitter are reduced under the same power consumption, and the power consumption of the radio frequency transmitter is reduced under the same noise level.

Description

Radio frequency transmitter

Technical Field

The present application relates to the field of communications technologies, and in particular, to a radio frequency transmitter.

Background

In order to realize communication between devices in a communication system, it is often necessary to transmit signals by modulating the frequency of the signals to a high frequency using a radio frequency transmitter. Currently, a radio frequency transmitter generally comprises a digital-to-analog converter, a filter, a mixer and a power amplifier, wherein the filter is generally a transimpedance amplifier, and the transimpedance amplifier comprises an operational amplifier, a first resistor, a second resistor, a first capacitor and a second capacitor. As shown in fig. 1, two output ends of the digital-to-analog converter are connected with two input ends of the operational amplifier one by one; the first resistor and the first capacitor are connected in parallel between one input end and one output end of the operational amplifier, and the second resistor and the second capacitor are connected in parallel between the other input end and the other output end of the operational amplifier; two output ends of the operational amplifier are connected with two input ends of the frequency mixer one by one; the output end of the mixer is connected with the input end of the power amplifier; the output end of the power amplifier is connected with the antenna.

The working process of the radio frequency transmitter is as follows: after the digital-to-analog converter converts the digital signal into a current signal, the current signal is output to a filter, and the current signal contains noise, such as quantization noise, thermal noise, flicker noise and the like; the filter carries out filtering processing on the input current signal (namely filtering noise in the current signal), and simultaneously converts the current signal into a voltage signal, and then outputs the voltage signal to the mixer; the mixer mixes the input voltage signal with a local oscillator signal to obtain a high-frequency signal, and then outputs the high-frequency signal to the power amplifier; the power amplifier amplifies the power of the input high-frequency signal and transmits the high-frequency signal through the antenna.

Because the transimpedance amplifier needs to realize not only the filtering function but also the current-voltage conversion function, the gain and bandwidth requirements of the operational amplifier included in the transimpedance amplifier are high, and the power consumption of the operational amplifier is high. In addition, the operational amplifier is generally a multi-stage structure because of its high gain requirement. Since noise of the multi-stage operational amplifier is mainly generated at the first stage, in order to reduce the noise of the operational amplifier, it is necessary to increase power consumption of the first stage of the operational amplifier to reduce the noise of the first stage, so as to achieve reduction of the noise of the operational amplifier. However, since the power consumption of the subsequent stage in the multi-stage operational amplifier tends to be several times that of the previous stage, if the power consumption of the first stage of the operational amplifier is increased, the power consumption of the other stages of the operational amplifier will be greater, thereby further causing the power consumption of the operational amplifier to increase.

Disclosure of Invention

In order to solve the problem that the power consumption of an operational amplifier in a radio frequency transmitter in the related art is high, the application provides the radio frequency transmitter. The technical scheme is as follows:

the radio frequency transmitter includes: the device comprises a digital-to-analog converter, a passive network, two buffers, a mixer and a power amplifier;

two output ends of the digital-to-analog converter are connected with two input nodes of the passive network one by one, and two output ends of the digital-to-analog converter are connected with input ends of the two buffers one by one; the output ends of the two buffers are connected with the two input ends of the frequency mixer one by one; the output end of the mixer is connected with the input end of the power amplifier; and the output end of the power amplifier is connected with an antenna.

Specifically, the working process of the radio frequency transmitter is as follows: the digital-to-analog converter converts a digital signal to be transmitted into a current signal and outputs the current signal to the passive network, wherein the current signal contains noise; the passive network carries out filtering processing on the input current signal (namely filtering noise in the current signal), converts the current signal into a voltage signal and outputs the voltage signal to two buffers; the two buffers output the input voltage signals to the mixer; the mixer mixes the input voltage signal with a local oscillator signal to obtain a high-frequency signal, and outputs the high-frequency signal to the power amplifier; the power amplifier amplifies the input high-frequency signal, outputs the high-frequency signal to the antenna, and transmits the high-frequency signal by the antenna.

In the embodiment of the invention, because the passive network does not include the operational amplifier, compared with a scheme of filtering and current-voltage conversion through a trans-impedance amplifier in the related art, the passive network provided by the embodiment of the invention can greatly reduce power consumption.

In addition, because the equivalent input impedance of the two buffers is relatively large, the two buffers are used for isolating the digital-to-analog converter from the mixer, so that a voltage signal obtained after a current signal output by the digital-to-analog converter is processed by the passive network and the two buffers, namely, a voltage signal output to the mixer by the two buffers has relatively large output swing amplitude, and the signal quality of the voltage signal input to the mixer is relatively high.

Furthermore, since both buffers are single-stage structures, the power consumption of both buffers can be used to reduce the noise generated by them, so that compared with the scheme in which the transimpedance amplifier in the related art includes an operational amplifier whose only first stage power consumption is used to reduce the noise generated by it, the two buffers provided by the embodiments of the present invention can have a lower noise level and a higher bandwidth under the same power consumption as the operational amplifier, and the power consumption of both buffers will be lower under the same noise level as the operational amplifier.

The digital-to-analog converter comprises a plurality of first current steering units, wherein each first current steering unit comprises a current source, a first P-Metal-Oxide-Semiconductor (PMOS) tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube;

one end of the current source is connected with an external power supply, and the other end of the current source is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube; the grid electrode of the first PMOS tube is connected with a first signal source, and the first PMOS tube is connected with the third PMOS tube in series in the forward direction; the grid electrode of the second PMOS tube is connected with a second signal source, and the second PMOS tube is connected with the fourth PMOS tube in series in the forward direction; the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are both connected with a third signal source; the drain electrodes of the third PMOS tube and the fourth PMOS tube are connected with two input nodes of the passive network one by one, and the drain electrodes of the third PMOS tube and the fourth PMOS tube are connected with the input ends of the two buffers one by one.

The first PMOS tube and the third PMOS tube are connected in series in the forward direction, namely the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube; the forward serial connection of the second PMOS tube and the fourth PMOS tube means that the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube.

In the embodiment of the invention, the third PMOS tube and the fourth PMOS tube form a common-gate tube, and the common-gate tube formed by the third PMOS tube and the fourth PMOS tube is used for isolating the digital-to-analog converter from the passive network, so that the influence of the fluctuation of the voltage signal output by the passive network on the current signal output by the digital-to-analog converter can be reduced, and the current signal output by the digital-to-analog converter is prevented from generating harmonic waves.

Furthermore, the passive network includes two passive units, one end of each of the two passive units is connected to one of the two output ends of the digital-to-analog converter, and the other end of each of the two passive units is grounded.

In the embodiment of the invention, the external power supply connected with the plurality of first current steering units included in the digital-to-analog converter, the plurality of first current steering units, the two passive units included in the passive network and the ground connected with the two passive units form a current loop, so that the two passive units can filter noise in the input current signals and generate voltage signals at one ends of the two passive units.

The digital-to-analog converter comprises a plurality of second current steering units, wherein each second current steering unit comprises a current source, a first N-Metal-Oxide-Semiconductor (NMOS) tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube;

one end of the current source is grounded, and the other end of the current source is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube respectively; the grid electrode of the first NMOS tube is connected with a first signal source, and the first NMOS tube is connected with the third NMOS tube in series in the forward direction; the grid electrode of the second NMOS tube is connected with a second signal source, and the second NMOS tube is connected with the fourth NMOS tube in series in the forward direction; the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, and the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are both connected with a third signal source; the drain electrodes of the third NMOS tube and the fourth NMOS tube are connected with two input nodes of the passive network one by one, and the drain electrodes of the third NMOS tube and the fourth NMOS tube are connected with the input ends of the two buffers one by one.

The first NMOS tube and the third NMOS tube are connected in series in the forward direction, namely the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube; the forward serial connection of the second NMOS tube and the fourth NMOS tube means that the drain electrode of the second NMOS tube is connected with the source electrode of the fourth NMOS tube.

In the embodiment of the invention, the third NMOS tube and the fourth NMOS tube form a common-gate tube, and the common-gate tube formed by the third NMOS tube and the fourth NMOS tube is used for isolating the digital-to-analog converter from the passive network, so that the influence of the fluctuation of the voltage signal output by the passive network on the current signal output by the digital-to-analog converter can be reduced, and the current signal output by the digital-to-analog converter is prevented from generating harmonic waves.

Furthermore, the passive network includes two passive units, one end of each of the two passive units is connected to one of the two output ends of the digital-to-analog converter, and the other end of each of the two passive units is connected to an external power supply.

In the embodiment of the invention, the ground to which the plurality of second current steering units included in the digital-to-analog converter are connected, the plurality of second current steering units, the two passive units included in the passive network and the external power supply to which the two passive units are connected form a current loop, so that the two passive units can filter noise in the input current signal and generate a voltage signal at one end of the two passive units.

Wherein each of the two passive units comprises a first resistor and a first capacitor, the first resistor being connected in parallel with the first capacitor; alternatively, the first and second electrodes may be,

each passive unit of the two passive units comprises a second resistor, a third resistor, a second capacitor and a third capacitor, the second resistor is connected with the second capacitor in parallel, a circuit formed by the second resistor and the second capacitor is connected with the third capacitor in series, and a circuit formed by the second resistor, the second capacitor and the third capacitor is connected with the third resistor in parallel.

The beneficial effect that technical scheme that this application provided brought is: the radio frequency transmitter comprises a digital-to-analog converter, a passive network, two buffers, a mixer and a power amplifier. When the radio frequency transmitter works, the digital-to-analog converter converts a digital signal to be transmitted into a current signal and outputs the current signal to a passive network; the passive network carries out filtering processing on an input current signal, converts the current signal into a voltage signal and outputs the voltage signal to the mixer through the two buffers; the mixer mixes the input voltage signal with a local oscillator signal to obtain a high-frequency signal, and outputs the high-frequency signal to the power amplifier; the power amplifier amplifies the input high-frequency signal, outputs the high-frequency signal to the antenna, and transmits the high-frequency signal by the antenna. Because the passive network in the radio frequency transmitter does not comprise an operational amplifier, compared with a scheme of filtering and current-voltage conversion through a trans-impedance amplifier in the related art, the passive network provided by the embodiment of the invention can greatly reduce power consumption. In addition, since both buffers in the radio frequency transmitter are of a single-stage structure, the power consumption of both buffers can be used to reduce the noise generated by the buffers, so that compared with a scheme in which the transimpedance amplifier in the related art includes an operational amplifier whose only first stage power consumption is used to reduce the noise generated by the operational amplifier, the two buffers provided by the embodiment of the present invention can have a lower noise level and a higher bandwidth under the same power consumption as the operational amplifier, and the power consumption of both buffers will be lower under the same noise level as the operational amplifier.

Drawings

Fig. 1 is a schematic structural diagram of a radio frequency transmitter provided in the related art;

fig. 2 is a schematic structural diagram of a first radio frequency transmitter according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a second radio frequency transmitter according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a third rf transmitter according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a fourth rf transmitter according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a fifth rf transmitter according to an embodiment of the present invention;

fig. 7(a) is a schematic structural diagram of a passive unit according to an embodiment of the present invention;

fig. 7(b) is a schematic structural diagram of another passive unit provided in the embodiment of the present invention;

FIG. 8(a) is a schematic structural diagram of a buffer according to an embodiment of the present invention;

FIG. 8(b) is a schematic structural diagram of another buffer according to an embodiment of the present invention;

reference numerals:

1: a digital-to-analog converter; 1 a: an output of the digital-to-analog converter; 11: a first current steering unit; 12: a second current steering unit; VDD: an external power supply; CS: a current source; csa: one end of a current source; csb: the other end of the current source; SWN: a first signal source; SWP: a second signal source; vb: a third signal source;

q1: a first PMOS tube; s 1: a source electrode of the first PMOS tube; d 1: the drain electrode of the first PMOS tube; g 1: a grid electrode of the first PMOS tube; q2: a second PMOS tube; s 2: a source electrode of the second PMOS tube; d 2: the drain electrode of the second PMOS tube; g 2: a grid electrode of a second PMOS tube; q3: a third PMOS tube; s 3: a source electrode of a third PMOS tube; d 3: the drain electrode of the third PMOS tube; g 3: a grid electrode of a third PMOS tube; q4: a fourth PMOS tube; s 4: a source electrode of a fourth PMOS tube; d 4: the drain electrode of the fourth PMOS tube; g 4: a grid electrode of a fourth PMOS tube;

q5: a first NMOS transistor; s 5: a source electrode of the first NMOS tube; d 5: the drain electrode of the first NMOS tube; g 5: a grid electrode of the first NMOS tube; q6: a second NMOS transistor; s 6: a source electrode of the second NMOS tube; d 6: the drain electrode of the second NMOS tube; g 6: a grid electrode of the second NMOS tube; q7: a third NMOS transistor; s 7: a source electrode of the third NMOS tube; d 7: the drain electrode of the third NMOS tube; g 7: a grid electrode of a third NMOS tube; q8: a fourth NMOS transistor; s 8: a source electrode of the fourth NMOS tube; d 8: the drain electrode of the fourth NMOS tube; g 8: a grid electrode of a fourth NMOS tube;

2: a passive network; 2 a: an input node of a passive network; 21: a passive unit; 21 a: one end of the passive unit; 21 b: the other end of the passive unit; r1: a first resistor; c1: a first capacitor; r2: a second resistor; r3: a third resistor; c2: a second capacitor; c3: a third capacitor;

3: a buffer; 3 a: an input of a buffer; 3 b: an output of the buffer; q9: a fifth PMOS tube; s 9: a source electrode of a fifth PMOS tube; d 9: a drain electrode of a fifth PMOS tube; g 9: a grid electrode of a fifth PMOS tube; q10: a fifth NMOS transistor; s 10: a source electrode of a fifth NMOS tube; d 10: a drain electrode of a fifth NMOS tube; g 10: a grid electrode of a fifth NMOS tube;

4: a mixer; 4 a: an input of a mixer; 4 b: an output of the mixer;

5: a power amplifier; 5 a: an input of a power amplifier; 5 b: an output of the power amplifier.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Before explaining the embodiments of the present invention in detail, an application scenario related to the embodiments of the present invention will be described. Radio frequency transmitters in communication systems are typically constructed with digital-to-analog converters, filters, mixers, and power amplifiers. In the related art, a filter in a radio frequency transmitter is generally a transimpedance amplifier, and when both gain and bandwidth of an operational amplifier included in the transimpedance amplifier need to be high and noise level of the operational amplifier needs to be low, power consumption of the operational amplifier is often high. Therefore, the embodiments of the present invention provide a radio frequency transmitter, in which a transimpedance amplifier in the related art is replaced with a passive network and two buffers, so as to reduce the noise level and improve the bandwidth of the radio frequency transmitter under the same power consumption, and reduce the power consumption of the radio frequency transmitter under the same noise level. The structure of the radio frequency transmitter provided in the embodiment of the present invention may specifically be a structure of an up-mixing link of the radio frequency transmitter.

Fig. 2 is a schematic structural diagram of a radio frequency transmitter according to an embodiment of the present invention. Referring to fig. 2, the radio frequency transmitter includes: the device comprises a digital-to-analog converter 1, a passive network 2, two buffers 3, a mixer 4 and a power amplifier 5;

two output ends 1a of the digital-to-analog converter 1 are connected with two input nodes 2a of the passive network 2 one by one, and two output ends 1a of the digital-to-analog converter 1 are connected with input ends 3a of the two buffers 3 one by one; the output ends 3b of the two buffers 3 are connected with the two input ends 4a of the mixer 4 one by one; the output 4b of the mixer 4 is connected to the input 5a of the power amplifier 5; the output 5b of the power amplifier 5 is connected to the antenna.

Specifically, the working process of the radio frequency transmitter is as follows: the digital-to-analog converter 1 converts a digital signal to be transmitted into a current signal, and outputs the current signal to the passive network 2, wherein the current signal contains noise; the passive network 2 performs filtering processing on the input current signal (i.e. filtering noise in the current signal), converts the current signal into a voltage signal, and outputs the voltage signal to the two buffers 3; the two buffers 3 output the input voltage signals to the mixer 4; the mixer 4 mixes the input voltage signal with a local oscillator signal to obtain a high-frequency signal, and outputs the high-frequency signal to the power amplifier 5; the power amplifier 5 amplifies the input high-frequency signal, outputs the high-frequency signal to the antenna, and transmits the high-frequency signal from the antenna.

The digital-to-analog converter 1 is a structure capable of converting a digital signal into a current signal, such as a current steering structure, and the like, which is not limited in the embodiment of the present invention. The current signal output by the dac 1 is a difference between currents output by two output terminals 1a of the dac 1, for example, a current output by one output terminal of the two output terminals 1a of the dac 1 is Ip, a current output by the other output terminal is In, and if Ip is positive and In is negative, the current signal output by the dac 1 is Ip-In.

The passive network 2 is a network composed of passive elements, such as a Resistance-Capacitance (RC) network. Since the passive network 2 does not include an operational amplifier, compared with a scheme of filtering and current-voltage conversion through a transimpedance amplifier in the related art, the passive network 2 provided by the embodiment of the invention can greatly reduce power consumption.

The two buffers 3 are each of a single-stage structure, and may be both high-speed buffers or the like. Because the equivalent input impedance of the two buffers 3 is relatively large, the two buffers 3 are used for isolating the digital-to-analog converter 1 from the mixer 4, so that a voltage signal (namely, a voltage signal output to the mixer 4 by the two buffers 3) obtained after a current signal output by the digital-to-analog converter 1 is processed by the passive network 2 and the two buffers 3 has a relatively large output swing, and the signal quality of the voltage signal input to the mixer 4 is relatively high.

In addition, since the two buffers 3 are both single-stage structures, the power consumption of the two buffers 3 can be used to reduce the noise generated by the two buffers 3, so that compared with a scheme in which the transimpedance amplifier in the related art includes an operational amplifier whose only first stage power consumption is used to reduce the noise generated by the operational amplifier, the two buffers 3 provided by the embodiment of the present invention can have a lower noise level and a higher bandwidth under the condition of the same power consumption as the operational amplifier, and the power consumption of the two buffers 3 is lower under the condition of the same noise level as the operational amplifier.

The local oscillation signal is generated by the local oscillation circuit, and after the local oscillation circuit generates the local oscillation signal, the local oscillation signal can be output to the frequency mixer 4, and then the frequency mixer 4 mixes the local oscillation signal with the input voltage signal so as to convert the voltage signal into a high-frequency signal by using the local oscillation signal.

It should be noted that, in practical applications, the digital-to-analog converter 1 may include the following two structures, and of course, the digital-to-analog converter 1 may also have other structures as long as the structure can implement the function of converting the digital signal into the current signal.

The first structure is as follows: referring to fig. 3, the digital-to-analog converter 1 includes a plurality of first current steering units 11, each of which includes a current source CS, a first PMOS transistor Q1, a second PMOS transistor Q2, a third PMOS transistor Q3, and a fourth PMOS transistor Q4;

one end csa of the current source CS is connected to an external power supply VDD, and the other end csb of the current source CS is connected to the source s1 of the first PMOS transistor Q1 and the source s2 of the second PMOS transistor Q2, respectively; a grid g1 of the first PMOS tube Q1 is connected with a first signal source SWN, and the first PMOS tube Q1 is connected with a third PMOS tube Q3 in series in the forward direction; a gate g2 of the second PMOS transistor Q2 is connected with a second signal source SWP, and the second PMOS transistor Q2 is connected with a fourth PMOS transistor Q4 in series in the forward direction; a gate g3 of the third PMOS tube Q3 is connected with a gate g4 of the fourth PMOS tube Q4, and a gate g3 of the third PMOS tube Q3 and a gate g4 of the fourth PMOS tube Q4 are both connected with a third signal source Vb; the drain d3 of the third PMOS transistor Q3 and the drain d4 of the fourth PMOS transistor Q4 are connected to two input nodes 2a of the passive network 2 one by one, and the drain d3 of the third PMOS transistor Q3 and the drain d4 of the fourth PMOS transistor Q4 are connected to the input terminals 3a of the two buffers 3 one by one.

The forward serial connection of the first PMOS transistor Q1 and the third PMOS transistor Q3 means that the drain d1 of the first PMOS transistor Q1 is connected with the source s3 of the third PMOS transistor Q3; the forward serial connection of the second PMOS transistor Q2 and the fourth PMOS transistor Q4 means that the drain d2 of the second PMOS transistor Q2 is connected to the source s4 of the fourth PMOS transistor Q4.

The plurality of first current steering units 11 correspond to a plurality of bits of the digital signal one to one, each first current steering unit in the plurality of first current steering units 11 is configured to convert the corresponding bit in the digital signal into a current signal, and the current signal output by the dac 1 is a sum of the current signals output by the plurality of first current steering units 11.

The current source CS is used to ensure constant current output of the external power supply VDD, that is, the output current of the external power supply VDD is kept constant within a certain load variation range.

For each of the first current steering units 11, the levels of the outputs of the first signal source SWN and the second signal source SWP connected to the first current steering unit are opposite, and at this time, only one of the first PMOS transistor Q1 connected to the first signal source SWN and the second PMOS transistor Q2 connected to the second signal source SWP are turned on at the same time. For example, when the first signal source SWN is at a high level, the second signal source SWP is at a low level, and at this time, the first PMOS transistor Q1 connected to the first signal source SWN is turned on, and the second PMOS transistor Q2 connected to the second signal source SWP is turned off; when the first signal source SWN is at a low level, the second signal source SWP is at a high level, and at this time, the first PMOS transistor Q1 connected to the first signal source SWN is turned off, and the second PMOS transistor Q2 connected to the second signal source SWP is turned on.

In addition, the levels output by the first signal source SWN and the second signal source SWP connected to the first current steering unit are obtained based on the corresponding bits of the first current steering unit in the digital signal. Specifically, one of the first signal source SWN and the second signal source SWP connected to the first current steering unit may directly output a level corresponding to a bit corresponding to the first current steering unit in the digital signal, and the other signal source may output a level obtained by inverting a level corresponding to a bit corresponding to the first current steering unit in the digital signal by the inverter.

The third PMOS transistor Q3 and the fourth PMOS transistor Q4 form a common-gate transistor (cascode transistor), and the common-gate transistor is disposed on an output branch of the current source, so that the output resistance can be increased, and the influence of the change of the output voltage on the output current can be reduced. That is, the common-gate transistor formed by the third PMOS transistor Q3 and the fourth PMOS transistor Q4 is used to isolate the digital-to-analog converter 1 from the passive network 2, so that the influence of the fluctuation of the voltage signal output by the passive network 2 on the current signal output by the digital-to-analog converter 1 can be reduced, and the current signal output by the digital-to-analog converter 1 is prevented from generating harmonic waves.

The level output by the third signal source Vb is generated by a bias circuit, and the third signal source Vb is used for simultaneously controlling the conduction of a third PMOS transistor Q3 and a fourth PMOS transistor Q4 connected with the third signal source Vb, so that the normal operation of the third PMOS transistor Q3 and the fourth PMOS transistor Q4 is ensured.

Further, when the digital-to-analog converter 1 has the above-mentioned first structure, referring to fig. 4, the passive network 2 may include two passive elements 21, one end 21a of the two passive elements 21 is connected to the two output ends 1a of the digital-to-analog converter 1 one by one, and the other end 21b of the two passive elements 21 is grounded.

At this time, the external power source VDD to which the plurality of first current steering units 11 included in the digital-to-analog converter 1 are connected, the plurality of first current steering units 11, the two passive units 21 included in the passive network 2, and the ground to which the two passive units 21 are connected form a current loop, so that the two passive units 21 can filter noise in the input current signal (i.e., filter the current signal), and generate a voltage signal at one end 21a of the two passive units 21 (i.e., convert the current signal into a voltage signal).

The second structure is as follows: referring to fig. 5, the digital-to-analog converter 1 includes a plurality of second current steering units 12, each of which includes a current source CS, a first NMOS transistor Q5, a second NMOS transistor Q6, a third NMOS transistor Q7, and a fourth NMOS transistor Q8;

one end csa of the current source CS is grounded, and the other end csb of the current source CS is respectively connected with the source s5 of the first NMOS transistor Q5 and the source s6 of the second NMOS transistor Q6; a gate g5 of the first NMOS transistor Q5 is connected to a first signal source SWN, and the first NMOS transistor Q5 is connected in series with a third NMOS transistor Q7 in a forward direction; a gate g6 of the second NMOS transistor Q6 is connected to a second signal source SWP, and the second NMOS transistor Q6 is connected in series with a fourth NMOS transistor Q8 in the forward direction; a gate g7 of the third NMOS transistor Q7 is connected with a gate g8 of the fourth NMOS transistor Q8, and a gate g7 of the third NMOS transistor Q7 and a gate g8 of the fourth NMOS transistor Q8 are both connected with a third signal source Vb; the drain d7 of the third NMOS transistor Q7 and the drain d8 of the fourth NMOS transistor Q8 are connected to the two input nodes 2a of the passive network 2 one by one, and the drain d7 of the third NMOS transistor Q7 and the drain d8 of the fourth NMOS transistor Q8 are connected to the input terminals 3a of the two buffers 3 one by one.

The forward serial connection of the first NMOS transistor Q5 and the third NMOS transistor Q7 means that the drain d5 of the first NMOS transistor Q5 is connected to the source s7 of the third NMOS transistor Q7; the forward serial connection of the second NMOS transistor Q6 and the fourth NMOS transistor Q8 means that the drain d6 of the second NMOS transistor Q6 is connected to the source s8 of the fourth NMOS transistor Q8.

The plurality of second current steering units 12 correspond to a plurality of bits of the digital signal one to one, each second current steering unit in the plurality of second current steering units 12 is configured to convert the corresponding bit in the digital signal into a current signal, and at this time, the current signal output by the digital-to-analog converter 1 is a sum of the current signals output by the plurality of second current steering units 12.

For each of the second current steering units 12, the levels of the outputs of the first signal source SWN and the second signal source SWP connected to the second current steering unit are opposite, and at this time, only one of the first NMOS transistor Q5 connected to the first signal source SWN and the second NMOS transistor Q6 connected to the second signal source SWP are turned on at the same time. For example, when the first signal source SWN is at a high level, the second signal source SWP is at a low level, and at this time, the first NMOS transistor Q5 connected to the first signal source SWN is turned on, and the second NMOS transistor Q6 connected to the second signal source SWP is turned off; when the first signal source SWN is at a low level, the second signal source SWP is at a high level, and at this time, the first NMOS transistor Q5 connected to the first signal source SWN is turned off, and the second NMOS transistor Q6 connected to the second signal source SWP is turned on.

In addition, the levels output by the first signal source SWN and the second signal source SWP connected to the second current steering unit are obtained based on the corresponding bits of the second current steering unit in the digital signal. Specifically, one of the first signal source SWN and the second signal source SWP connected to the second current steering unit may directly output a level corresponding to a bit corresponding to the second current steering unit in the digital signal, and the other signal source may output a level obtained by inverting the level corresponding to the bit corresponding to the second current steering unit in the digital signal by the inverter.

The third NMOS transistor Q7 and the fourth NMOS transistor Q8 form a common-gate transistor, and the common-gate transistor is disposed in an output branch of the current source, so that output resistance can be increased, and influence of output voltage variation on output current can be reduced. That is, the common-gate transistor formed by the third NMOS transistor Q7 and the fourth NMOS transistor Q8 is used to isolate the digital-to-analog converter 1 from the passive network 2, so that the influence of the fluctuation of the voltage signal output by the passive network 2 on the current signal output by the digital-to-analog converter 1 can be reduced, and the current signal output by the digital-to-analog converter 1 is prevented from generating harmonic waves.

The level output by the third signal source Vb is generated by a bias circuit, and the third signal source Vb is used for simultaneously controlling the conduction of a third NMOS transistor Q7 and a fourth NMOS transistor Q8 connected to the third signal source Vb, so that the normal operation of the third NMOS transistor Q7 and the fourth NMOS transistor Q8 is ensured.

Further, when the digital-to-analog converter 1 has the second structure, referring to fig. 6, the passive network 2 may include two passive units 21, one end 21a of each of the two passive units 21 is connected to one of the two output terminals 1a of the digital-to-analog converter 1, and the other end 21b of each of the two passive units 21 is connected to the external power supply VDD.

At this time, the ground to which the plurality of second current steering units 12 included in the digital-to-analog converter 1 are connected, the plurality of second current steering units 12, the two passive units 21 included in the passive network 2, and the external power supply VDD to which the two passive units 21 are connected form a current loop, so that the two passive units 21 can filter noise in the input current signal and generate a voltage signal at one end 21a of the two passive units 21.

Both the two passive units 21 in the above two structures may be circuits composed of passive elements. For example, referring to fig. 7(a), each of the two passive cells 21 includes a first resistor R1 and a first capacitor C1, the first resistor R1 being connected in parallel with the first capacitor C1; alternatively, referring to fig. 7(b), each of the two passive cells 21 includes a second resistor R2, a third resistor R3, a second capacitor C2 and a third capacitor C3, the second resistor R2 is connected in parallel with the second capacitor C2, a circuit formed by a second resistor R2 and a second capacitor C2 is connected in series with the third capacitor C3, and a circuit formed by a second resistor R2, a second capacitor C2 and a third capacitor C3 is connected in parallel with the third resistor R3.

It should be noted that, in practical applications, the two passive units 21 may also be configured in other structures according to specific application requirements, as long as the structures can implement a function of filtering an input current signal and a function of converting the input current signal into a voltage signal.

It should be noted that, in practical applications, both the buffers 3 may be the structures shown in fig. 8(a) or the structures shown in fig. 8(b), and of course, both the buffers 3 may also be other structures as long as the equivalent input impedance of the structures is relatively large, and the function of isolating the digital-to-analog converter 1 from the mixer 4 can be achieved.

Wherein, referring to fig. 8(a), each of the two buffers 3 includes a current source CS and a fifth PMOS transistor Q9; one end csa of the current source CS is connected to the external power supply VDD, the other end csb of the current source CS is connected to the source s9 of the fifth PMOS transistor Q9 and one input end 4a of the mixer 4, the gate g9 of the fifth PMOS transistor Q9 is connected to one output end 1a of the digital-to-analog converter 1, and the drain d9 of the fifth PMOS transistor Q9 is grounded.

At this time, since the equivalent input impedance of each of the two buffers 3 including the fifth PMOS transistor Q9 is relatively large, the two buffers 3 can achieve the isolation between the digital-to-analog converter 1 and the mixer 4.

Wherein, referring to fig. 8(b), each of the two buffers 3 includes a current source CS and a fifth NMOS transistor Q10; a drain d10 of the fifth NMOS transistor Q10 is connected to the external power supply VDD, a gate g10 of the fifth NMOS transistor Q10 is connected to an output terminal 1a of the digital-to-analog converter 1, one end csa of the current source CS is connected to a source s10 of the fifth NMOS transistor Q10 and one input terminal 4a of the mixer 4, and the other end csb of the current source CS is grounded.

At this time, since the equivalent input impedance of each of the two buffers 3 including the fifth NMOS transistor Q10 is relatively large, the two buffers 3 can achieve the isolation between the digital-to-analog converter 1 and the mixer 4.

In an embodiment of the invention, the radio frequency transmitter comprises a digital-to-analog converter, a passive network, two buffers, a mixer and a power amplifier. When the radio frequency transmitter works, the digital-to-analog converter converts a digital signal to be transmitted into a current signal and outputs the current signal to a passive network; the passive network carries out filtering processing on an input current signal, converts the current signal into a voltage signal and outputs the voltage signal to the mixer through the two buffers; the mixer mixes the input voltage signal with a local oscillator signal to obtain a high-frequency signal, and outputs the high-frequency signal to the power amplifier; the power amplifier amplifies the input high-frequency signal, outputs the high-frequency signal to the antenna, and transmits the high-frequency signal by the antenna. Because the passive network in the radio frequency transmitter does not comprise an operational amplifier, compared with a scheme of filtering and current-voltage conversion through a trans-impedance amplifier in the related art, the passive network provided by the embodiment of the invention can greatly reduce power consumption. In addition, since both buffers in the radio frequency transmitter are of a single-stage structure, the power consumption of both buffers can be used to reduce the noise generated by the buffers, so that compared with a scheme in which the transimpedance amplifier in the related art includes an operational amplifier whose only first stage power consumption is used to reduce the noise generated by the operational amplifier, the two buffers provided by the embodiment of the present invention can have a lower noise level and a higher bandwidth under the same power consumption as the operational amplifier, and the power consumption of both buffers will be lower under the same noise level as the operational amplifier.

The above-mentioned embodiments are provided not to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A radio frequency transmitter, characterized in that the radio frequency transmitter comprises: the device comprises a digital-to-analog converter, a passive network, two buffers, a mixer and a power amplifier;

two output ends of the digital-to-analog converter are connected with two input nodes of the passive network one by one, and two output ends of the digital-to-analog converter are connected with input ends of the two buffers one by one; the output ends of the two buffers are connected with the two input ends of the frequency mixer one by one; the output end of the mixer is connected with the input end of the power amplifier; the output end of the power amplifier is connected with an antenna; the passive network is used for filtering an input current signal and simultaneously converting the current signal into a voltage signal, and the two buffers are both single-stage high-speed buffers;

the passive network comprises two passive units, one ends of the two passive units are connected with two output ends of the digital-to-analog converter one by one, and the other ends of the two passive units are grounded; or the passive network comprises two passive units, one ends of the two passive units are connected with the two output ends of the digital-to-analog converter one by one, and the other ends of the two passive units are connected with an external power supply;

each of the two buffers comprises a current source and a fifth PMOS (p-channel metal oxide semiconductor) tube, one end of the current source is connected with an external power supply, the other end of the current source is respectively connected with a source electrode of the fifth PMOS and one input end of the mixer, a grid electrode of the fifth PMOS tube is connected with one output end of the digital-to-analog converter, and a drain electrode of the fifth PMOS tube is grounded; or each of the two buffers comprises a current source and a fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with an external power supply, the grid electrode of the fifth NMOS tube is connected with one output end of the digital-to-analog converter, one end of the current source is respectively connected with the source electrode of the fifth NMOS tube and one input end of the mixer, and the other end of the current source is grounded.

2. The radio frequency transmitter of claim 1, wherein the digital-to-analog converter includes a plurality of first current steering units, each first current steering unit including a current source, a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;

3. The radio frequency transmitter of claim 1, wherein the digital-to-analog converter includes a plurality of second current steering units, each second current steering unit including a current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

4. The radio frequency transmitter of claim 1, wherein each of the two passive elements includes a first resistor and a first capacitor, the first resistor being connected in parallel with the first capacitor; alternatively, the first and second electrodes may be,