CN108898228A - A kind of quantum adder designs method for not destroying source operand - Google Patents
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Abstract
The present invention provides a kind of quantum adder designs method for not destroying source operand, belongs to quantum wire design field.6 fundamental quantity cervicals orifice of uterus of parallel computation are convenient in present invention design, then quantum half adder, quantum full adder and corresponding restorer are designed on this basis, and the n design methods for not destroying source operand adder are constituted by quantum half adder, quantum full adder and corresponding restorer.It is an advantage of the invention that devising restorer, so that the source operand for participating in operation is not destroyed, while quantum information processing is embodied in the high efficiency of signal processing：12n-3 basic operation is only needed to achieve that n Integral additive operations, and time complexity is only 6n+3.
Description
Technical field
The present invention relates to quantum wire design fields, are specifically related to a kind of quantum addition for not destroying source operand
Device design method.
Background technique
Quantum computer has unique processing data capability, can solve the insoluble mathematics of existing classic computer and ask
Topic, such as the prime factorization and discrete logarithm of big number solve, and therefore, it becomes countries in the world Strategic Competition focus.Adder
It is quantum computer important component, is different from traditional counting, quantum calculation has unclonable characteristic, therefore research does not destroy source
The adder calculator of operand is very valuable.
In quantum calculation, information unit is indicated with quantum bit, and there are two basic quantum states for it | 0>With | 1>, fundamental quantity
Sub- state is referred to as ground state.One quantum bit can be the linear combination of two ground state, be commonly referred to as superposition state, be represented by | ψ
>=a | 0>+b|1>, wherein a and b is two plural numbers.
Tensor product is to be combined small vector space, constitutes a kind of method of bigger vector space, uses symbolTable
Show.For two ground state | u>With | v>, their tensor productCommon dummy suffix notation | uv>, | u>|v>Or | u, v>It indicates,
Such as ground state | 0>With | 1>, their tensor product is represented by
For the n times tensor product of matrix UIt can write a Chinese character in simplified form intoFor quantum state | u>N times tensor productIt can also write a Chinese character in simplified form into
Quantum wire can be made of the quantum bit door of a sequence, in the expression figure of quantum wire, every line all tables
Show the line of quantum wire, the execution sequence of quantum wire is from left to right.What quantum bit door can be convenient uses matrix form
It indicates.The quantum door of n quantum bit can use one 2n×2nUnitary matrice U indicate, i.e.,Wherein U+It is the conjugation of U
Transposed matrix, I are unit matrix,It is the n times tensor product of I.X (NOT gate), V and V+It is three common single quantum bit doors,
Their matrix indicates：
Wherein i is imaginary unit.
Most important muliti-qubit door be it is U controlled, by control quantum bit and target quantum bit, when control bit is
It when 1, is indicated with stain, when control bit is 0, is shown by white dots.Work as U=X, V, V+, at this time controlled U be referred to as it is controlled non-
Door, V controlled, controlled V+Fig. 1 is shown in door, their symbol expression.
One important performance indexes of quantum wire are the complexity of route.The complexity of route is divided into quantum cost complexity
Degree and quantum time complexity.Controlled not-gate, V controlled, controlled V+The quantum cost and runing time complexity of door are all 1.
The quantum cost of quantum wire refers to controlled not-gate in route, V controlled, controlled V+Total quantity of door.Quantum wire when
Between complexity be quantum door in parallel working line total time.
Summary of the invention
The present invention provides a kind of quantum adder for not destroying source operand, is convenient for 6 bases of parallel computation including designing
Then this quantum door designs quantum half adder, quantum full adder and corresponding restorer on this basis, and is added by quantum half
Device, quantum full adder and corresponding restorer constitute the n design methods for not destroying source operand adder, realize quantum information
Handle the high efficiency in signal processing：12n-3 basic operation is only needed to achieve that n Integral additive operations.
Technical solution of the present invention：
The present invention utilizes three kinds of controlled doors of basic quantum (i.e.：It is controlled not-gate, V and controlled quantum full adder V controlled+Door)
To construct the realization route for not destroying source operand.
Invention specific design scheme and step be：
1, the design of 6 fundamental quantity cervicals orifice of uterus
6 fundamental quantity cervical orifice of uterus designed lines are realized using 3 controlled doors, use symbol Q respectively1、Q2、Q3、Q4、Q5And Q6Table
Show.Q1、Q2、Q5And Q6Quantum cost and quantum time complexity be all 3, Q3And Q4Quantum cost and quantum time complexity
It is 4.Their structure is respectively：Elementary gate Q1And Q2It is all by 1 V controlled, 1 controlled V+Door, a controlled not-gate and 3
Quantum bit line is constituted；Elementary gate Q3By 2 V controlled, a controlled not-gates, 1 controlled V+Door and 3 quantum bit lines；
Elementary gate Q4By 2 controlled V+Door, a controlled not-gate, 1 controlled V and 3 quantum bit lines；Elementary gate Q5It is controlled by 2
V, a controlled not-gate and 4 quantum bit lines are constituted；Elementary gate Q6By 1 it is V controlled, 1 it is V+ controlled, one it is controlled
NOT gate and 4 quantum bit lines are constituted；
It should be noted that by Q3It is applied to | 0>|b0>|a0>, obtain
2, the design of quantum half adder and restorer
Utilize V controlled, elementary gate P2The quantum half adder designed lines in Fig. 3 are realized, with symbol A1It indicates.
Quantum half adder is applied to quantum state | 0>|b0>|a0>, obtain
WhereinIt is xor operation, b0, a0∈ { 0,1 }.Quantum half adder realizes addition (b known to formula (1)0+a0),
First quantum bit of middle output | a0b0>Store addition (b0+a0) carry information, second quantum bit of outputStorage be addition and.
In order not to destroy source operand, the restorer of the design such as quantum half adder of Fig. 4, it is by controlled V and elementary gate
P3It constitutes, with symbol R1It indicates.
The restorer of quantum half adder is applied to quantum stateIt obtains
WhereinIt is xor operation, b0, a0∈ { 0,1 }.The restorer of quantum half adder will known to formula (2)It is reset to | b0>|a0>。
Quantum wire is analyzed, the quantum cost and time complexity that quantum half adder and corresponding restorer can be obtained all are
4。
3, the design of quantum full adder and restorer
Utilize elementary gate P1And P5Quantum full adder designed lines are realized, with symbol A2It indicates.
Quantum full adder is applied to quantum state | 0>|bi>|ai>|ci-1>, obtain
WhereinIt is xor operation, bi, ai, ci-1∈ { 0,1 }.Quantum full adder realizes addition (b known to formula (3)i+ai
+ci-1), wherein first quantum bit exportedStore addition (bi+ai+ci-1) carry information, it is defeated
Second quantum bit outStorage be addition and.
In order not to destroy source operand, the restorer of the design such as quantum full adder of Fig. 6, it is by elementary gate P3And P6Composition,
With symbol R2It indicates.
The restorer of quantum full adder is applied to quantum state?
It arrives
WhereinIt is xor operation, bi, ai, ci-1∈ { 0,1 }.The restorer of quantum full adder will known to formula (4)It is reset to | bi>。
Quantum wire is analyzed, the quantum cost and time complexity that quantum full adder and restorer can be obtained are 6.
4, n quantum bit does not destroy the design of source operand adder
Realize that the n quantum bit in Fig. 7 does not destroy source and grasps using quantum half adder, quantum full adder and corresponding restorer
The quantum adder designs route counted, with symbol ADIt indicates.N quantum bit do not destroy the quantum adder of source operand by
(n-1) a quantum full adder and restorer (and are decomposed into n-1 elementary gate P1、P5、P6And P3), 1 quantum half adder, 1
The restorer of quantum half adder and a controlled not-gate are constituted.It realizes the two n add operations for not destroying source operand.
Assuming that n integers a and b are stored in the ground state of following two n quantum bits：
Wherein an-1an-2...a0And bn-1bn-2...b0It is the binary representation of integer a and b, a respectivelyh, bh∈ { 0,1 }, h
=0 ..., n-1.
Add the quantum ground state of n quantum bitThe service bit of add operation the most, and put in order to obtain | 00bn- 1an-10bn-2an-2...0b0a0>As input.Adder is applied to | 00bn-1an-10bn-2an-2...0b0a0>, obtain
AD|00bn-1an-10bn-2an-2...0b0a0>=| snsn-1bn-1an-1sn-2bn-2an-2...s0b0a0> (6)
Wherein s=a+b, snsn-1sn-2...s0It is the binary representation of integer s, sh∈ { 0,1 }, h=0 ..., n.
By formula (6) it is found that adder realizes following add operation：
Quantum wire is analyzed, can obtain realizing that the quantum cost of the adder for not destroying source operand of n integers is 6
(n-1)+6 (n-1)+2 × 4+1=12n-3, n >=2, (n-1) a elementary gate P1With an elementary gate P2Parallel operation, (n-1) is a
Elementary gate P3With an elementary gate P4Parallel operation, therefore wire time complexity is 3 (n-1)+3 (n-1)+2 × 4+1=6n+3,
N >=2, this has fully demonstrated the high efficiency of this patent design addition circuit.
Advantages of the present invention is with effect：
The present invention solves the problems, such as " not destroying the quantum add operation of source operand ", devises one and does not destroy source operation
Several quantum adders.The invention has the advantages that restorer is devised, so that the source operand for participating in operation is not destroyed, while body
Quantum information processing is showed in the high efficiency of signal processing：12n-3 basic operation is only needed to achieve that n addition of integer fortune
It calculates, and time complexity is only 6n+3.
Detailed description of the invention
Fig. 1 is the title and symbol table diagram of quantum bit door of the present invention；
Fig. 2 is the line map and corresponding schematic diagram of 6 elementary gates of the invention；
Fig. 3 is that the quantum of quantum half adder of the present invention realizes line map；
Fig. 4 is that the quantum of the restorer of quantum half adder of the present invention realizes line map；
Fig. 5 is that the quantum of quantum full adder of the present invention realizes line map；
Fig. 6 is that the quantum of the restorer of quantum full adder of the present invention realizes line map；
Fig. 7 is the quantum realization line map that the present invention does not destroy source operand quantum adder；
Fig. 8 is the quantum realization line map that the present invention one does not destroy source operand quantum add operation example.
Specific embodiment
The invention will be further described with reference to embodiments.
As shown in figures 1-8, detailed process is as follows,
1, the design of 6 fundamental quantity cervicals orifice of uterus
6 fundamental quantity cervical orifice of uterus designed lines in Fig. 2 are realized using 3 controlled doors, use symbol Q respectively1、Q2、Q3、Q4、Q5
And Q6It indicates.Q1、Q2、Q5And Q6Quantum cost and quantum time complexity be all 3, Q3And Q4Quantum cost and the quantum time
Complexity is 4.Their structure is respectively：Elementary gate Q1And Q2It is all by 1 V controlled, 1 controlled V+Door, one it is controlled non-
Door and 3 quantum bit lines are constituted；Elementary gate Q3By 2 V controlled, a controlled not-gates, 1 controlled V+Door and 3 quantum bits
Line；Elementary gate Q4By 2 controlled V+Door, a controlled not-gate, 1 controlled V and 3 quantum bit lines；Elementary gate Q5By 2
A controlled V, a controlled not-gate and 4 quantum bit lines are constituted；Elementary gate Q6By 1 it is V controlled, 1 it is V+ controlled, one
A controlled not-gate and 4 quantum bit lines are constituted；
It should be noted that by Q3It is applied to | 0>|b0>|a0>, obtain
2, the design of quantum half adder and restorer
Utilize V controlled, elementary gate P2The quantum half adder designed lines in Fig. 3 are realized, with symbol A1It indicates.
Quantum half adder is applied to quantum state | 0>|b0>|a0>, obtain
WhereinIt is xor operation, b0, a0∈ { 0,1 }.Quantum half adder realizes addition (b known to formula (1)0+a0),
First quantum bit of middle output | a0b0>Store addition (b0+a0) carry information, second quantum bit of outputStorage be addition and.
In order not to destroy source operand, the restorer of the design such as quantum half adder of Fig. 4, it is by controlled V and elementary gate
P3It constitutes, with symbol R1It indicates.
The restorer of quantum half adder is applied to quantum stateIt obtains
WhereinIt is xor operation, b0, a0∈ { 0,1 }.The restorer of quantum half adder will known to formula (2)It is reset to | b0>|a0>。
Quantum wire in analysis chart 3 and Fig. 4, can be obtained quantum half adder and corresponding restorer quantum cost and when
Between complexity be all 4.
3, the design of quantum full adder and restorer
Utilize elementary gate P1And P5The quantum full adder designed lines in Fig. 5 are realized, with symbol A2It indicates.
Quantum full adder is applied to quantum state | 0>|bi>|ai>|ci-1>, obtain
WhereinIt is xor operation, bi, ai, ci-1∈ { 0,1 }.Quantum full adder realizes addition (b known to formula (3)i+ai
+ci-1), wherein first quantum bit exportedStore addition (bi+ai+ci-1) carry information, it is defeated
Second quantum bit outStorage be addition and.
In order not to destroy source operand, the restorer of the design such as quantum full adder of Fig. 6, it is by elementary gate P3And P6Composition,
With symbol R2It indicates.
The restorer of quantum full adder is applied to quantum state?
It arrives
WhereinIt is xor operation, bi, ai, ci-1∈ { 0,1 }.The restorer of quantum full adder will known to formula (4)It is reset to | bi>。
Quantum wire in analysis chart 5 and Fig. 6, quantum cost and the time that quantum full adder and restorer can be obtained are complicated
Degree is 6.
4, n quantum bit does not destroy the design of source operand adder
Realize that the n quantum bit in Fig. 7 does not destroy source and grasps using quantum half adder, quantum full adder and corresponding restorer
The quantum adder designs route counted, with symbol ADIt indicates.N quantum bit do not destroy the quantum adder of source operand by
(n-1) a quantum full adder and restorer (and are decomposed into n-1 elementary gate P1、P5、P6And P3), 1 quantum half adder, 1
The restorer of quantum half adder and a controlled not-gate are constituted.It realizes the two n add operations for not destroying source operand.
Assuming that n integers a and b are stored in the ground state of following two n quantum bits：
Wherein an-1an-2...a0And bn-1bn-2...b0It is the binary representation of integer a and b, a respectivelyh, bh∈ { 0,1 }, h
=0 ..., n-1.
Add the quantum ground state of n quantum bitThe service bit of add operation the most, and put in order to obtain | 00bn- 1an-10bn-2an-2...0b0a0>As input.Adder is applied to | 00bn-1an-10bn-2an-2...0b0a0>, obtain
AD|00bn-1an-10bn-2an-2...0b0a0>=| snsn-1bn-1an-1sn-2bn-2an-2...s0b0a0> (6)
Wherein s=a+b, snsn-1sn-2...s0It is the binary representation of integer s, sh∈ { 0,1 }, h=0 ..., n.
By formula (6) it is found that adder realizes following add operation：
Quantum wire in analysis chart 7 can obtain the quantum generation for realizing the adder for not destroying source operand of n integers
Valence is 6 (n-1)+6 (n-1)+2 × 4+1=12n-3, n >=2, (n-1) a elementary gate P1With an elementary gate P2Parallel operation, (n-
1) a elementary gate P3With an elementary gate P4Parallel operation, therefore wire time complexity is 3 (n-1)+3 (n-1)+2 × 4+1=
6n+3, n >=2, this has fully demonstrated the high efficiency of this patent design addition circuit.
Enable n=3, it is assumed that 3 integers a and b are stored in the ground state of following two 3 quantum bits：
Wherein a2a1a0And b2b1b0It is the binary representation of integer a and b, a respectivelyh, bh∈ { 0,1 }, h=0 ..., 2.
Design adder realizes following add operation：
Specific implementation process is：Add the quantum ground state of 4 quantum bitsThe service bit of add operation the most, and arrange
Sequence obtains | 00b2a20b1a10b0a0>As input, adder is applied to | 00b2a20b1a10b0a0>, obtain
AD|00b2a20b1a10b0a0>=| s3s2b2a2s1b1a1s0b0a0> (10)
Wherein s=a+b, s3s2s1s0It is the binary representation of integer s, sh∈ { 0,1 }, h=0 ..., 3.
Route is realized as shown in figure 8, it is by elementary gate P1、P5、P6And P3Each 2, P2And P4Each 1,2 controlled V and
One controlled not-gate composition, the quantum cost of route are 33, and the time complexity of route is 21.
The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to embodiment,
Those skilled in the art can also make various equivalent modifications on the premise of not violating the inventive spirit of the present invention
Or replacement, these equivalent variation or replacement are all contained in scope of the present application.
Claims (5)
1. one is not destroyed the quantum adder designs method of source operand, which is characterized in that the method is controlled using quantum
6 fundamental quantity cervicals orifice of uterus of parallel computation are convenient in door design, then complete using 6 fundamental quantity cervical orifice of uterus design quantum half adders, quantum
Add device and corresponding restorer, finally constitutes n using quantum half adder, quantum full adder and the setting of corresponding restorer and do not break
The design method of bad source operand adder.
2. one according to claim 1 is not destroyed the quantum adder designs method of source operand, it is characterized in that, designs
The detailed process of 6 fundamental quantity cervicals orifice of uterus is：
6 fundamental quantity cervical orifice of uterus designed lines are realized using 3 controlled doors, use symbol P respectively1、P2、P3、P4、P5And P6It indicates, 6
The quantum cost and quantum time complexity of fundamental quantity cervical orifice of uterus designed lines are all 3, and structure is respectively：Elementary gate P1By 2 by
Control V, a controlled not-gate and 3 quantum bit lines are constituted；Elementary gate P2By 1 it is V controlled, 1 it is V+ controlled, one by
It controls NOT gate and 3 quantum bit lines is constituted；Elementary gate P3By 2 V controlled, controlled not-gates and 3 quantum bit line structures
At；Elementary gate P4It is made of 2 V controlled, controlled not-gates and 3 quantum bit lines；Elementary gate P5By 1 it is V controlled, 1
A controlled V+, a controlled not-gate and 4 quantum bit lines are constituted；Elementary gate P6By 2 V controlled, controlled not-gates
It is constituted with 4 quantum bit lines.
3. one according to claim 1 is not destroyed the quantum adder designs method of source operand, it is characterized in that, designs
The realization process of quantum half adder and corresponding restorer is：
Utilize V controlled, elementary gate P2Quantum half adder designed lines are realized, with symbol A1It indicates,
Quantum half adder is applied to quantum state | 0>|b0>|a0>, obtain
WhereinIt is xor operation, b0, a0∈ { 0,1 }.Quantum half adder realizes addition (b known to formula (1)0+a0), wherein defeated
First quantum bit out | a0b0>Store addition (b0+a0) carry information, second quantum bit of output
Storage be addition and；
Source operand is not destroyed, designs the restorer of quantum half adder, it is by controlled V and elementary gate P3It constitutes, with symbol R1Table
Show；
The restorer of quantum half adder is applied to quantum stateIt obtains
WhereinIt is xor operation, b0, a0∈ { 0,1 }.The restorer of quantum half adder will known to formula (2)
It is reset to | b0>|a0>；
The quantum cost and time complexity of quantum half adder and corresponding restorer are all 4.
4. one according to claim 1 is not destroyed the quantum adder designs method of source operand, it is characterized in that, designs
The realization process of quantum full adder and corresponding restorer is：
Utilize elementary gate P1And P5Quantum full adder designed lines are realized, with symbol A2It indicates；
Quantum full adder is applied to quantum state | 0>|bi>|ai>|ci-1>, obtain
WhereinIt is xor operation, bi, ai, ci-1∈ { 0,1 }, quantum full adder realizes addition (b known to formula (3)i+ai+
ci-1), wherein first quantum bit exportedStore addition (bi+ai+ci-1) carry information, it is defeated
Second quantum bit outStorage be addition and；
Source operand is not destroyed, the restorer of quantum full adder is designed, it is by elementary gate P3And P6Composition, with symbol R2It indicates；
The restorer of quantum full adder is applied to quantum stateIt obtains
WhereinIt is xor operation, bi, ai, ci-1∈ { 0,1 }.The restorer of quantum full adder will known to formula (4)It is reset to | bi>；
The quantum cost and time complexity of quantum full adder and restorer are 6.
5. one according to claim 1 is not destroyed the quantum adder designs method of source operand, it is characterized in that, designs
The realization process that n quantum bits do not destroy source operand adder is：
Realize that n quantum bit does not destroy the quantum of source operand using quantum half adder, quantum full adder and corresponding restorer
Adder designs route, with symbol ADIt indicates, n quantum bit does not destroy the quantum adder of source operand by (n-1) a quantum
Full adder and restorer (and it is decomposed into n-1 elementary gate P1、P5、P6And P3), 1 quantum half adder, 1 quantum half adder
Restorer and controlled not-gate constitute, realize the two n add operations for not destroying source operand；
Assuming that n integers a and b are stored in the ground state of following two n quantum bits：
Wherein an-1an-2...a0And bn-1bn-2...b0It is the binary representation of integer a and b, a respectivelyh, bh∈ { 0,1 }, h=
0 ..., n-1；
Add the quantum ground state of n quantum bitThe service bit of add operation the most, and put in order to obtain | 00bn-1an- 10bn-2an-2...0b0a0>As input, adder is applied to | 00bn-1an-10bn-2an-2...0b0a0>, obtain
AD|00bn-1an-10bn-2an-2...0b0a0>=| snsn-1bn-1an-1sn-2bn-2an-2...s0b0a0>(6) wherein s=a+b,
snsn-1sn-2...s0It is the binary representation of integer s, sh∈ { 0,1 }, h=0 ..., n；
By formula (6) it is found that adder realizes following add operation：
The quantum cost for realizing the adder for not destroying source operand of n integers is 6 (n-1)+6 (n-1)+2 × 4+1=12n-
3, n >=2, (n-1) a elementary gate P1With an elementary gate P2Parallel operation, (n-1) a elementary gate P3With an elementary gate P4Parallel
Operation, therefore wire time complexity is 3 (n-1)+3 (n-1)+2 × 4+1=6n+3, n >=2.
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Cited By (2)
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| CN110417545A (en) * | 2019-06-28 | 2019-11-05 | 中国人民解放军战略支援部队信息工程大学 | Finite field discrete logarithm quantum solves line optimization building method |
| CN111598249A (en) * | 2020-05-19 | 2020-08-28 | 北京百度网讯科技有限公司 | Method, apparatus, classical computer and storage medium for determining approximate quantum gate |
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