CN108880204A - Chaotic frequency modulation digital switch power control circuit based on FPGA - Google Patents
Chaotic frequency modulation digital switch power control circuit based on FPGA Download PDFInfo
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- CN108880204A CN108880204A CN201811018393.3A CN201811018393A CN108880204A CN 108880204 A CN108880204 A CN 108880204A CN 201811018393 A CN201811018393 A CN 201811018393A CN 108880204 A CN108880204 A CN 108880204A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Manipulation Of Pulses (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention discloses a kind of chaotic frequency modulation digital switch power control circuit based on FPGA, including PID duty cycle parameters counting circuit, chaos sequence generation circuit, chaotic Signals Processing circuit, digital pulse width modulation circuit；The PID duty cycle parameters counting circuit is electrically connected with digital pulse width modulation circuit；The chaos sequence generation circuit is electrically connected with chaotic Signals Processing circuit；The chaotic Signals Processing circuit is electrically connected with digital pulse width modulation circuit；The digital pulse width modulation circuit is electrically connected with circuit output signal.The chaotic modulation of numerical control switch power switch frequency may be implemented in the circuit, and modulation range is controllable, can inhibit the electromagnetic interference of numerical control switch power supply, can be used for the design of digitizing switch power supply control chip.
Description
Technical field
The present invention relates to power electronics control technology fields, are to be related to a kind of pulsewidth tune of chaos frequency more specifically
System modulation FPGA control circuit, inhibits to control it is suitable for the electromagnetic interference of digital switch power supply.
Background technique
Due to the distinctive programmability of numerical control switch power supply, portability, the characteristics such as multi-functional control can be achieved, gets over it
The favor by market is got over, however input current and switch tube voltage due to Switching Power Supply is rich in causes electromagnetism dry
The switching frequency harmonic components of noise are disturbed, energy concentrates at switching frequency and its frequency multiplication, forms serious electromagnetic interference.It answers
Noise harmonic frequency can be dispersed with chaotic frequency modulation technology, reduce discrete harmonic amplitude, be power spectrum in continuous frequency spectrum
Characteristic inhibits electromagnetic interference.And at present especially in digital switch power supply control field, also lack economical and effective, versatile
Chaotic frequency modulation scheme.
Summary of the invention
The purpose of the present invention is to provide a kind of chaotic frequency modulation digital switch power control circuit based on FPGA, can
To realize the chaotic modulation of switching frequency, modulation range can effectively can inhibit the electricity of digital switch power supply by parameter setting
Magnetic disturbance.
The present invention the technical solution to solve the technical problem is that：A kind of chaotic frequency modulation digital switch electricity based on FPGA
Source control circuit, it is characterised in that：Including PID duty cycle parameters counting circuit, chaos sequence generation circuit, chaotic Signals Processing
Circuit, digital pulse width modulation circuit；The PID duty cycle parameters counting circuit is electrically connected with digital pulse width modulation circuit
It connects；The chaos sequence generation circuit is electrically connected with chaotic Signals Processing circuit；The chaotic Signals Processing circuit with
Digital pulse width modulation circuit is electrically connected；The digital pulse width modulation circuit is electrically connected with circuit output signal.
In the chaos sequence generation circuit, the output end and data selector of the failing edge Single Pulse1 that is delayed
The data selection port of Multiplexe1 is connected, the output end and data selector of data selector Multiplexe2
The zero-input terminal of Multiplexe1 is connected, constant Constant1 chaotic maps initial value and data selector Multiplexe1
One-input terminal be connected, the output end of data selector Multiplexe1 and the input terminal of chaotic maps functional circuit and
The one-input terminal of Multiplexe2 is connected, the zero-input terminal phase of the output end and Multiplexe2 of chaotic maps functional circuit
Even, the data of data selector Multiplexe2 selection end and the Comparator1's of several comparator word pulse-width modulation circuits is defeated
Outlet is connected, and output end, that is, chaos sequence Nc of data selector Multiplexe2 is connected with chaotic Signals Processing circuit；Whenever
When the output end of Comparator1 is that the new switch periods of low level i.e. start, a new chaos number Nc is generated.
In the chaotic Signals Processing circuit, the output end, that is, chaos sequence and data/address bus AltBus1 of Multiplexe2
Input terminal be connected, the output end of data/address bus AltBus1 is connected with an input terminal of multiplier Product1, constant
Constant2 chaotic frequency modulation degree parameter Re is connected with another input terminal of Product1, the output end of Product1 with
The zero-input terminal of data selector Multiplexe3 is connected, and constant Constant3 fixed cycle deviant N ' and data select
The one-input terminal of device Multiplexe3 is connected, input signal In2, that is, chaotic frequency modulation switching signal and Multiplexe3's
Data selection port is connected, and the output end of Multiplexe3 is connected with an input terminal of adder Adder1, constant
Constant4 period addend N is connected with another input terminal of adder Adder1, the output end of adder Adder1 and delay
The input terminal of cells D elay1 is connected, output end, that is, switch periods number N of delay unit Delay1TWith digital pulse width modulation circuit
It is connected；When input signal In2, that is, chaotic frequency modulation switching signal is high level, switch periods number NTFor fixed value N '+N,
Then switching frequency is fixed value f/ (N '+N), and wherein f is the work clock of accumulator Inc1, when input signal In2, that is, chaos frequency
When rate modulation switch signal is low level, switch periods number NTFor chaos change value NcRe+N, then switching frequency is chaos tune
Value f/ (NcRe+N) processed, each new switch periods determine switching frequency by Nc, and the size of Re determines warble rate,
Re is bigger, and switching frequency variation range is bigger.
In the PID duty cycle parameters counting circuit and digital pulse-width modulation circuit, input signal In1, that is, power supply feedback
Signal is connected with the input terminal of PID duty cycle parameters counting circuit, output end, that is, duty ratio of PID duty cycle parameters counting circuit
Parameter D is connected with " b " input terminal of comparator Comparator2, the output end and comparator Comparator2 of accumulator Inc1
" a " input terminal be connected with " b " input terminal of comparator Comparator1, the output end of Comparator2 and accumulator Inc1
Reset terminal be connected, " a " input terminal of Comparator1 and switch periods number NTIt is connected, the output of comparator Comparator2
End is connected with " R " input terminal of S-R trigger, the output end of comparator Comparator1 and " S " input terminal of S-R trigger
It is connected, output end Q, that is, switching pulse of S-R trigger is connected with the output signal Out of circuit；When being reset to for accumulator Inc1
0 when starting counting that i.e. a new switch periods start, and switching pulse exports high level, once accumulator Inc1 is greater than duty ratio
Parameter D, switching pulse just lock output low level until accumulator Inc1 is greater than NT, a switch periods terminate, then add up
Device Inc1 is reset to 0, starts a new switch periods.
The beneficial effects of the invention are as follows：The chaotic modulation of numerical control switch power switch frequency may be implemented, modulation range can
Control, can inhibit the electromagnetic interference of numerical control switch power supply, can be used for the design of digitizing switch power supply control chip.
Detailed description of the invention
Fig. 1 is schematic block circuit diagram of the present invention.
Specific embodiment
The present invention is that FPGA circuitry realizes design scheme, and wherein chaotic maps functional circuit and PID duty cycle parameters calculate
Conventional design scheme can be used as circuit module in circuit.
A kind of chaotic frequency modulation digital switch power control circuit based on FPGA, including PID duty cycle parameters calculate
Circuit 3, chaos sequence generation circuit 1, chaotic Signals Processing circuit 2, digital pulse width modulation circuit 4；The PID duty cycle parameters
Counting circuit is electrically connected with digital pulse width modulation circuit；The chaos sequence generation circuit and chaotic Signals Processing circuit
It is electrically connected；The chaotic Signals Processing circuit is electrically connected with digital pulse width modulation circuit；The digital pulse width
Modulation circuit is electrically connected with circuit output signal.
Chaos sequence generation circuit include failing edge Single Pulse1, data selector Multiplexe1 and
Multiplexe2, constant Constant1 chaotic maps initial value, chaotic maps functional circuit；The chaos sequence generation circuit
In, the output end of delay failing edge Single Pulse1 is connected with the data selection port of data selector Multiplexe1,
The output end of data selector Multiplexe2 is connected with the zero-input terminal of data selector Multiplexe1, constant
Constant1 chaotic maps initial value is connected with the one-input terminal of data selector Multiplexe1, data selector
The output end of Multiplexe1 is connected with the one-input terminal of the input terminal of chaotic maps functional circuit and Multiplexe2, mixes
The output end of ignorant mapping function circuit is connected with the zero-input terminal of Multiplexe2, the number of data selector Multiplexe2
It is connected according to selection end with the output end of the Comparator1 of number comparator word pulse-width modulation circuit, data selector
The output end of Multiplexe2, that is, chaos sequence Nc is connected with chaotic Signals Processing circuit；Whenever the output end of Comparator1
When starting for the new switch periods of low level i.e., a new chaos number Nc is generated.Chaos sequence generation circuit, effect
When being that each new switch periods starts, a new chaos number Nc is generated, is adjusted for current switch period to be arranged
Switching frequency processed.
Chaotic Signals Processing circuit includes data/address bus AltBus1, multiplier Product1, constant Constant2 chaos
Warble rate parameter Re, data selector Multiplexe3, constant Constant3 fixed cycle deviant N ', adder
Adder1, constant Constant4 period addend N, delay unit Delay1.In the chaotic Signals Processing circuit,
Output end, that is, chaos sequence of Multiplexe2 is connected with the input terminal of data/address bus AltBus1, data/address bus AltBus1's
Output end is connected with an input terminal of multiplier Product1, constant Constant2 chaotic frequency modulation degree parameter Re with
Another input terminal of Product1 is connected, the output end of Product1 and the zero-input terminal of data selector Multiplexe3
It is connected, constant Constant3 fixed cycle deviant N ' is connected with the one-input terminal of data selector Multiplexe3, input
Signal In2, that is, chaotic frequency modulation switching signal is connected with the data selection port of Multiplexe3, and Multiplexe3's is defeated
Outlet is connected with an input terminal of adder Adder1, and constant Constant4 period addend N and adder Adder1's is another
A input terminal is connected, and the output end of adder Adder1 is connected with the input terminal of delay unit Delay1, delay unit Delay1
Output end, that is, switch periods number NTIt is connected with digital pulse width modulation circuit；When input signal In2, that is, chaotic frequency modulation switch
When signal is high level, switch periods number NTFor fixed value N '+N, then switching frequency is fixed value f/ (N '+N), and wherein f is tired
The work clock for adding device Inc1, when input signal In2, that is, chaotic frequency modulation switching signal is low level, switch periods number NT
For chaos change value NcRe+N, then switching frequency is chaotic modulation value f/ (NcRe+N), each new switch periods, by Nc
Determine switching frequency, the size of Re determines warble rate, and Re is bigger, and switching frequency variation range is bigger.Its role is to lifes
At switch periods parameter NT, switching frequency is that wherein f is f/NT, the work clock of accumulator Inc1 can by input signal In2
To select between fixed switching frequency and chaotic modulation switching frequency, tune can be passed through when using chaotic modulation switching frequency
Warble rate is arranged in the size for saving Re.
PID duty cycle parameters counting circuit and digital pulse-width modulation circuit include PID duty cycle parameters counting circuit, compare
Device Comparator1 and Comparator2, accumulator Inc1, S-R trigger.The PID duty cycle parameters counting circuit and
In digital pulse width modulation circuit, the input terminal phase of input signal In1, that is, power supply feedback signal and PID duty cycle parameters counting circuit
Even, " b " input terminal phase of the output end, that is, duty cycle parameters D and comparator Comparator2 of PID duty cycle parameters counting circuit
Even, the output end of accumulator Inc1 and " b " of " a " input terminal of comparator Comparator2 and comparator Comparator1 are defeated
Enter end be connected, the output end of Comparator2 is connected with the reset terminal of accumulator Inc1, " a " input terminal of Comparator1 and
Switch periods number NTIt is connected, the output end of comparator Comparator2 is connected with " R " input terminal of S-R trigger, comparator
The output end of Comparator1 is connected with " S " input terminal of S-R trigger, output end Q, that is, switching pulse of S-R trigger with
The output signal Out of circuit is connected；When accumulator Inc1 is when being reset to 0 and starting counting that i.e. a new switch periods start,
Switching pulse export high level, once accumulator Inc1 be greater than duty cycle parameters D, switching pulse just lock export low level until
Accumulator Inc1 is greater than NT, a switch periods terminate, and then accumulator Inc1 is reset to 0, start a new switch periods.
Its role is to when accumulator Inc1 is when being reset to 0 and starting counting that i.e. a new switch periods start, switching pulse output
High level, once accumulator Inc1 is greater than duty cycle parameters D, switching pulse just locks output low level until accumulator Inc1 is big
In NT, a switch periods terminate, and then accumulator Inc1 is reset to 0, start a new switch periods, and power is opened in completion
The control of pass.
Claims (4)
1. a kind of chaotic frequency modulation digital switch power control circuit based on FPGA, it is characterised in that：Including PID duty ratio
Parameter calculation circuit, chaos sequence generation circuit, chaotic Signals Processing circuit, digital pulse width modulation circuit；The PID duty ratio
Parameter calculation circuit is electrically connected with digital pulse width modulation circuit；The chaos sequence generation circuit and chaotic Signals Processing
Circuit is electrically connected；The chaotic Signals Processing circuit is electrically connected with digital pulse width modulation circuit；The number
Pulse-width modulation circuit is electrically connected with circuit output signal.
2. the chaotic frequency modulation digital switch power control circuit based on FPGA according to claim 1, it is characterised in that：
In the chaos sequence generation circuit, the output end and data selector Multiplexe1 of the failing edge Single Pulse1 that is delayed
Data selection port be connected, " 0 " of the output end of data selector Multiplexe2 and data selector Multiplexe1
Input terminal is connected, and constant Constant1 chaotic maps initial value is connected with the one-input terminal of data selector Multiplexe1,
" 1 " of the output end of data selector Multiplexe1 and the input terminal of chaotic maps functional circuit and Multiplexe2 inputs
End is connected, and the output end of chaotic maps functional circuit is connected with the zero-input terminal of Multiplexe2, data selector
The data selection end of Multiplexe2 is connected with the output end of the Comparator1 of number comparator word pulse-width modulation circuit, data
The output end of selector Multiplexe2, that is, chaos sequence Nc is connected with chaotic Signals Processing circuit；Whenever Comparator1's
When output end is that the new switch periods of low level i.e. start, a new chaos number Nc is generated.
3. the chaotic frequency modulation digital switch power control circuit based on FPGA according to claim 1, it is characterised in that：
In the chaotic Signals Processing circuit, output end, that is, chaos sequence of Multiplexe2 and the input terminal of data/address bus AltBus1
It is connected, the output end of data/address bus AltBus1 is connected with an input terminal of multiplier Product1, and constant Constant2 is mixed
Ignorant warble rate parameter Re is connected with another input terminal of Product1, the output end and data selector of Product1
The zero-input terminal of Multiplexe3 is connected, constant Constant3 fixed cycle deviant N ' and data selector
The one-input terminal of Multiplexe3 is connected, input signal In2, that is, chaotic frequency modulation switching signal and Multiplexe3 number
It is connected according to selection port, the output end of Multiplexe3 is connected with an input terminal of adder Adder1, constant
Constant4 period addend N is connected with another input terminal of adder Adder1, the output end of adder Adder1 and delay
The input terminal of cells D elay1 is connected, output end, that is, switch periods number N of delay unit Delay1TWith digital pulse width modulation circuit
It is connected；When input signal In2, that is, chaotic frequency modulation switching signal is high level, switch periods number NTFor fixed value N '+N,
Then switching frequency is fixed value f/ (N '+N), and wherein f is the work clock of accumulator Inc1, when input signal In2, that is, chaos frequency
When rate modulation switch signal is low level, switch periods number NTFor chaos change value NcRe+N, then switching frequency is chaos tune
Value f/ (NcRe+N) processed, each new switch periods determine switching frequency by Nc, and the size of Re determines warble rate,
Re is bigger, and switching frequency variation range is bigger.
4. the chaotic frequency modulation digital switch power control circuit based on FPGA according to claim 1, it is characterised in that：
In the PID duty cycle parameters counting circuit and digital pulse-width modulation circuit, input signal In1, that is, power supply feedback signal with
The input terminal of PID duty cycle parameters counting circuit is connected, output end, that is, duty cycle parameters D of PID duty cycle parameters counting circuit
It is connected with " b " input terminal of comparator Comparator2, the output end of accumulator Inc1 and " a " of comparator Comparator2
Input terminal is connected with " b " input terminal of comparator Comparator1, the output end of Comparator2 and answering for accumulator Inc1
Position end is connected, " a " input terminal and switch periods number N of Comparator1TBe connected, the output end of comparator Comparator2 with
" R " input terminal of S-R trigger is connected, and the output end of comparator Comparator1 is connected with " S " input terminal of S-R trigger,
Output end Q, that is, switching pulse of S-R trigger is connected with the output signal Out of circuit；0 beginning is reset to as accumulator Inc1
When counting is that a new switch periods start, switching pulse exports high level, once accumulator Inc1 is greater than duty cycle parameters
D, switching pulse just lock output low level until accumulator Inc1 is greater than NT, a switch periods terminate, then accumulator
Inc1 is reset to 0, starts a new switch periods.
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| CN201811018393.3A CN108880204B (en) | 2018-09-03 | 2018-09-03 | Chaotic frequency modulation digital switching power supply control circuit based on FPGA |
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| CN201811018393.3A CN108880204B (en) | 2018-09-03 | 2018-09-03 | Chaotic frequency modulation digital switching power supply control circuit based on FPGA |
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| CN108880204B CN108880204B (en) | 2023-06-27 |
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Cited By (1)
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