CN108877634B - Synchronous controller, display device and control method thereof - Google Patents
Synchronous controller, display device and control method thereof Download PDFInfo
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- CN108877634B CN108877634B CN201810896212.0A CN201810896212A CN108877634B CN 108877634 B CN108877634 B CN 108877634B CN 201810896212 A CN201810896212 A CN 201810896212A CN 108877634 B CN108877634 B CN 108877634B
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The embodiment of the invention provides a synchronous controller, a display device and a control method thereof, relates to the technical field of display, and can realize that two existing driving chips are used for synchronously transmitting data signals for each data line, a new driving chip is not required to be manufactured, the cost is reduced, and poor display caused by the fact that the two driving chips cannot synchronously transmit the data signals is improved. The synchronous controller includes: the data signal splitting module is used for splitting the whole original data signal into a first area original data signal and a second area original data signal; the time sequence control signal splitting module is used for splitting the whole original time sequence control signal into a first area original time sequence control signal and a second area original time sequence control signal; and the control module is used for controlling the synchronous output of the data signal splitting module and the time sequence control signal splitting module.
Description
Technical Field
The invention relates to the technical field of display, in particular to a synchronous controller, a display device and a control method thereof.
Background
With the development of display technologies, the size of a display panel is getting larger, and for a large-sized display panel, in the prior art, the same driving chip is usually used to drive sub-pixels in the whole display area, the driving chip is connected to data lines through leads, and then data signals generated by the driving chip are transmitted to the sub-pixels in the display area through the data lines for charging, so as to realize a display function.
In order to solve the problem of uneven display brightness in a large-size display panel, a technology of respectively driving different display areas by using two driving chips is provided, however, the two driving chips are needed to be used, the existing driving chips are designed for the same display area, and if the existing driving chips are still used, the two driving chips cannot be guaranteed to synchronously transmit data signals to corresponding data lines, so that poor display is caused; if a new driver chip is made for the synchronization problem, the cost of the display device will be high.
Disclosure of Invention
Embodiments of the present invention provide a synchronous controller, a display device, and a control method thereof, which can implement synchronous data signal transmission for each data line by using two existing driving chips, without manufacturing a new driving chip, reduce cost, and improve poor display caused by the fact that the two driving chips cannot synchronously transmit data signals.
In one aspect, an embodiment of the present invention provides a synchronous controller, including:
a first signal output terminal and a second signal output terminal;
the data signal splitting module is used for splitting the whole original data signal into a first area original data signal and a second area original data signal, outputting the first area original data signal to the first signal output end, and outputting the second area original data signal to the second signal output end;
the time sequence control signal splitting module is used for splitting the whole original time sequence control signal into a first area original time sequence control signal and a second area original time sequence control signal, outputting the first area original time sequence control signal to the first signal output end, and outputting the second area original time sequence control signal to the second signal output end;
the control module is electrically connected to the data signal splitting module and the timing control signal splitting module, and is configured to control the data signal splitting module to synchronously output the first area original data signal and the second area original data signal, and further control the timing control signal splitting module to synchronously output the first area original timing control signal and the second area original timing control signal.
In another aspect, an embodiment of the present invention provides a display device, including:
the above-mentioned synchronous controller;
the display panel comprises a first display area and a second display area, wherein the first display area comprises a plurality of first pixel driving circuits and a plurality of first data lines electrically connected with the first pixel driving circuits, and the second display area comprises a plurality of second pixel driving circuits and a plurality of second data lines electrically connected with the second pixel driving circuits;
the display panel further comprises a first scanning driving circuit and a second scanning driving circuit, wherein the first scanning driving circuit is electrically connected with the plurality of first pixel driving circuits, and the second scanning driving circuit is electrically connected with the plurality of second pixel driving circuits;
the first driving chip is electrically connected with the first scanning driving circuit and the plurality of first data lines;
the second driving chip is electrically connected with the second scanning driving circuit and the plurality of second data lines;
the first signal output end of the synchronous controller is electrically connected to the first driving chip, and the second signal output end of the synchronous controller is electrically connected to the second driving chip.
On the other hand, an embodiment of the present invention further provides a control method for a display device, which is used for the display device described above, and the method includes:
the data signal splitting module acquires an integral original signal and splits the integral original signal into a first area original data signal and a second area original data signal;
the time sequence control signal splitting module acquires an integral original time sequence control signal and splits the integral original time sequence control signal into a first area original time sequence control signal and a second area original time sequence control signal;
the data signal splitting module transmits the first area original data signal to the first driving chip through the first signal output end, and transmits the second area original data signal to the second driving chip through the second signal output end;
the time sequence control signal splitting module transmits the first area original time sequence control signal to the first driving chip through the first signal output end, and transmits the second area original time sequence control signal to the second driving chip through the second signal output end;
the first driving chip generates a first area actual data signal according to the first area original data signal and transmits the first area actual data signal to the plurality of first data lines, and generates a first area actual time sequence control signal according to the first original time sequence control signal and transmits the first area actual time sequence control signal to the first scanning driving circuit;
and the second driving chip generates a second area actual data signal according to the second area original data signal and transmits the second area actual data signal to the plurality of second data lines, and generates a second area actual time sequence control signal according to the second original time sequence control signal and transmits the second area actual time sequence control signal to the second scanning driving circuit.
In the embodiment of the invention, the synchronous controller is used for connecting two driving chips, the splitting of the original signal is realized according to different display areas through the data signal splitting module and the time sequence control signal splitting module, and the split original signal is synchronously output to the two driving chips corresponding to different display areas through the control module, so that the data signals can be synchronously transmitted to each data line by using the existing driving chips without manufacturing new driving chips, the cost is reduced, and the poor display caused by the fact that the two driving chips cannot synchronously transmit the signals is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a block diagram of a synchronous controller according to an embodiment of the present invention;
FIG. 2 is a block diagram of another embodiment of a synchronization controller;
FIG. 3 is a block diagram of another embodiment of a synchronous controller;
FIG. 4 is a schematic structural diagram of a display device according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a method for controlling a display device according to an embodiment of the present invention;
fig. 6 is a flowchart illustrating another control method for a display device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
As shown in fig. 1, fig. 1 is a block diagram of a synchronous controller according to an embodiment of the present invention, and an embodiment of the present invention provides a synchronous controller 1, including: a first signal output terminal out1 and a second signal output terminal out 2; the data signal splitting module 11 is electrically connected to the first signal output terminal out1 and the second signal output terminal out2, and the data signal splitting module 11 is configured to split the entire original data signal into a first area original data signal and a second area original data signal, output the first area original data signal to the first signal output terminal out1, and output the second area original data signal to the second signal output terminal out 2; the timing control signal splitting module 12 is electrically connected to the first signal output end out1 and the second signal output end out2, and the timing control signal splitting module 12 is configured to split the entire original timing control signal into a first area original timing control signal and a second area original timing control signal, output the first area original timing control signal to the first signal output end out1, and output the second area original timing control signal to the second signal output end out 2; the control module 13 is electrically connected to the data signal splitting module 11 and the timing control signal splitting module 12, the control module 13 is configured to control the data signal splitting module 11 to synchronously output a first area original data signal and a second area original data signal, and the control module 13 is further configured to control the timing control signal splitting module 12 to synchronously output a first area original timing control signal and a second area original timing control signal.
Specifically, the existing driving chip is configured to receive an original timing control signal and an original data signal, generate an actual timing control signal according to the original timing control signal, and transmit the actual timing control signal to the scanning driving circuit, the scanning driving circuit is configured to output a scanning signal to a scanning line in the display area, the driving chip is further configured to generate an actual data signal according to the original data control signal, and transmit the actual data signal to the data line, and the scanning line controls the sub-pixels in the corresponding row in the display area to be charged according to the actual data signal on the data line under the control of the scanning signal. Therefore, when two driving chips are used to drive two display areas in the same display panel, the synchronous controller in the embodiment of the present invention is configured to provide the required original timing control signal and original data signal for the two driving chips, wherein the first signal output terminal out1 and the second signal output terminal out2 of the synchronous controller 1 are electrically connected to the two driving chips respectively, the synchronous controller 1 obtains an overall original signal from the motherboard, the overall original signal includes an overall original data signal and an overall original timing control signal, wherein the data signal splitting module 11 and the timing control signal splitting module 12 are configured to split the overall original signal into signals corresponding to the two display areas and output the signals to the two driving chips respectively through the first signal output terminal out1 and the second signal output terminal out2, and the control module 13 is configured to control the split signals to be synchronously sent to the two driving chips, therefore, the two driving chips can synchronously output the corresponding data signals and the corresponding time sequence control signals to two different display areas.
According to the synchronous controller provided by the embodiment of the invention, the splitting of the original signal is realized according to different display areas through the data signal splitting module and the time sequence control signal splitting module, and the split original signal is synchronously output to the two driving chips corresponding to different display areas through the control module, so that the data signals can be synchronously transmitted to each data line by using the existing driving chips, a new driving chip is not required to be manufactured, the cost is reduced, and the poor display caused by the fact that the two driving chips cannot synchronously transmit the signals is improved.
Optionally, as shown in fig. 2, fig. 2 is a block diagram of another synchronous controller in an embodiment of the present invention, where the synchronous controller 1 further includes: the first conversion module 141 is electrically connected to the data signal splitting module 11 and the timing control signal splitting module 12, the first conversion module 141 is configured to convert the first high-speed differential signal into a first logic signal and output the first logic signal to the data signal splitting module 11 and the timing control signal splitting module 12, where the first logic signal includes an integral original data signal and an integral original timing control signal; the second conversion module 142 is electrically connected to the data signal splitting module 11 and the timing control signal splitting module 12, and the second conversion module 142 is configured to convert a second logic signal into a second high-speed differential signal and convert a third logic signal into a third high-speed differential signal, where the second logic signal includes a first area original data signal and a first area original timing control signal, and the third logic signal includes a second area original data signal and a second area original timing control signal.
Specifically, the data signal splitting module 11 is electrically connected to the first signal output end out1 and the second signal output end out2 through the second conversion module 142, and the timing control signal splitting module 12 is electrically connected to the first signal output end out1 and the second signal output end out2 through the second conversion module 142, where signals obtained by the driver chip in the prior art are usually high-speed differential signals, and it is necessary to decode and process the high-speed differential signals, so the first conversion module 141 in the synchronous controller in the embodiment of the present invention is used to decode and convert the high-speed differential signals that cannot be directly processed into logic signals, and then the splitting of the original data signals and the splitting of the original timing control signals are respectively realized in the data signal splitting module 11 and the timing control signal splitting module 12, and the split original data signals and the original timing control signals are logic signals, in order to enable the conventional driving chip to directly use the signal output by the synchronous controller 1, the split original data signal and the original timing control signal are converted into a high-speed differential signal by the second conversion module 142, and then the high-speed differential signal is output to the driving chip through the first signal output end out1 and the second signal output end out 2.
Optionally, as shown in fig. 3, fig. 3 is a block diagram of another synchronous controller in an embodiment of the present invention, where the synchronous controller further includes: a power input terminal d0, a first power output terminal d1, and a second power output terminal d 2; the power conversion module 14 is electrically connected to the power input terminal d0, the first power output terminal d1 and the second power output terminal d2, and the power conversion module 14 is configured to convert an initial power signal of the power input terminal d0 into a first power signal and a second power signal, output the first power signal to the first power output terminal d1, and output the second power signal to the second power output terminal d 2.
Specifically, in the prior art, only a power supply signal required by one driver chip is externally provided, and in the embodiment of the present invention, since two driver chips are used, a power supply conversion module may be disposed in the synchronous controller to convert the externally provided power supply signal into power supply signals required by the two driver chips, and output the power supply signals to the two driver chips through the first power output terminal d1 and the second power output terminal d2, respectively.
Optionally, the data signal splitting module 11 and the timing control signal splitting module 12 are implemented by a field-programmable gate array, and the control module 13 may be implemented by a single chip microcomputer.
As shown in fig. 4, fig. 4 is a schematic structural diagram of a display device in an embodiment of the present invention, and an embodiment of the present invention further provides a display device, including: the above-described synchronous controller 1; a display panel 2 including a first display region 21 and a second display region 22, the first display region 21 including a plurality of first pixel driving circuits (not shown) and a plurality of first data lines data1 electrically connected to the plurality of first pixel driving circuits, the second display region 22 including a plurality of second pixel driving circuits (not shown) and a plurality of second data lines data2 electrically connected to the plurality of second pixel driving circuits; the display panel 2 further includes a first scan driving circuit 31 and a second scan driving circuit 32, the first scan driving circuit 31 being electrically connected to the plurality of first pixel driving circuits, the second scan driving circuit 32 being electrically connected to the plurality of second pixel driving circuits; a first driver chip IC1 electrically connected to the first scan driver circuit 31 and the plurality of first data lines data 1; a second driving chip IC2 electrically connected to the second scan driving circuit 32 and the plurality of second data lines 22; the first signal output terminal out1 of the synchronous controller 1 is electrically connected to the first driver IC1, and the second signal output terminal out2 of the synchronous controller 1 is electrically connected to the second driver IC 2.
Specifically, the first data line data1 and the second data line data2 are used for transmitting data signals, the first scan driving circuit 31 and the second scan driving circuit 32 are used for providing scan signals for scan lines, the scan lines are used for controlling the pixel driving circuits to cooperate with the data lines to realize charging of the sub-pixels, and in another embodiment of the present invention, the display area of the display panel 2 is divided into a first display area 21 and a second display area 22, wherein the first driving chip IC1 is used for controlling the first display area 21, and the second driving chip IC2 is used for controlling the second display area, so that the first driving chip IC1 can be disposed below the first display area 21, the second driving chip IC2 can be disposed below the second display area 22, so that the first driving chip IC1 is electrically connected to the first data line data1 corresponding to the first display area 21, and the second driving chip IC2 is electrically connected to the second data line data2 corresponding to the second display area 22, compared with the prior art that the same driving chip is used for connecting all the data lines, the length difference of the lead wires between the driving chip and different data lines is reduced. The specific structure and principle of the synchronous controller 1 are the same as those of the above-described embodiments, and are not described herein again. The first driver chip IC1 acquires a first area original timing control signal and a first area original data signal output from the synchronization controller 1 and implements control of the first display area 21 based on these two signals, and the second driver chip IC2 acquires a second area original timing control signal and a second area original data signal output from the synchronization controller 1 and implements control of the second display area 22 based on these two signals. Wherein the first driver chip IC1 controls the first scan driver circuit 31 based on the first area original timing control signal, controls the data signal transmitted on the first data line data1 based on the first area original data signal, and the second driver chip IC2 controls the second scan driver circuit 32 based on the second area original timing control signal, and controls the data signal transmitted on the second data line data2 based on the second area original data signal. Because the signal output to the first driver IC1 and the signal output to the second driver IC2 in the synchronous controller 1 are synchronously transmitted under the control of the control module 13, the display device in the embodiment of the invention can realize synchronous transmission of data signals to corresponding data lines through two driver chips, does not need to manufacture new driver chips, reduces the cost, and improves poor display caused by the fact that the two driver chips cannot synchronously transmit the data signals.
According to the display device provided by the embodiment of the invention, the synchronous controller is connected with the two driving chips, the splitting of the original signal is realized according to different display areas through the data signal splitting module and the time sequence control signal splitting module, and the split original signal is synchronously output to the two driving chips corresponding to different display areas through the control module, so that the data signal can be synchronously transmitted to each data line by using the conventional driving chips, a new driving chip is not required to be manufactured, the cost is reduced, and the poor display caused by the fact that the two driving chips cannot synchronously transmit the signal is improved.
Optionally, the display panel 2 includes a bending region 3, and the first display region 21 and the second display region 22 are respectively located at two sides of the bending region 3.
Specifically, for the bendable display panel 2, the display panel 2 can be repeatedly bent in the bending region 3, and therefore, when the two driving chips are used to control the first display region 21 and the second display region 22 respectively located at two sides of the bending region 3, the first driving chip IC1 can be disposed at one side of the bending region 3 close to the first display region 21, and the second driving chip IC2 can be disposed at one side of the bending region 3 close to the second display region 22, so that the driving chips can be prevented from being disposed in the bending region 3, and the driving chips can be prevented from being damaged by bending; on the other hand, the connecting lead between the first driver IC1 and the first data line data1 can be prevented from crossing the bending region 3, and the connecting lead between the second driver IC2 and the second data line data2 can be prevented from crossing the bending region 3, thereby preventing the connecting lead from being broken due to bending.
Alternatively, the first scan driving circuit 31 is located at a side of the first display region 21 away from the bending region 3, and the second scan driving circuit 32 is located at a side of the second display region 22 away from the bending region 3.
Specifically, in this way, the first scan driving circuit 31 and the second scan driving circuit 32 can be prevented from being located in the bending region 3, and the bending can be prevented from damaging the scan driving circuits. In addition, since two scan driving circuits are provided and the scan driving circuits output scan signals to the scan lines, display defects due to voltage drops on the scan lines can be improved as compared with a case where only one scan driving circuit is provided.
Optionally, the display device further includes: the flexible circuit board 4, the first signal output terminal out1 of the synchronous controller 1 are electrically connected to the first driver IC1 through the flexible circuit board 4, and the second signal output terminal out2 of the synchronous controller 1 is electrically connected to the second driver IC2 through the flexible circuit board 4. The flexible circuit board 4 is used for realizing the electric connection between the synchronous controller 1 and the two driving chips, and even if the flexible circuit board 4 spans the bending area 3, the wire breakage caused by bending is not easy to occur.
As shown in fig. 1 to 5, fig. 5 is a schematic flowchart of a control method of a display device in an embodiment of the present invention, and the embodiment of the present invention further provides a control method of a display device, which is used for the display device, and the method includes:
it should be noted that there is no time sequence restriction between step 101 and step 201, and both steps are performed simultaneously.
102, the data signal splitting module 11 transmits the first area original data signal to the first driver chip IC1 through the first signal output end out1, and transmits the second area original data signal to the second driver chip IC2 through the second signal output end out 2;
it should be noted that there is no time sequence restriction between step 102 and step 202, the two steps are performed simultaneously, and under the action of the control module 13, the first area original data signal and the second area original data signal are synchronously output to the first driver chip IC1 and the second driver chip IC2, and the first area original timing control signal and the second area original timing control signal are synchronously output to the first driver chip IC1 and the second driver chip IC 2.
in step 303, the second driver IC2 generates a second region actual data signal according to the second region original data signal and transmits the second region actual data signal to the plurality of second data lines data2, and generates a second region actual timing control signal according to the second original timing control signal and transmits the second region actual timing control signal to the second scan driver circuit 32.
It should be noted that there is no time sequence restriction between step 302 and step 302, the two steps are performed simultaneously, and since the first area original data signal and the second area original data signal are synchronously output to the first driver chip IC1 and the second driver chip IC2, the first area original timing control signal and the second area original timing control signal are synchronously output to the first driver chip IC1 and the second driver chip IC2, the first driver chip IC1 and the second driver chip IC2 synchronously output the first area actual data signal and the second area actual data signal to the first data line 1 and the second data line data2, and the first driver chip IC1 and the second driver chip IC2 synchronously output the first area actual timing control signal and the second area actual timing control signal to the first scan driver circuit 31 and the second scan driver circuit 32.
Specifically, the specific structures and principles of the synchronous controller, the first driving chip, the second driving chip and the display panel are the same as those of the above embodiments, and are not described herein again.
According to the control method of the display device provided by the embodiment of the invention, the synchronous controller is connected with the two driving chips, the splitting of the original signal is realized according to different display areas through the data signal splitting module and the time sequence control signal splitting module, and the split original signal is synchronously output to the two driving chips corresponding to different display areas through the control module, so that the data signal can be synchronously transmitted to each data line by using the existing driving chips without manufacturing new driving chips, the cost is reduced, and the poor display caused by the fact that the two driving chips cannot synchronously transmit the signal is improved.
Optionally, the synchronization controller comprises: the first conversion module 141 is electrically connected to the data signal splitting module 11 and the timing control signal splitting module 12; the second conversion module 142 is electrically connected to the data signal splitting module 11 and the timing control signal splitting module 12;
as shown in fig. 3, 4 and 6, fig. 6 is a schematic flowchart of another control method for a display device according to an embodiment of the present invention, where the method further includes:
before the process of acquiring the whole original signal by the data signal splitting module 11 and the whole original timing control signal by the timing control signal splitting module 12, i.e. before the above steps 101 and 201;
in the step 101, the step of acquiring the whole original signal by the data signal splitting module 11 specifically includes: acquiring an integral original signal in the first logic signal;
in step 201, the step of acquiring the whole original timing control signal by the timing control signal splitting module 12 is specifically: acquiring an integral original signal in the first logic signal;
the process of the step 102, the data signal splitting module 11 transmitting the first area original data signal to the first driver chip IC1 through the first signal output terminal out1, and transmitting the second area original data signal to the second driver chip IC2 through the second signal output terminal out2, and the process of the step 201, the timing control signal splitting module 12 transmitting the first area original timing control signal to the first driver chip IC1 through the first signal output terminal out1, and transmitting the second area original timing control signal to the second driver chip IC2 through the second signal output terminal out2 includes:
step 1021, the data signal splitting module 11 transmits the first area original data signal and the second area original data signal to the second conversion module 142, and step 2021, the timing control signal splitting module 12 transmits the first area timing control signal and the second area timing control signal to the second conversion module 142;
Alternatively, the first-area actual timing control signal includes an initial signal and a timing signal for the first scan driving circuit 31; the second area actual timing control signal includes an initial signal and a timing signal for the second scan driving circuit 32.
Specifically, the first scan driving circuit 31 and the second scan driving circuit 32 each include cascaded multiple shift registers, each shift register generates an output signal according to an input signal and a timing signal, the input signal of each shift register is from a previous shift register except the first shift register, and the input signal of the first shift register is defined as an initial signal of the scan driving circuit, so that the scan driving circuit needs the timing signal and the initial signal and is provided by the driving chip.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A synchronous controller, comprising:
a first signal output terminal and a second signal output terminal;
the data signal splitting module is used for splitting the whole original data signal into a first area original data signal and a second area original data signal, outputting the first area original data signal to the first signal output end, and outputting the second area original data signal to the second signal output end;
the time sequence control signal splitting module is used for splitting the whole original time sequence control signal into a first area original time sequence control signal and a second area original time sequence control signal, outputting the first area original time sequence control signal to the first signal output end, and outputting the second area original time sequence control signal to the second signal output end;
the control module is electrically connected to the data signal splitting module and the timing control signal splitting module, and is configured to control the data signal splitting module to synchronously output the first area original data signal and the second area original data signal, and further control the timing control signal splitting module to synchronously output the first area original timing control signal and the second area original timing control signal;
the synchronization controller further includes:
the first conversion module is electrically connected to the data signal splitting module and the timing control signal splitting module, and is configured to convert a first high-speed differential signal into a first logic signal and output the first logic signal to the data signal splitting module and the timing control signal splitting module, where the first logic signal includes the entire original data signal and the entire original timing control signal;
the second conversion module is electrically connected to the data signal splitting module and the timing control signal splitting module, and is configured to convert a second logic signal into a second high-speed differential signal and convert a third logic signal into a third high-speed differential signal, where the second logic signal includes the first area original data signal and the first area original timing control signal, and the third logic signal includes the second area original data signal and the second area original timing control signal.
2. The synchronous controller according to claim 1, further comprising:
a power input terminal, a first power output terminal and a second power output terminal;
the power conversion module is electrically connected to the power input end, the first power output end and the second power output end, and is used for converting an initial power signal of the power input end into a first power signal and a second power signal, outputting the first power signal to the first power output end, and outputting the second power signal to the second power output end.
3. The synchronous controller according to claim 1 or 2,
the data signal splitting module and the time sequence control signal splitting module are realized by a field editable gate array.
4. A display device, comprising:
a synchronous controller according to any one of claims 1 to 3;
the display panel comprises a first display area and a second display area, wherein the first display area comprises a plurality of first pixel driving circuits and a plurality of first data lines electrically connected with the first pixel driving circuits, and the second display area comprises a plurality of second pixel driving circuits and a plurality of second data lines electrically connected with the second pixel driving circuits;
the display panel further comprises a first scanning driving circuit and a second scanning driving circuit, wherein the first scanning driving circuit is electrically connected with the plurality of first pixel driving circuits, and the second scanning driving circuit is electrically connected with the plurality of second pixel driving circuits;
the first driving chip is electrically connected with the first scanning driving circuit and the plurality of first data lines;
the second driving chip is electrically connected with the second scanning driving circuit and the plurality of second data lines;
the first signal output end of the synchronous controller is electrically connected to the first driving chip, and the second signal output end of the synchronous controller is electrically connected to the second driving chip.
5. The display device according to claim 4,
the display panel comprises a bending area, and the first display area and the second display area are respectively positioned on two sides of the bending area.
6. The display device according to claim 5,
the first scanning driving circuit is located on one side, far away from the bending area, of the first display area, and the second scanning driving circuit is located on one side, far away from the bending area, of the second display area.
7. The display device according to claim 4, comprising:
and a first signal output end of the synchronous controller is electrically connected to the first driving chip through the flexible circuit board, and a second signal output end of the synchronous controller is electrically connected to the second driving chip through the flexible circuit board.
8. A control method for a display device according to any one of claims 4 to 7, the method comprising:
the data signal splitting module acquires an integral original data signal and splits the integral original data signal into a first area original data signal and a second area original data signal;
the time sequence control signal splitting module acquires an integral original time sequence control signal and splits the integral original time sequence control signal into a first area original time sequence control signal and a second area original time sequence control signal;
the data signal splitting module transmits the first area original data signal to the first driving chip through the first signal output end, and transmits the second area original data signal to the second driving chip through the second signal output end;
the time sequence control signal splitting module transmits the first area original time sequence control signal to the first driving chip through the first signal output end, and transmits the second area original time sequence control signal to the second driving chip through the second signal output end;
the first driving chip generates a first area actual data signal according to the first area original data signal and transmits the first area actual data signal to the plurality of first data lines, and generates a first area actual time sequence control signal according to the first area original time sequence control signal and transmits the first area actual time sequence control signal to the first scanning driving circuit;
the second driving chip generates second area actual data signals according to the second area original data signals and transmits the second area actual data signals to the plurality of second data lines, and generates second area actual time sequence control signals according to the second area original time sequence control signals and transmits the second area actual time sequence control signals to the second scanning driving circuit;
the synchronization controller includes:
the first conversion module is electrically connected with the data signal splitting module and the time sequence control signal splitting module;
the second conversion module is electrically connected with the data signal splitting module and the time sequence control signal splitting module;
the method further comprises the following steps:
before the data signal splitting module acquires an integral original data signal and the time sequence control signal splitting module acquires an integral original time sequence control signal;
the first conversion module acquires a first high-speed differential signal, converts the first high-speed differential signal into a first logic signal, and outputs the first logic signal to the data signal splitting module and the timing control signal splitting module, wherein the first logic signal comprises the integral original data signal and the integral original timing control signal;
the data signal splitting module is specifically configured to obtain an overall original data signal:
acquiring the integral original data signal in the first logic signal;
the time sequence control signal splitting module is used for acquiring the whole original time sequence control signal and specifically comprises the following steps:
acquiring the integral original time sequence control signal in the first logic signal;
the data signal splitting module transmits the first area original data signal to the first driving chip through the first signal output end, transmits the second area original data signal to the second driving chip through the second signal output end, and the time sequence control signal splitting module transmits the first area original time sequence control signal to the first driving chip through the first signal output end, and the process of transmitting the second area original time sequence control signal to the second driving chip through the second signal output end includes:
the data signal splitting module transmits the first area original data signal and the second area original data signal to the second conversion module, and the timing control signal splitting module transmits the first area original timing control signal and the second area original timing control signal to the second conversion module;
the second conversion module converts a second logic signal into a second high-speed differential signal and converts a third logic signal into a third high-speed differential signal, the second high-speed differential signal is transmitted to the first driving chip through the first signal output end, the third high-speed differential signal is transmitted to the second driving chip through the second signal output end, the second logic signal comprises a first area original data signal and a first area original time sequence control signal, and the third logic signal comprises a second area original data signal and a second area original time sequence control signal.
9. The method of claim 8,
the first area actual timing control signal includes an initial signal and a timing signal for the first scan driving circuit;
the second area actual timing control signal includes an initial signal and a timing signal for the second scan driving circuit.
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| CN111768732B (en) * | 2019-04-01 | 2022-04-15 | 北京京东方光电科技有限公司 | Display driving device, display device and display driving method |
| CN111048030A (en) * | 2020-01-02 | 2020-04-21 | 昆山国显光电有限公司 | Drive chip and display device |
| CN112882400B (en) * | 2021-01-12 | 2022-10-25 | 杭州芯格微电子有限公司 | Driving multiple I's simultaneously 2 Method for C slave device and chip driven by controller simultaneously |
| US11955070B2 (en) * | 2021-05-12 | 2024-04-09 | Novatek Microelectronics Corp. | Emission control method for driver circuit of display panel |
| CN114822401B (en) * | 2022-06-30 | 2022-09-27 | 惠科股份有限公司 | Display device, source electrode chip on film and driving method |
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