CN108830003A - The inspection method of integrated circuit diagram - Google Patents
The inspection method of integrated circuit diagram Download PDFInfo
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- CN108830003A CN108830003A CN201810672248.0A CN201810672248A CN108830003A CN 108830003 A CN108830003 A CN 108830003A CN 201810672248 A CN201810672248 A CN 201810672248A CN 108830003 A CN108830003 A CN 108830003A
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- 238000007689 inspection Methods 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000010586 diagram Methods 0.000 title claims abstract description 33
- 239000002184 metal Substances 0.000 claims description 209
- 229910052751 metal Inorganic materials 0.000 claims description 209
- 239000000284 extract Substances 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 3
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000010009 beating Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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Abstract
The present invention provides a kind of inspection methods of integrated circuit diagram, including：Via densities are set and check file；Obtain regional ensemble to be measured；Calculate the via densities in the region to be measured；And the via densities in the region to be measured are checked；If the via densities in the region to be measured are more than or equal to the predetermined value, pass through, if the via densities in the region to be measured are less than the predetermined value, the region to be measured is marked.The inspection of via densities is converted a kind of special layout design rules inspection by method provided by the present invention, the automation inspection to via densities is realized by design rule check file, through-hole no marking or the accurate positionin beaten less can be achieved, check that covering surface is complete, indicative label quickly and efficiently can be carried out to the region for not meeting design rule, convenient for layout design, personnel are modified domain, improve and check efficiency save the cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of inspection method of integrated circuit diagram.
Background technique
In the last part technology of semiconductor devices manufacture, it can grow on a semiconductor substrate by metal interconnecting wires and insulating layer
Then the multiple layer metal interconnection layer of composition manufactures through-hole in insulating layer, deposited metal realizes different layers metal connecting line in through-hole
Between connection.The number of number of through-holes between the metal connecting line of different layers will affect circuit performance, and number is very few to be made
It is excessive to obtain resistance drop, therefore generally wishes that join domain there can be enough through-holes in layout design.
There are two ways to checking join domain via densities at present, one is manual inspection, this method heavy workload,
And the integrality checked is limited.Another is to calculate IR drop (pressure drop) by automation tools to push away if pressure drop is excessive
It surveys via densities and not enough returns again to modification domain.This method the disadvantage is that the insufficient region of via densities can not be accurately positioned,
And software cost is higher.Therefore, in layout design flow, a kind of inspection of efficiently complete circuit layout via densities is needed
Checking method.
Summary of the invention
The purpose of the present invention is to provide a kind of inspection methods of integrated circuit diagram, to solve existing inspection method work
Amount is big and checks not comprehensive enough problem.
Another object of the present invention is to provide a kind of inspection methods of integrated circuit diagram, to solve existing inspection method
The insufficient region of via densities can not be carried out being accurately positioned and use the higher problem of software cost.
In order to achieve the above object, the present invention provides a kind of inspection method of integrated circuit diagram, the domain includes
One or more metal interference networks it is characterized by comprising the following steps：
Via densities are set and check file, including being arranged described in the text title and setting of each metal interference networks
The predetermined value of via densities；
It loads the domain and the via densities checks file；
Obtain regional ensemble to be measured；
Calculate the via densities in the region to be measured；And
The via densities in the region to be measured are checked；If the via densities in the region to be measured are more than or equal to described
Predetermined value then passes through, if the via densities in the region to be measured are less than the predetermined value, marks to the region to be measured
Note.
Optionally, the same metal interference networks include all metal connecting lines with connection relationship.
Optionally, the connection relationship is to realize adjacent two layers metal connecting line in same metal interference networks by through-hole
Connection.
Optionally, the text title is set on one or more layers described metal connecting line of same metal interference networks.
Optionally, the step of acquisition regional ensemble to be measured includes：Obtain the metal connecting line of metal interference networks to be measured.
Optionally, it according to the text title of the metal interference networks to be measured, is identified on the domain to be detected
Metal interference networks；According to connection relationship, all metal connecting lines of metal interference networks to be measured are extracted.
Optionally, the metal connecting line in the metal interference networks is abstracted into a series of metal connecting line figures, adjacent two
The join domain of layer metal connecting line is the overlapping region of respective metal line figure on domain.
Optionally, the regional ensemble to be measured is the set of the overlapping region.
Optionally, it according to the positional relationship of metal connecting line figure in metal interference networks to be measured described on the domain, mentions
Take the overlapping region of neighbouring double layer of metal line figure.
Optionally, the via densities of the overlapping region be the overlapping region in all through-hole gross areas with it is described heavy
The area ratio in folded region.
Optionally, the inspection checks to include that inspection to the overlapping region through-hole no marking and the overlapping region through-hole are few
The inspection beaten.
Optionally, if the via densities of the overlapping region are less than the predetermined value, the overlapping region leads to
Hole no marking or the overlapping region through-hole are beaten less, and the overlapping region is marked.
In conclusion in the inspection method of integrated circuit diagram provided by the invention, including：Via densities inspection is set
File, including the text title of each metal interference networks is arranged and the predetermined value of the via densities is arranged；Load institute
It states domain and the via densities checks file；Obtain regional ensemble to be measured；Calculate the via densities in the region to be measured；And
The via densities in the region to be measured are checked；If the via densities in the region to be measured are more than or equal to the predetermined value,
Then pass through, if the via densities in the region to be measured are less than the predetermined value, the region to be measured is marked.The present invention
The inspection of via densities is converted a kind of special layout design rules inspection by institute's providing method, passes through design rule check text
Part realizes to the automation inspections of via densities, it can be achieved that through-hole no marking or the less accurate positionin beaten, check that covering surface is complete, can
Indicative label quickly and efficiently is carried out to the region for not meeting design rule, domain is carried out more convenient for layout design personnel
Change, improves and check efficiency save the cost.
Detailed description of the invention
Fig. 1 is the flow diagram of the inspection method of integrated circuit diagram provided in an embodiment of the present invention；
Fig. 2 is the cross-sectional view of different metal interference networks connection；
Fig. 3 is the top view of different metal interference networks connection；
Fig. 4 is the connection schematic diagram of the metal wire of two metal interference networks；
Fig. 5 is the schematic diagram that the identification of metal interconnection area is extracted；
Fig. 6 is the schematic diagram that via densities provided in an embodiment of the present invention calculate；
Fig. 7 is the signal of adjacent metal overlapping region provided in an embodiment of the present invention and overlapping region via densities
Figure；
Wherein, 11- metal connecting line Mi-1, 12- metal connecting line Mi, 121- metal wire a_Mi, 122- metal wire b_Mi, 123- gold
Belong to line c_Mi, 13- metal connecting line Mi+1, 14- metal wire a_MiWith metal connecting line Mi+1Overlapping region, 15- metal wire a_MiAnd metal
Line Mi-1Overlapping region, 16- metal wire b_Mi and metal connecting line Mi+1Overlapping region, 17- metal wire b_MiWith metal connecting line Mi-1
Overlapping region, 18- metal wire c_MiWith metal connecting line Mi+1Overlapping region, 19- metal wire c_MiWith metal connecting line Mi-1Overlay region
Domain, 2- metal interference networks VDD_a, 21- metal connecting line a_Mi-1, 22- metal connecting line a_Mi, 23- metal connecting line a_Mi+1, 24-
Metal connecting line a_Mi-1With metal connecting line a_MiOverlapping region, 25- metal connecting line a_MiWith metal connecting line a_Mi+1Overlapping region, 3-
Metal interference networks VDD_b, 31- metal connecting line b_Mi-1, 32- metal connecting line b_Mi, 33- metal connecting line b_Mi+1, 34- metal company
Line b_Mi-1With metal connecting line b_MiOverlapping region, 35- metal connecting line b_MiWith metal connecting line b_Mi+1Overlapping region, 41- metal wire
Mi, 42- metal wire Mi+1, the overlapping region 43-, the overlapping region 44-, the overlapping region 451-1, the overlapping region 452-2,453-3
Number overlapping region, the overlapping region 454-4, the overlapping region 455-5, the overlapping region 456-6, the overlapping region 457-7,
The overlapping region 458-8, the overlapping region 459-9.
Specific embodiment
A specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following description,
Advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate
Ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
As described in the background art, in IC Layout, it is desirable to which metal contact zone domain can have enough
Through-hole, and at present for the inspection method of metal contact zone domain via densities include manual inspection method and using automate
The method that tool calculates pressure drop, the former heavy workload, and the integrality checked is limited, the latter can not be to the insufficient area of via densities
Domain is accurately positioned, and software cost is higher.
Therefore, in IC Layout process, to solve the above-mentioned problems, the present invention provides the integrated electricity of one kind
The inspection method of road domain.
Refering to fig. 1, it is the flow diagram of the inspection method of integrated circuit diagram provided in an embodiment of the present invention, such as schemes
Shown in 1, the inspection method of the integrated circuit diagram includes the following steps；
Step S1：Via densities are set and check file, including be arranged each metal interference networks text title and
The predetermined value of the via densities is set；
Step S2：It loads the domain and the via densities checks file；
Step S3：Obtain regional ensemble to be measured；
Step S4：Calculate the via densities in the region to be measured；And
Step S5：The via densities in the region to be measured are checked；If the via densities in the region to be measured are greater than
Equal to the predetermined value, then pass through, if the via densities in the region to be measured are less than the predetermined value, to the region to be measured
It is marked.
Specifically, in order to guarantee that layout design can meet process flow, meeting basis is set in IC Layout
It counts regular configuration file and checks writing for file (DRC, design rule check) to be designed rule.By automation
The automation inspection to layout design may be implemented in detection instrument, DRC.It is a kind of special the inspection of via densities can be converted to
Layout design rules inspection, the automation inspection to via densities is realized by DRC.
Specifically, in step sl, when the number of through-holes between the metal connecting line to different layers detects, needing elder generation
Via densities are set and check file.
Further, in the last part technology of semiconductor devices, adjacent two layers metal connecting line needs are realized mutually by through-hole
Even, this interconnection will carry out between the neighbouring double layer of metal line of the same metal wire interference networks.Due to described
Interference networks are included one or more metals on domain, therefore, in the step S1, are needed to different metal interference networks
Identification is distinguished, then the setting via densities check that file includes：The text of each metal interference networks on domain is set
Title.
Further, to realize the automatic detection to the via densities of metal connecting line join domain, described be arranged is led to
Hole density checks that file further includes：The predetermined value of the via densities is set.Specifically, designer can be certainly in layout design
The inspection intensity of via densities is defined, i.e., by the predetermined value of design requirement setting via densities.Realize metal wire join domain
Via densities check controllable.Further, the predetermined value is the minimum value of the via densities, i.e., according to different design need
Ask, in conjunction in design rule about through-hole width (width), interval (space) and with the extended range of upper/lower layer metallic
(enclosure) regulation, designer can set the minimum value of the via densities of permission.
Specifically, integrated circuit diagram and the via densities set are checked file load in the step S2
Into automation tools, such as EDA (electric design automation, Electronic Design Automatic) tool.Further
, after the integrated circuit diagram is loaded into automation tools, in automation tools, by the metal connecting line in domain
A series of metal connecting line figures are abstracted into, specifically, metal connecting line figure is the polygon that multiple barrier defines.
Further, in step s3, it is described be detected as it is close to the through-hole in metal interference networks same in the domain
Degree is detected.Specifically, comprising all metal connecting lines with connection relationship in same metal interference networks, further,
The connection relationship is that the connection of adjacent two layers metal connecting line in same metal interference networks is realized by through-hole.Described in acquisition
Before region to be measured, need first to identify the interconnection area of adjacent two layers metal connecting line in same metal interference networks on domain,
Interconnection area is the region to be measured.
Further, usually there are multiple metal wire interference networks in a domain, referring to Fig.2, illustrating difference
The domain structure of metal interference networks, wherein MiIndicate that the metal connecting line in metal interference networks, subscript i indicate metal wire institute
The number of plies；ViThe through-hole of upper/lower layer metallic cabling is connected between indication circuit, i indicates the number of plies where through-hole, other schematic diagrames
Middle meaning is identical.
Refering to Fig. 2 and Fig. 3, metal connecting line Mi-111 and metal connecting line Mi12 pass through through-hole Vi-1Connection, MiWith Mi+1By logical
Hole ViConnection.By can be seen that in Fig. 2 and Fig. 3, metal connecting line Mi12 share 3 metal line a_Mi121, metal wire b_Mi122 and gold
Belong to line c_Mi123.Wherein metal wire a_Mi121 and metal wire c_Mi123 pass through through-hole Vi、Vi-1With metal connecting line Mi+113 or golden
Belong to line Mi-111 are connected, and form interference networks.Metal wire b_Mi122 not with upper/lower layer metallic line M in figurei+113 or metal connect
Line Mi-111 are connected, i.e. metal wire b_Mi122 are not belonging to this interference networks.
Due to usually containing multiple metal wire interference networks in a domain, if not by variant metal interconnection net
Network is distinguish, and the domain overlapping region of different interference networks may be extracted when extracting metal wire interconnection area, is mentioned
Take region entanglement.Therefore it needs to distinguish identification to different metal interference networks.Therefore it needs to gold different in domain
Belong to interference networks and text title is set, to distinguish.Preferably, can one layer of same metal interference networks in domain or
The text title is set on metal connecting line described in multilayer.It should be noted that set to the metal interference networks in domain herein
Via densities check that the text title of the metal interference networks in file corresponds in the text title and step S1 set.
Then the step of acquisition regional ensemble to be measured includes：Obtain the metal connecting line of metal interference networks to be measured.Specifically
, after domain and the via densities set are checked that file is loaded into automation tools, checked by the via densities
File and the automation tools identify metal interconnecting network to be measured, and according to the connection relationship of metal connecting line, extract to
Survey all metal connecting lines in metal interconnecting network.
Further, since the connection relationship of metal connecting line is that neighbouring double layer of metal line is real by through-hole connection
Existing, as shown in Fig. 2, through-hole is perpendicular to upper/lower layer metallic line in actual technique.In automation tools, by domain
In metal connecting line be abstracted into a series of metal connecting line figures, and the interconnection area of the adjacent two layers metal connecting line is domain
The overlapping region of upper respective metal line figure.Then the region to be measured is the overlapping region.
Further, adjacent two are identified by the overlapping region of corresponding adjacent two layers metal connecting line figure on identification domain
The interconnection area of layer metal connecting line, that is, identify region to be measured.Specifically, refering to Fig. 3, in Fig. 3, metal wire a_Mi121, gold
Belong to line b_Mi122 and metal wire c_MiWith upper/lower layer metallic line Mi-111 and Mi+113 have overlapping region (to respectively correspond weight in figure
Folded region 14,15, overlapping region 16,17, overlapping region 18,19), but as shown in Figure 2, metal wire b_Mi122 not and up and down
Layer metal is connected, and is also not belonging to this metal interference networks, therefore the only metalolic network thus of overlapping region 14,15,18,19 is mutual
Even region, overlapping region 16,17 should not be identified as MiWith upper/lower layer metallic Mi+1、Mi-1Metal interconnection area.
Further, the collection for obtaining the region to be measured is combined into the set for obtaining the overlapping region.Specifically, identifying
After the overlapping region, the overlapping region of the adjacent two layers metal connecting line figure identified is extracted, the overlapping is finally obtained
The set in region.
Refering to Fig. 3, the extraction process of overlapping region set is illustrated by taking Fig. 3 as an example.There are two metals to interconnect in Fig. 3
Network VDD_a and VDD_b.Metal interference networks to be measured are identified by connection relationship and text mark first, are extracted again later
All metal connecting lines in metal interference networks to be measured out, such as metal interference networks to be measured are metal interference networks " VDD_a ",
The metal connecting line in the metal interference networks, including metal connecting line a_M are then extracted by connection relationshipi-121, metal connecting line a_
Mi22 and metal connecting line a_Mi+123.Similarly, if metal interference networks to be measured are metal interference networks VDD_b, pass through text mark
Note " VDD_b " and connection relationship extract the metal connecting line on the interference networks, including metal connecting line b_Mi-131, metal connecting line b_
Mi32 and metal connecting line b_Mi+133。
Gather next, extracting overlapping region in metal interference networks to be measured.If metal interference networks to be measured are that metal is mutual
Network network VDD_a, then extracts metal connecting line a_Mi-1With metal connecting line a_MiOverlapping region 24 and metal connecting line a_MiAnd gold
Belong to line a_Mi+1Set of the overlapping region 25 as region to be measured.If metal interference networks to be measured are metal interference networks
In VDD_b, then metal connecting line b_M is extractedi-1With metal connecting line b_MiOverlapping region 34 and metal connecting line b_MiConnect with metal
Line b_Mi+1Set of the overlapping region 35 as region to be measured.
Further, in step s 4, the via densities in the region to be measured are all through-holes in the overlapping region
The area ratio of the gross area and the overlapping region.Specifically, the via densities calculating process in the region to be measured is：If same
Adjacent two layers metal connecting line M in metal interference networksi41 and metal connecting line Mi+142 width is respectively WMiAnd WMi+1, then two
The length and width of layer metal connecting line lap are also just respectively WMiAnd WMi+1.In addition, through-hole V in overlapping regioniLength and wide point
It Wei not LViAnd WViIf through-hole number is n on the overlapping region, then via densities D is represented by：
Refering to Fig. 6, if metal connecting line width as shown in the figure is to be set as 1, through-hole is the square that side length is 0.1, in gold
Belong to line Mi41 and metal connecting line Mi+142 overlapping region 43, does not have through-hole Vi, i.e., through-hole no marking the case where, i.e., via densities are
0.In metal connecting line Mi41 and metal connecting line Mi+1A through-hole V has been beaten in 43 overlapping region 44i, at this time via densities be then
(0.1*0.1) * 1/ (1*1)=0.01.
Continue, refering in Fig. 7, the width of metal wire Mi shown in Fig. 7 and Mi+1 are to be set as 1, and through-hole is that side length is 0.1
Square, then overlapping region 1,3,7,9 via densities be (0.1*0.1) * 9/ (1*1)=0.09.Overlapping region 2,4,
6,8 via densities are (0.1*0.1) * 4/ (1*1)=0.04.The via densities of overlapping region 5 are (0.1*0.1) * 1/ (1*1)
=0.01.
It should be noted that the above calculating process is intended merely to the concept for helping to understand via densities and its checks logic,
Operation, user or layout design personnel can be executed automatically by related command in practical applications without carrying out this operation.
Further, step S5 is carried out, the via densities of the overlapping region are checked, if the overlapping region
Via densities are more than or equal to the predetermined value, then check and pass through, right if the via densities of the overlapping region are less than predetermined value
The overlapping region is marked.The via densities of the i.e. described overlapping region are more than or equal to the minimum value of acceptable via densities
When, the via densities of the overlapping region meet design requirement, then by checking, when the via densities of the overlapping region are less than
When the minimum value of acceptable via densities, then show that the via densities of overlapping region are too small, therefore the region can be mentioned
The property shown label, so that designer carries out subsequent improvement.Further, inspection packet is carried out to the via densities of the overlapping region
It includes：(through-hole is beaten less to the inspection and the overlapping region through-hole of the overlapping region through-hole no marking (overlapping region does not have through-hole)
Density is too low) inspection.It should be understood that designer can adjust through-hole by adjusting the size of via densities predetermined value
Density checks intensity.Predetermined value is bigger, then via densities needed for showing the domain are bigger, checks that intensity is stronger.Conversely, then checking
Intensity is weaker.It, then only need to be pre- by this if designer need to only check the case where interconnection area through-hole no marking (via densities 0)
Definite value is set as one close to 0 positive number.
With continued reference to 6 and Fig. 7, through-hole no marking inspection and label are specifically described, as shown in fig. 6, in metal wire
MiWith metal wire Mi+1Overlapping region have overlapping region 43 and overlapping region 44, at overlapping region 43, without through-hole by metal
Line MiWith metal wire Mi+1Connection, the at this time referred to as no marking of through-hole.To realize the check mark in through-hole no marking region, in through-hole
Density checks that the predetermined value being arranged in file should be set as a positive number close to 0, such as 0.001.Checking overlapping region 43
When, via densities 0<0.001, design rule is violated, overlapping region 43 will be labeled；Checking overlapping region 44
When, via densities 0.01>0.0001, meet via densities design rule, overlapping region 44 can pass through inspection.Referring to above-mentioned
Illustrate, checks that file can realize the inspection of metal interconnection area through-hole no marking by via densities, through-hole no marking region is mentioned
The property shown label facilitates layout design personnel to carry out subsequent domain change.
Refering to Fig. 7, inspection is played through-hole less and label is specifically described, through-hole beats the interconnecting area referred in metal less
The case where there are through-holes in domain, but the density of through-hole is unsatisfactory for design rule, the i.e. via densities of overlapping region are less than acceptable
The minimum value of via densities.In one embodiment, metal wire MiWith metal wire Mi+1Overlapping region have No. 1 overlapping region
451, No. 2 overlapping regions 452,3 overlapping region 454,5 of overlapping region 453,4 overlapping region of overlapping region 455,6
456, No. 7 overlapping regions, 457, No. 8 overlapping regions 458 and No. 9 overlapping region 459.The via densities of overlapping region are different, Fig. 7
Shown in metal wire MiAnd Mi+1Width be 1, through-hole is the square that side length is 0.1.
Via densities No. 1, No. 3, No. 7 and No. 9 overlapping region are (0.1*0.1) * 9/ (1*1)=0.09；
Via densities No. 2, No. 4, No. 6 and No. 8 overlapping regions are (0.1*0.1) * 4/ (1*1)=0.04；
Via densities No. 5 overlapping regions are (0.1*0.1) * 1/ (1*1)=0.01.
Assuming that setting via densities minimum value is 0.05, then have
1. the via densities 0.09 of No. 1, No. 3, No. 7 and No. 9 overlapping region>0.05 meets design rule, passes through；
2. the via densities 0.04 of No. 2, No. 4, No. 6 and No. 8 overlapping regions<0.05 violates design rule, is labeled；
3. the via densities 0.01 of No. 5 overlapping regions<0.05 violates design rule, is labeled.
Assuming that setting via densities minimum value is 0.03, then have
1. the via densities 0.09 of No. 1, No. 3, No. 7 and No. 9 overlapping region>0.03 meets design rule, passes through；
2. the via densities 0.04 of No. 2, No. 4, No. 6 and No. 8 overlapping regions>0.03 meets design rule, passes through；
3. the via densities 0.01 of No. 5 overlapping regions<0.03 violates design rule, is labeled.
Assuming that setting via densities minimum value is 0.005, then have
1. the via densities 0.09 of No. 1, No. 3, No. 7 and No. 9 overlapping region>0.01 meets design rule, passes through；
2. the via densities 0.04 of No. 2, No. 4, No. 6 and No. 8 overlapping regions>0.01 meets design rule, passes through；
3. the via densities 0.01 of No. 5 overlapping regions<0.005 meets design rule, passes through.
Referring to above description, the inspection that file can realize that metal interconnection area through-hole is beaten less is checked by via densities,
The indicative label for beating through-hole region less facilitates layout design personnel to carry out subsequent domain change.
In conclusion in the inspection method of integrated circuit diagram provided by the invention, including：Via densities inspection is set
File, including the text title of each metal interference networks is arranged and the predetermined value of the via densities is arranged；Load institute
It states domain and the via densities checks file；Obtain regional ensemble to be measured；Calculate the via densities in the region to be measured；And
The via densities in the region to be measured are checked；If the via densities in the region to be measured are more than or equal to the predetermined value,
Then pass through, if the via densities in the region to be measured are less than the predetermined value, the region to be measured is marked.The present invention
The inspection of via densities is converted a kind of special layout design rules inspection by institute's providing method, passes through design rule check text
Part realizes to the automation inspections of via densities, it can be achieved that through-hole no marking or the less accurate positionin beaten, check that covering surface is complete, can
Indicative label quickly and efficiently is carried out to the region for not meeting design rule, domain is carried out more convenient for layout design personnel
Change, improves and check efficiency save the cost.
Further, the present invention not only may be implemented to lack metal wire join domain through-hole (through-hole no marking) situation
Qualitative examination, moreover it is possible to realize the quantitative check to metal wire join domain via densities not enough (through-hole is beaten less).Meanwhile designer
Member can also make to check intensity controlled according to the via densities of practical situations sets itself inspection.
The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and
Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (12)
1. a kind of inspection method of integrated circuit diagram, the domain includes one or more metals interference networks its features and exists
In, including：
Via densities are set and check file, including the text title of each metal interference networks is arranged and the through-hole is arranged
The predetermined value of density；
It loads the domain and the via densities checks file；
Obtain regional ensemble to be measured；
Calculate the via densities in the region to be measured；And
The via densities in the region to be measured are checked；If the via densities in the region to be measured are more than or equal to described predetermined
Value, then pass through, if the via densities in the region to be measured are less than the predetermined value, the region to be measured is marked.
2. the inspection method of integrated circuit diagram as described in claim 1, which is characterized in that the same metal interference networks
Including all metal connecting lines with connection relationship.
3. the inspection method of integrated circuit diagram as claimed in claim 2, which is characterized in that the connection relationship is by logical
Realize the connection of adjacent two layers metal connecting line in same metal interference networks in hole.
4. the inspection method of integrated circuit diagram as claimed in claim 2, which is characterized in that in same metal interference networks
The text title is set on one or more layers described metal connecting line.
5. the inspection method of integrated circuit diagram as described in claim 1, which is characterized in that described to obtain regional ensemble to be measured
The step of include：Obtain the metal connecting line of metal interference networks to be measured.
6. the inspection method of integrated circuit diagram as claimed in claim 5, which is characterized in that interconnected according to the metal to be measured
The text title of network identifies metal interference networks to be detected on the domain；According to connection relationship, extract to be measured
All metal connecting lines of metal interference networks.
7. the inspection method of integrated circuit diagram as claimed in claim 5, which is characterized in that will be in the metal interference networks
Metal connecting line be abstracted into a series of metal connecting line figures, the join domain of adjacent two layers metal connecting line is respective metal on domain
The overlapping region of line figure.
8. the inspection method of integrated circuit diagram as claimed in claim 7, which is characterized in that the regional ensemble to be measured is institute
State the set of overlapping region.
9. the inspection method of integrated circuit diagram as claimed in claim 8, which is characterized in that according on the domain it is described to
The positional relationship of metal connecting line figure in metal interference networks is surveyed, the overlapping region of adjacent two layers metal connecting line figure is extracted.
10. the inspection method of integrated circuit diagram as claimed in claim 8, which is characterized in that the through-hole of the overlapping region
Density is the area ratio of all the through-hole gross areas and the overlapping region in the overlapping region.
11. the inspection method of integrated circuit diagram as claimed in claim 10, which is characterized in that the inspection inspection includes to institute
The inspection that the inspection and the overlapping region through-hole for stating overlapping region through-hole no marking are beaten less.
12. the inspection method of integrated circuit diagram as claimed in claim 11, which is characterized in that if the overlapping region is logical
Hole density is less than the predetermined value, then the through-hole no marking of the overlapping region or the overlapping region through-hole are beaten less, to institute
Overlapping region is stated to be marked.
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| CN201810672248.0A CN108830003A (en) | 2018-06-26 | 2018-06-26 | The inspection method of integrated circuit diagram |
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Application publication date: 20181116 |