CN108807512B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN108807512B
CN108807512B CN201710310685.3A CN201710310685A CN108807512B CN 108807512 B CN108807512 B CN 108807512B CN 201710310685 A CN201710310685 A CN 201710310685A CN 108807512 B CN108807512 B CN 108807512B
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well
top layer
conductivity type
semiconductor substrate
doped region
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CN108807512A (en
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林鑫成
胡钰豪
林文新
吴政璁
马洛宜·库马
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention provides a semiconductor device and a forming method thereof, wherein the semiconductor device comprises a semiconductor substrate with a first conductive type and a first well arranged in the semiconductor substrate, wherein the first well has a second conductive type opposite to the first conductive type. The semiconductor device also includes a buried layer disposed in the semiconductor substrate and under the first well, wherein the buried layer has the first conductivity type and contacts the first well. The semiconductor device further comprises a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices having buried layers and methods of forming the same.
Background
In the semiconductor industry, an Ultra High Voltage (UHV) device generally includes a well and a top layer with two opposite conductive types in a drift region (drift region), such as a deep high voltage N-well (DHVNW) and a P-type top layer located in the deep high voltage N-well and close to the top surface of the device, so that carriers of the two opposite conductive types maintain electrical balance, and thus the UHV device is easily fully depleted, the breakdown voltage of the device is increased, and the on-resistance is reduced.
However, in the non-epitaxial semiconductor process, the formation of the deep high voltage well requires high temperature diffusion and injection (D/I) so that the carrier concentration is not uniformly distributed and the high concentration carriers are concentrated on the top surface of the semiconductor substrate. In order to make the carrier concentration distribution uniform and easily achieve complete depletion, the carrier concentration of the top layer in the deep high voltage well must be increased, but the on-resistance of the extra-high voltage device will be increased accordingly. In addition, since the carrier concentration of the deep high voltage well is concentrated on the top, carriers are easily injected into the field oxide layer due to the high electric field, so that the reliability of the device is affected.
Although the semiconductor devices and the methods for forming the same are adequate for their intended purposes, they have not yet fully met the requirements in every aspect, and thus there are still problems to be solved in the art of adjusting the carrier concentration in the drift region of semiconductor devices.
Disclosure of Invention
Embodiments of a semiconductor device and a method of forming the same are provided. In order to reduce the surface electric field of the semiconductor device and make the semiconductor device easily reach complete depletion, the embodiment of the invention provides a semiconductor substrate with a first conductive type, a first well, namely a deep high-voltage well, is arranged in the semiconductor substrate, the first well has a second conductive type opposite to the first conductive type, a buried layer with the first conductive type is arranged under the first well to reduce the carrier doping concentration of a first top layer with the first conductive type in the first well, the carrier concentration originally positioned at the top of the semiconductor substrate and having the first conductive type is dispersed to the bottom of the semiconductor substrate, so that the carrier concentration of the first well close to the top surface of the semiconductor substrate is not balanced by only one first top layer with the opposite conductive type, and the on-resistance of the semiconductor device is further reduced.
In addition, by arranging the buried layer with the opposite conduction type under the deep high-voltage well, the carrier concentration of the deep high-voltage well is not concentrated at the top, the probability of injecting carriers into the field oxide layer can be effectively reduced, and the reliability of the semiconductor device is further improved.
According to some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well disposed in the semiconductor substrate, wherein the first well has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a buried layer disposed in the semiconductor substrate and under the first well, wherein the buried layer has the first conductivity type and the buried layer contacts the first well. The semiconductor device further comprises a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.
According to some embodiments, a method of forming a semiconductor device is provided. The method includes providing a semiconductor substrate having a first conductivity type, and forming a first well within the semiconductor substrate, wherein the first well has a second conductivity type opposite the first conductivity type. The method also includes forming a buried layer in the semiconductor substrate and under the first well, wherein the buried layer has the first conductivity type and the buried layer contacts the first well. The method further includes forming a source electrode, a drain electrode, and a gate structure on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.
Drawings
Aspects of embodiments of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. It is noted that, according to industry standard practice, the various features (features) in the drawings may not be drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-7 are cross-sectional views illustrating various stages in the formation of a semiconductor device, according to some embodiments of the present invention.
Reference numerals:
100 to a semiconductor device;
101-a semiconductor substrate;
103-patterning the photoresist layer;
105-embedding layer;
107a, 107 b-isolation structures;
109 to the first well;
111 to a second well;
113 to a first top layer;
115 to a second top layer;
117-gate structure;
119-a first doped region;
121-a second doped region;
123 to a third doped region;
125-interlayer dielectric layer;
127 to a source electrode;
127a, 127b, 129a to guide holes;
129-drain electrode;
d-depth.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different elements of the provided semiconductor devices. Specific examples of the elements and their configurations are described below to simplify the embodiments of the present invention. These are, of course, merely examples and are not intended to be limiting. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described below. Like reference numerals are used to identify like elements in the various figures and described embodiments. It will be understood that additional operations may be provided before, during, and after the methods described below, and that some of the recited operations may be substituted or deleted for other embodiments of the methods.
Some embodiments of the present invention provide methods of forming semiconductor devices. Fig. 1-7 are cross-sectional views illustrating various stages in the formation of a semiconductor device 100, in accordance with some embodiments of the present invention.
According to some embodiments, as shown in fig. 1, a semiconductor substrate 101 having a first conductivity type is provided. The semiconductor substrate 101 may be made of silicon or other semiconductor materials, or the semiconductor substrate 101 may comprise other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. The first conductivity type of the present embodiment is P-type, so the semiconductor substrate 101 is a lightly doped P-type substrate. In other embodiments, the first conductivity type may be N-type, and thus the semiconductor substrate 101 is a lightly doped N-type substrate.
Continuing as described above, as shown in fig. 1, a patterned photoresist layer 103 is selectively formed on the semiconductor substrate 101. The region not covered by the patterned photoresist layer 103 is a region where a buried layer and a first well are subsequently formed, and the region covered by the patterned photoresist layer 103 is a region where a second well is subsequently formed. In other embodiments, the patterned photoresist layer 103 may not be formed, and in a subsequent process, a buried layer is formed globally within the semiconductor substrate 101.
According to some embodiments, as shown in fig. 2, a buried layer 105 having a first conductive type is formed in the semiconductor substrate 101 through an ion implantation process and a high temperature diffusion process using the patterned photoresist layer 103 as a mask. In the present embodiment, the semiconductor substrate 101 is a P-type substrate, and the buried layer 105 is formed by implanting a P-type dopant, such as boron (B), into the semiconductor substrate 101. In other embodiments, the semiconductor substrate 101 is an N-type substrate, and the buried layer 105 is formed by implanting N-type dopants, such As phosphorus (P) or arsenic (As), into the semiconductor substrate 101. In addition, in some embodiments, the dopant concentration of buried layer 105 is about 1 × 1014Atom/cubic centimeter (atom/cm)3) To about 1x1015Atom/cubic centimeter (atom/cm)3) And the depth D of the buried layer 105 is in the range of about 5 μm to about 15 μm.
Next, as shown in fig. 3, the patterned photoresist layer 103 is removed, and isolation structures 107a and 107b are formed on the semiconductor substrate 101. In some embodiments, a portion of the isolation structures 107a and 107b is embedded in the semiconductor substrate 101, and another portion of the isolation structures 107a and 107b is formed over the semiconductor substrate 101.
In some embodiments, the isolation structures 107a and 107b may be formed using local oxidation of silicon (LOCOS) isolation techniques. In other embodiments, the isolation structures 107a and 107b may be Shallow Trench Isolation (STI) structures. In some embodiments, the isolation structures 107a and 107b are formed of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material.
According to some embodiments, as shown in fig. 4, a first well 109 is formed in the semiconductor substrate 101 and on the buried layer 105, the first well 109 having a second conductivity type opposite to the first conductivity type. In the present embodiment, the first well 109 is a deep high voltage N-well, and the dopant concentration of the first well 109 is about 1 × 1015Atom/cubic centimeter (atom/cm)3) To about 5x1015Atom/cubic centimeter (atom/cm)3) Within the range of (1). It is noted that the first well 109 is in contact with the buried layer 105, and the interface of the first well 109 and the buried layer 105 creates a P-N junction (P-N junction) due to the opposite conductivity type of the first well 109 and the buried layer 105.
The first well 109 may be formed by ion implantation, and in the present embodiment, the first well 109 and the buried layer 105 are formed by two separate ion implantation processes. In other embodiments, the first well 109 and the buried layer 105 may be formed simultaneously by the same energy ion implantation process, for example, the buried layer 105 is formed by implanting boron (B), and the first well 109 is formed by implanting phosphorus (P) or arsenic (As), since boron (B) has smaller ions, boron (B) may be implanted into the semiconductor substrate 101 at a faster rate under the same energy of ion implantation, and thus the P-type buried layer 105 may be formed under the N-type first well 109.
Then, as shown in fig. 4, a second well 111 is formed in the semiconductor substrate 101 having the first conductivity type, the second well 111 having the first conductivity type is adjacent to the first well 109, and the depth of the first well 109 is deeper than that of the second well 111, so the first well 109 can be referred to as a deep high voltage well. In the present embodiment, the second well 111 is a P-type well, and the second well111 at a doping concentration of about 1x1016Atom/cubic centimeter (atom/cm)3) To about 9x1016Atom/cubic centimeter (atom/cm)3) Within the range of (1). In some embodiments, the isolation structure 107a is on the first well 109 and covers a portion of the first well 109. The isolation structure 107b is on the second well 111, and covers a portion of the second well 111. In this embodiment, the length of the buried layer 105 is at least approximately the same as the length of the first well 109. In other embodiments where the patterned photoresist layer 103 is not formed, the buried layer 105 extends to below the second well 111.
According to some embodiments, as shown in fig. 5, a first top layer 113 and a second top layer 115 are formed within the first well 109 near the top of the first well 109. The first top layer 113 has a first conductivity type, the second top layer 115 is on the first top layer 113 and contacts the first top layer 113, and the second top layer 115 has a second conductivity type. In the present embodiment, the first top layer 113 is P-type, the second top layer 115 is N-type, and the first top layer 113 and the second top layer 115 are completely disposed below the isolation structure 107a, i.e., the projection range of the isolation structure 107a on the semiconductor substrate 101 completely covers the projection range of the first top layer 113 and the second top layer 115 on the semiconductor substrate 101.
It is noted that the interface of the first top layer 113 and the first well 109 creates a P-N junction because the first top layer 113 and the first well 109 have opposite conductivity types. Likewise, the interface of the second top layer 115 and the first top layer 113 also creates a P-N junction, since the second top layer 115 and the first top layer 113 have opposite conductivity types. In some embodiments, the dopant concentration of each of the first top layer 113 and the second top layer 115 is about 1 × 1016Atom/cubic centimeter (atom/cm)3) To about 9x1016Atom/cubic centimeter (atom/cm)3) And the dopant concentration of the first top layer 113 and the second top layer 115 are approximately the same.
Overall, the dopant concentration of the first and second top layers 113 and 115 is greater than the dopant concentration of the first well 109, and the dopant concentration of the first well 109 is greater than the dopant concentration of the buried layer 105.
In addition, according to some embodiments of the present invention, the interface between the buried layer 105 and the first well 109, the interface between the first well 109 and the first top layer 113, and the interface between the first top layer 113 and the second top layer 115 are all P-N junctions, and by uniformly dispersing a plurality of P-N junctions in the semiconductor substrate 101, the surface field (RESURF) can be reduced multiple times, so that the semiconductor device can withstand higher voltage, can easily reach complete depletion, and further reduce on-resistance and increase breakdown voltage.
Subsequently, as shown in fig. 5, a gate structure 117 is formed on the semiconductor substrate 101 and a portion of the isolation structure 107a, and the gate structure 117 covers a portion of the first well 109 and a portion of the second well 111. In some embodiments, the gate structure 117 may include one or more gate dielectric layers (not shown), and one or more gate electrode layers disposed on the gate dielectric layers (not shown).
The gate dielectric layer may be made of silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (low-k), or a combination of the foregoing. In some embodiments, the gate dielectric layer is formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or a spin coating (spin coating) process.
The gate electrode layer is made of a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), polysilicon, or other suitable material. In some embodiments, the gate electrode layer is formed by a deposition process and a patterning process. The deposition process may be a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a High Density Plasma CVD (HDPCVD) process, a metal-organic chemical vapor deposition (MOCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, or a combination thereof.
According to some embodiments, as shown in fig. 6, a first doped region 119 is formed within the first well 109, and a second doped region 121 and a third doped region 123 are formed within the second well 111. In addition, the third doped region 123 is adjacent to the second doped region 121. In some embodiments, the first doped region 119 has the same conductivity type as the first well 109, the second doped region 121 has the opposite conductivity type as the second well 111, and the third doped region 123 has the same conductivity type as the second well 111. In the present embodiment, the first doping region 119 is N-type, the second doping region 121 is N-type, the third doping region 123 is P-type, and the doping concentration of the first doping region 119, the second doping region 121 and the third doping region 123 is about 1 × 1018Atom/cubic centimeter (atom/cm)3) To about 1x1019Atom/cubic centimeter (atom/cm)3) Within the range of (1).
According to some embodiments, an inter-layer dielectric (ILD) layer 125 is formed on the semiconductor substrate 101, the isolation structures 107a and 107b, and the gate structure 117, as shown in fig. 7. In some embodiments, the interlayer dielectric layer 125 is formed of silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other suitable dielectric materials. The interlayer dielectric layer 125 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), spin-on coating, or other suitable process.
According to some embodiments, as shown in fig. 7, after the interlayer dielectric layer 125 is formed, the source electrode 127 and the drain electrode 129 are formed on the interlayer dielectric layer 125. In addition, via holes (via)127a, 127b, and 129a are formed in the interlayer dielectric layer 125. The drain electrode 129 is electrically connected to the first doped region 119 through a via hole 129a, and the source electrode 127 is electrically connected to the third doped region 123 and the second doped region 121 through via holes 127a and 127b, respectively. In some embodiments, the source electrode 127, the drain electrode 129, and the vias 127a, 127b, and 129a may comprise a metal or other suitable conductive material.
In some embodiments, the gate structure 117 is disposed between the source electrode 127 and the drain electrode 129, and the gate structure 117 is closer to the source electrode 127 than the drain electrode 129. After the source electrode 127 and the drain electrode 129 are formed, the semiconductor device 100 is completed.
In order to reduce the surface electric field of the semiconductor device and make the semiconductor device easily reach complete depletion, the embodiment of the invention provides a semiconductor substrate with a first conductive type, a first well, namely a deep high-voltage well, is arranged in the semiconductor substrate, the first well has a second conductive type opposite to the first conductive type, a buried layer with the first conductive type is arranged under the first well to reduce the carrier doping concentration of a first top layer with the first conductive type in the first well, the carrier concentration originally positioned at the top of the semiconductor substrate and having the first conductive type is dispersed to the bottom of the semiconductor substrate, so that the carrier concentration of the first well close to the top surface of the semiconductor substrate is not balanced by only one first top layer with the opposite conductive type, and the on-resistance of the semiconductor device is further reduced.
In addition, by arranging the buried layer with the opposite conduction type under the first trap, the carrier concentration of the first trap can not be concentrated at the top, the probability of injecting carriers into the field oxide layer can be effectively reduced, and the reliability of the semiconductor device is further improved.
The components of several embodiments are summarized above so that those skilled in the art to which the invention pertains can more clearly understand the aspects of the embodiments of the invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art to which the invention relates will appreciate that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the invention.

Claims (12)

1. A semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
a first well disposed in the semiconductor substrate, wherein the first well has a second conductivity type opposite to the first conductivity type;
a first top layer disposed in the first well and having the first conductivity type;
a second top layer disposed in the first well and completely on the first top layer, wherein the second top layer has the second conductivity type and contacts the first top layer;
a buried layer disposed in the semiconductor substrate and under the first well, wherein the buried layer has the first conductivity type and contacts the first well; and
a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is disposed between the source electrode and the drain electrode, and the drain electrode is disposed above the buried layer;
the dopant concentration of the first top layer and the second top layer is greater than that of the first well, and the dopant concentration of the first well is greater than that of the buried layer.
2. The semiconductor device of claim 1, wherein the gate structure is closer to the source electrode than to the drain electrode.
3. The semiconductor device of claim 1, further comprising:
a second well disposed in the semiconductor substrate and adjacent to the first well, wherein the second well has the first conductivity type; and
an isolation structure covering a portion of the first well;
the gate structure is disposed on a portion of the isolation structure and covers a portion of the first well and a portion of the second well.
4. The semiconductor device of claim 3, further comprising:
a first doped region disposed in the first well and having the second conductivity type;
a second doped region disposed in the second well and having the second conductivity type; and
a third doped region disposed in the second well, having the first conductivity type and adjacent to the second doped region;
wherein the first doped region is electrically connected to the drain electrode, and the second doped region and the third doped region are electrically connected to the source electrode.
5. The semiconductor device of claim 3, wherein the buried layer extends below the second well.
6. The semiconductor device of claim 3, wherein the first top layer and the second top layer are disposed entirely below the isolation structure.
7. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate with a first conductive type;
forming a first well in the semiconductor substrate, wherein the first well has a second conductivity type opposite to the first conductivity type;
forming a first top layer in the first well, the first top layer having the first conductivity type;
forming a second top layer in the first well and on the first top layer, the second top layer having the second conductivity type, wherein the second top layer contacts the first top layer;
forming a buried layer in the semiconductor substrate and under the first well, wherein the buried layer has the first conductivity type and contacts the first well; and
forming a source electrode, a drain electrode and a gate structure on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode, and the drain electrode is located above the buried layer;
the dopant concentration of the first top layer and the second top layer is greater than that of the first well, and the dopant concentration of the first well is greater than that of the buried layer.
8. The method of claim 7, wherein said gate structure is closer to said source electrode than to said drain electrode.
9. The method of forming a semiconductor device according to claim 7, further comprising:
forming a second well in the semiconductor substrate, wherein the second well is adjacent to the first well and has the first conductivity type; and
forming an isolation structure to cover a portion of the first well;
wherein the gate structure is formed on a portion of the isolation structure and covers a portion of the first well and a portion of the second well.
10. The method of forming a semiconductor device according to claim 9, further comprising:
forming a first doped region in the first well, wherein the first doped region has the second conductive type;
forming a second doped region in the second well, wherein the second doped region has the second conductivity type; and
forming a third doped region in the second well, the third doped region having the first conductivity type and being adjacent to the second doped region;
wherein the first doped region is electrically connected to the drain electrode, and the second doped region and the third doped region are electrically connected to the source electrode.
11. The method of claim 9, wherein said buried layer extends below said second well.
12. The method of claim 9, wherein the first top layer and the second top layer are formed entirely under the isolation structure.
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