CN108733617A - 64 parallel-by-bits of Fibre channel scramble the FPGA implementation method of descrambler - Google Patents

64 parallel-by-bits of Fibre channel scramble the FPGA implementation method of descrambler Download PDF

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CN108733617A
CN108733617A CN201810467263.1A CN201810467263A CN108733617A CN 108733617 A CN108733617 A CN 108733617A CN 201810467263 A CN201810467263 A CN 201810467263A CN 108733617 A CN108733617 A CN 108733617A
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xin
data
output
tree
exclusive
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CN108733617B (en
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舒勇
朱力
翟大海
王昌庆
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Telecommunication Science And Technology Fifth Research Institute Co Ltd
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
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Abstract

The present invention provides the FPGA implementation methods that a kind of 64 parallel-by-bits of Fibre channel scramble descrambler.Including scrambling realization method and descrambling implementation method.The scrambling realization method is to realize the parallel scrambling in 64 tunnels using an exclusive or tree and a delay cell.The descrambling implementation method is to realize the parallel descrambling in 64 tunnels using an exclusive or tree and a delay cell.The present invention provides a kind of FPGA implementations of more high degree of parallelism to scramble implementation：The program realizes the parallel scrambling in 64 tunnels using an exclusive or tree and a delay cell.The parallel descrambling in 64 tunnels is realized using an exclusive or tree and a delay cell.The present invention can preferably adapt to the requirement of Fibre channel communication high speed rates.

Description

64 parallel-by-bits of Fibre channel scramble the FPGA implementation method of descrambler
Technical field
The invention belongs to scramble descrambler technical field more particularly to 64 parallel-by-bits of Fibre channel scrambling solution parallel Disturb the FPGA implementation method of device.
Background technology
In Fibre channel standards, when using 8B/10B transmission modes, in order to reduce long character recurrence probability, send End needs to scramble using frame, and receiving terminal needs to descramble using frame.Frame scrambling is generated by a linear feedback shift register Pseudo-random sequence carries out XOR operation completion with transmission data, and the corresponding multinomial of linear feedback shift register is G (x)=x58 +x39The initial value of+1,58 bits is low 58 of hexadecimal number 029438798327338h.Frame descrambling can be believed by inputting Number with its linear displacement signal carry out XOR operation completion.
In Fibre channel standards, the scrambling descrambling for giving 32 bit parallel inputs realizes structure chart.
However, in Fibre channel communications, usual rate is higher, even up to 8G bps sometimes, using 32 tunnels Parallel, FPGA is difficult to realize, it is therefore desirable to the FPGA implementations of more high degree of parallelism.
Invention content
In order to achieve the above objectives, the present invention provides the FPGA that a kind of 64 parallel-by-bits of Fibre channel scramble descrambler Implementation method, including scrambling realization method and descrambling implementation method；
The scrambling realization method is to realize the parallel scrambling in 64 tunnels, exclusive or using an exclusive or tree and a delay cell The output of tree is the output after scrambling；The input data of the delay unit is the output data of exclusive or tree, the output of exclusive or tree Data are after delay process as the output data of delay unit；
The input data of exclusive or tree is 64 data for needing to carry out scrambled 64 bit parallel data and delay unit output, Input data is computed output data of rear obtained 64 data as exclusive or tree, and calculation formula is：
1-39 of output data are：
40-58 of output data are：
59-64 of output data are：
In above-mentioned formula, din (n) indicates to need to carry out n-th of scrambled 64 bit parallel data, and dout (n) indicates to add Disturb 64 data exported with exclusive or tree n-th；
Xin_d (7) is expressed as the data of n-th of bit of scrambling time delay module output, and primary data is：xin_d (1)=xin_d (2)=... xin_d (6)=0；Xin_d (7) to xin_d (64) is low 58 of 029438798327338h, Middle xin_d (7) is a high position, and xin_d (58) is low level；
The descrambling implementation method is to realize the parallel descrambling in 64 tunnels, exclusive or using an exclusive or tree and a delay cell The output of tree is the output after descrambling；The input data of the delay unit is 64 bit parallel datas descrambled, different Or tree output data after delay process as the output data of delay unit；
The input data of exclusive or tree be 64 bit parallel datas descrambled and delay unit output 64 data, Input data is computed output data of rear obtained 64 data as exclusive or tree, and calculation formula is：
1-39 of output data are：
The 40-58 of output data is：
59-64 of output data are：
In above-mentioned formula, din (n) indicates that n-th of 64 bit parallel datas descrambled, dout (n) indicate solution Disturb 64 data exported with exclusive or tree n-th；
Xin-d (n) is expressed as the data of n-th of bit of descrambling delay unit output, and primary data is：xin_d (1)=xin_d (2)=... xin_d (6)=0；Xin_d (7) to xin_d (64) is low 58 of 029438798327338h, Middle xin_d (7) is a high position, and xin_d (58) is low level.
Beneficial effects of the present invention are：
The present invention provides a kind of FPGA implementations of more high degree of parallelism to scramble implementation：The program is different using one Or tree and a delay cell realize the parallel scrambling in 64 tunnels.The parallel solution in 64 tunnels is realized using an exclusive or tree and a delay cell It disturbs.The present invention can preferably adapt to the requirement of Fibre channel communication high speed rates.
Description of the drawings
The structure that Fig. 1 is relied on by scrambling realization method.
The structure that Fig. 2 is relied on for descrambling implementation method.
Specific implementation mode
The FPGA implementation method of 64 parallel-by-bits of Fibre channel scrambling descrambler of the present invention, including scrambling are realized Method and descrambling implementation method.
The scrambling realization method is as shown in Figure 1, be real using an exclusive or tree and a delay cell (D in Fig. 1) The parallel scrambling in existing 64 tunnels, the output of the exclusive or tree are the output after scrambling；The input data of the delay unit is exclusive or The output data of tree, the output data of exclusive or tree is after delay process as the output data of delay unit.
The input data of exclusive or tree is 64 data for needing to carry out scrambled 64 bit parallel data and delay unit output, Input data is computed output data of rear obtained 64 data as exclusive or tree, and calculation formula is：
1-39 of output data are：
40-58 of output data are：
59-64 of output data are：
In above-mentioned formula, din (n) indicates to need to carry out n-th of scrambled 64 bit parallel data, and dout (n) indicates to add Disturb 64 data exported with exclusive or tree n-th；
Xin_d (n) is expressed as the data of n-th of bit of scrambling time delay module output, and primary data is：xin_d (1)=xin-d (2)=... xin_d (6)=0；Xin_d (7) to xin_d (64) is low 58 of 029438798327338h, Middle xin_d (7) is a high position, and xin_d (58) is low level.
It is specifically described below.
Exclusive or tree table is shown as in Fig. 1：
D is expressed as in Fig. 1：
Xin_d (1)=xin (1)
Xin_d (2)=xin (2)
Xin_d (3)=xin (3)
Xin_d (4)=xin (4)
Xin_d (5)=xin (5)
Xin_d (6)=xin (6)
Xin_d (7)=xin (7)
Xin_d (8)=xin (8)
Xin_d (9)=xin (9)
Xin_d (10)=xin (10)
Xin_d (11)=xin (11)
Xin_d (12)=xin (12)
Xin_d (13)=xin (13)
Xin_d (14)=xin (14)
Xin_d (15)=xin (15)
Xin_d (16)=xin (16)
Xin_d (17)=xin (17)
Xin_d (18)=xin (18)
Xin_d (19)=xin (19)
Xin_d (20)=xin (20)
Xin_d (21)=xin (21)
Xin_d (22)=xin (22)
Xin_d (23)=xin (23)
Xin_d (24)=xin (24)
Xin_d (25)=xin (25)
Xin_d (26)=xin (26)
Xin_d (27)=xin (27)
Xin_d (28)=xin (28)
Xin_d (29)=xin (29)
Xin_d (30)=xin (30)
Xin_d (31)=xin (31)
Xin_d (32)=xin (32)
Xin_d (33)=xin (33)
Xin_d (34)=xin (34)
Xin_d (35)=xin (35)
Xin_d (36)=xin (36)
Xin_d (37)=xin (37)
Xin_d (38)=xin (38)
Xin_d (39)=xin (39)
Xin_d (40)=xin (40)
Xin_d (41)=xin (41)
Xin_d (42)=xin (42)
Xin_d (43)=xin (43)
Xin_d (44)=xin (44)
Xin_d (45)=xin (45)
Xin_d (46)=xin (46)
Xin_d (47)=xin (47)
Xin_d (48)=xin (48)
Xin_d (49)=xin (49)
Xin_d (50)=xin (50)
Xin_d (51)=xin (51)
Xin_d (52)=xin (52)
Xin_d (53)=xin (53)
Xin_d (54)=xin (54)
Xin_d (55)=xin (55)
Xin_d (56)=xin (56)
Xin_d (57)=xin (57)
Xin_d (58)=xin (58)
Xin-d (59)=xin (59)
Xin-d (60)=xin (60)
Xin-d (61)=xin (61)
Xin-d (62)=xin (62)
Xin_d (63)=xin (63)
Xin_d (64)=xin (64)
As shown in Fig. 2, the descrambling implementation method is real using an exclusive or tree and a delay cell (D in Fig. 2) The parallel descrambling in existing 64 tunnels, the output of exclusive or tree are the output after descrambling；The input data of the delay unit is to need to carry out 64 bit parallel datas of descrambling, the output data of exclusive or tree is after delay process as the output data of delay unit；
The input data of exclusive or tree be 64 bit parallel datas descrambled and delay unit output 64 data, Input data is computed output data of rear obtained 64 data as exclusive or tree, and calculation formula is：
1-39 of output data are：
The 40-58 of output data is：
59-64 of output data are：
In above-mentioned formula, din (n) indicates that n-th of 64 bit parallel datas descrambled, dout (n) indicate solution Disturb 64 data exported with exclusive or tree n-th；
Xin_d (n) is expressed as the data of n-th of bit of descrambling delay unit output, and primary data is：xin_d (1)=xin_d (2)=... xin_d (6)=0；Xin_d (7) to xin_d (64) is low 58 of 029438798327338h, Middle xin_d (7) is a high position, and xin_d (58) is low level.
It is specifically described below
Exclusive or tree table is shown as in Fig. 2：
D is expressed as in Fig. 2：
Xin_d (1)=xin (1)
Xin_d (2)=xin (2)
Xin_d (3)=xin (3)
Xin_d (4)=xin (4)
Xin_d (5)=xin (5)
Xin_d (6)=xin (6)
Xin_d (7)=xin (7)
Xin_d (8)=xin (8)
Xin_d (9)=xin (9)
Xin_d (10)=xin (10)
Xin_d (11)=xin (11)
Xin_d (12)=xin (12)
Xin_d (13)=xin (13)
Xin_d (14)=xin (14)
Xin_d (15)=xin (15)
Xin_d (16)=xin (16)
Xin_d (17)=xin (17)
Xin_d (18)=xin (18)
Xin-d (19)=xin (19)
Xin-d (20)=xin (20)
Xin_d (21)=xin (21)
Xin_d (22)=xin (22)
Xin_d (23)=xin (23)
Xin_d (24)=xin (24)
Xin_d (25)=xin (25)
Xin_d (26)=xin (26)
Xin_d (27)=xin (27)
Xin_d (28)=xin (28)
Xin_d (29)=xin (29)
Xin_d (30)=xin (30)
Xin_d (31)=xin (31)
Xin_d (32)=xin (32)
Xin_d (33)=xin (33)
Xin_d (34)=xin (34)
Xin_d (35)=xin (35)
Xin_d (36)=xin (36)
Xin_d (37)=xin (37)
Xin_d (38)=xin (38)
Xin_d (39)=xin (39)
Xin_d (40)=xin (40)
Xin_d (41)=xin (41)
Xin_d (42)=xin (42)
Xin_d (43)=xin (43)
Xin_d (44)=xin (44)
Xin_d (45)=xin (45)
Xin_d (46)=xin (46)
Xin_d (47)=xin (47)
Xin_d (48)=xin (48)
Xin_d (49)=xin (49)
Xin_d (50)=xin (50)
Xin_d (51)=xin (51)
Xin_d (52)=xin (52)
Xin_d (53)=xin (53)
Xin_d (54)=xin (54)
Xin_d (55)=xin (55)
Xin_d (56)=xin (56)
Xin_d (57)=xin (57)
Xin_d (58)=xin (58)
Xin_d (59)=xin (59)
Xin_d (60)=xin (60)
Xin_d (61)=xin (61)
Xin_d (62)=xin (62)
Xin_d (63)=xin (63)
Xin_d (64)=xin (64)

Claims (1)

  1. 64 parallel-by-bits of 1.Fibre channel scramble the FPGA implementation method of descrambler, including scrambling realization method and descrambling are in fact Existing method；
    The scrambling realization method is to realize the parallel scrambling in 64 tunnels using an exclusive or tree and a delay cell, exclusive or tree Output is the output after scrambling；The input data of the delay unit is the output data of exclusive or tree, the output data of exclusive or tree As the output data of delay unit after delay process；
    The input data of exclusive or tree is 64 data for needing to carry out scrambled 64 bit parallel data and delay unit output, input Data are computed output data of rear obtained 64 data as exclusive or tree, and calculation formula is：
    1-39 of output data are： I=1~39；
    40-58 of output data are： I=40~58；
    59-64 of output data are： I=59~64；
    In above-mentioned formula, din (n) indicates to need to carry out n-th of scrambled 64 bit parallel data, and dout (n) indicates exclusive or tree N-th of 64 data of output；
    Xin_d (n) is expressed as the data of n-th of bit of time delay module output, and primary data is：Xin_d (1)=xin_d (2)=... xin_d (6)=0；Xin_d (7) to xin_d (64) is low 58 of 029438798327338h, wherein xin_d (7) For a high position, xin_d (58) is low；
    The output of the descrambling implementation method exclusive or tree is the output after descrambling；The input data of the delay unit be need into 64 bit parallel datas of row descrambling, the output data of exclusive or tree is after delay process as the output data of delay unit；
    The input data of exclusive or tree is 64 bit parallel datas descrambled and 64 data of delay unit output, input Data are computed output data of rear obtained 64 data as exclusive or tree, and calculation formula is：
    1-39 of output data are： I=1~39；
    The 40-58 of output data is：I=40~58；
    59-64 of output data are：I=59~64；
    In above-mentioned formula, din (n) indicates to need to carry out n-th of scrambled 64 bit parallel data, and dout (n) indicates exclusive or tree N-th of 64 data of output；
    Xin-d (n) is expressed as the data of n-th of bit of time delay module output, and primary data is：Xin_d (1)=xin_d (2)=... xin_d (6)=0；Xin_d (7) to xin_d (64) is low 58 of 029438798327338h, wherein xin_d（7) For a high position, xin_d (58) is low.
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