CN108630520B - Preparation method of dielectric layer and gate-last process device - Google Patents

Preparation method of dielectric layer and gate-last process device Download PDF

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CN108630520B
CN108630520B CN201710161307.3A CN201710161307A CN108630520B CN 108630520 B CN108630520 B CN 108630520B CN 201710161307 A CN201710161307 A CN 201710161307A CN 108630520 B CN108630520 B CN 108630520B
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dielectric layer
layer
substrate
gate
groove
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CN108630520A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a preparation method of a dielectric layer and a back gate process device, which comprises the steps of forming a continuous dielectric layer on a substrate with a groove, wherein the dielectric layer covers the surface of the substrate and the side wall and the bottom of the groove, and the thermal expansion coefficients of the dielectric layer and the substrate are different; and after the dielectric layer on the surface of the substrate is removed, an annealing process is performed. Because the dielectric layer on the surface of the substrate is removed before the annealing process is carried out, the dielectric layer in the groove independently exists, the situation that the stress generated by the dielectric layer due to the thermal expansion phenomenon cannot be released in the annealing process is avoided, and the dielectric layer can be prevented from generating cracks and even breaking.

Description

Preparation method of dielectric layer and gate-last process device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a dielectric layer and a back grid process device.
Background
In the field of semiconductor manufacturing, it is generally necessary to form a plurality of film layers on a substrate to form a semiconductor device, however, each film layer is not necessarily formed on a flat surface during the preparation process.
For example, when a recess is formed in the surface of a substrate, a dielectric layer subsequently deposited on the substrate may cover the surface of the substrate and cover the sidewalls and bottom of the recess. At this time, when the annealing process is performed on the dielectric layer to improve the quality of the dielectric layer, cracks often occur in the dielectric layer, and particularly, the dielectric layer in the corner region near the top of the groove is easily broken, so that the quality of the dielectric layer is adversely affected.
Disclosure of Invention
The invention aims to provide a preparation method of a dielectric layer, which aims to solve the problem that cracks and even fractures are easy to occur in the dielectric layer in the existing preparation process of the dielectric layer.
In order to solve the above technical problem, the present invention provides a method for preparing a dielectric layer, comprising:
providing a substrate, wherein a groove is formed on the substrate;
forming a continuous dielectric layer on the substrate, wherein the dielectric layer covers the surface of the substrate and the bottom and the side wall of the groove, and the thermal expansion coefficients of the dielectric layer and the substrate are different;
removing the dielectric layer on the surface of the substrate and reserving the dielectric layer in the groove; and
an annealing process is performed.
Optionally, the method for removing the dielectric layer on the surface of the substrate includes:
covering a sacrificial layer on the substrate, wherein the sacrificial layer covers the dielectric layer and fills the groove;
performing a planarization process on the substrate to expose the dielectric layer on the surface of the substrate and retain the sacrificial layer in the groove;
performing an etching process to remove the exposed dielectric layer on the surface of the substrate; and
and removing the sacrificial layer in the groove.
Optionally, the planarization process is a chemical mechanical polishing process.
Optionally, before performing the planarization process, the method further includes:
and coating a filling layer on the sacrificial layer, wherein the surface of the filling layer is smoother relative to the surface of the sacrificial layer.
Optionally, the planarization process includes:
and performing a back etching process on the filling layer and the sacrificial layer until the dielectric layer on the surface of the substrate is exposed, and reserving the sacrificial layer in the groove, wherein the difference of the etching rates of the filling layer and the sacrificial layer is not more than 10 nm/s.
Optionally, the material of the filling layer is photoresist.
Optionally, the sacrificial layer is made of photoresist, and at this time, the planarization process may adopt a back etching process.
Optionally, the sacrificial layer may be an antireflection layer or an organic insulating layer.
Optionally, the difference between the thermal expansion coefficients of the dielectric layer and the substrate is greater than 2.
Optionally, the substrate is a base; or the substrate comprises a base and a film layer formed on the base.
Another objective of the present invention is to provide a method for manufacturing a gate last process device, including:
providing a substrate, wherein an isolation layer is formed on the substrate, and a grid electrode groove is formed in the isolation layer;
forming a continuous dielectric layer on the substrate, wherein the dielectric layer covers the surface of the isolation layer and the bottom and the side wall of the grid groove, and the thermal expansion coefficients of the dielectric layer and the isolation layer are different;
removing the dielectric layer on the surface of the isolation layer and reserving the dielectric layer in the grid groove; and
and performing an annealing process, and forming a gate electrode in the gate trench.
Optionally, the method for forming the gate trench includes:
forming a pseudo gate structure on the substrate, and forming a side wall on the side wall of the pseudo gate structure;
covering the isolation layer on the pseudo gate structure, and carrying out a planarization process on the isolation material to expose the pseudo gate structure;
and removing the pseudo gate structure and reserving the side wall to form the gate groove.
Optionally, the sidewall is made of silicon nitride.
Optionally, after performing the annealing process and before forming the gate electrode, the method further includes:
and forming a barrier layer in the gate trench.
Optionally, the barrier layer is a tantalum nitride layer.
Optionally, the gate last process device is a FINFET device.
Optionally, the dielectric layer is a high-K dielectric layer, and the gate electrode is a metal gate electrode.
In the preparation method of the dielectric layer, before the annealing process is carried out on the dielectric layer, the dielectric layer on the surface of the substrate is preferentially removed, and the dielectric layer in the groove is kept, so that the dielectric layer in the groove is independent, and even if the expansion degree between the dielectric layer and the substrate is different when the annealing process is carried out subsequently to improve the quality of the dielectric layer, the stress generated by the thermal expansion of the dielectric layer can be released in time due to the small area of the dielectric layer on the substrate, and the stress in the dielectric layer is relieved to avoid the dielectric layer from being broken. In particular, the stress on the dielectric layer on the corner region at the top of the trench is greatly reduced, and the probability of fracture of the dielectric layer on the corner region is effectively reduced. In the preparation method provided by the invention, the quality of the dielectric layer can be ensured through an annealing process, and the problem that the dielectric layer cracks and even breaks in a high-temperature environment can be avoided. Therefore, when the preparation method is adopted to form a gate-last process device, the leakage current phenomenon of the formed device can be improved as no crack or fracture is generated in the gate dielectric layer.
Drawings
FIG. 1 is a schematic view of a structure formed with a dielectric layer;
FIG. 2 is a schematic flow chart illustrating a method for fabricating a dielectric layer according to an embodiment of the invention;
FIGS. 3 a-3 c-4 are schematic structural diagrams of a dielectric layer during its fabrication in a method for fabricating the dielectric layer according to an embodiment of the present invention;
FIGS. 3c-1 to 3c-3 are schematic structural diagrams of a dielectric layer on a surface of a substrate during a process of removing the dielectric layer in a method for preparing the dielectric layer according to an embodiment of the invention;
FIG. 4 is a schematic flow chart illustrating a method for fabricating a device with gate last process according to an embodiment of the present invention;
fig. 5a to 5d are schematic structural diagrams in the process of manufacturing a device in a gate last process according to an embodiment of the present invention.
Detailed Description
As described in the background, when a dielectric layer is formed and subjected to an annealing process to improve the quality of the dielectric layer, cracks are often generated in the dielectric layer, and particularly, the dielectric layer is easily broken at a corner region near the top of a groove. As shown in fig. 1, when the dielectric layer 11 is formed on the substrate 10, the surface of the substrate 10 and the bottom and the sidewall of the groove 12 are covered at the same time, so as to form a continuous dielectric layer 11. When the annealing process is performed on the continuous dielectric layer 11, the dielectric layer on the corner region 12a at the top of the groove 12 is particularly prone to crack or even break, so that the quality of the dielectric layer 11 is affected, and the performance of the formed whole device is further reduced.
For example, in forming a semiconductor device using a gate last process, a dielectric layer and a gate electrode are typically formed within a gate trench after removing a dummy gate structure to form the gate trench. When the dielectric layer in the gate trench is cracked or broken, the leakage current of the formed semiconductor device is liable to occur.
In order to solve the above technical problems, the inventors have conducted many studies and found that the above problems occur because the dielectric layer is easily broken in a high temperature environment due to a difference in thermal expansion coefficient between the substrate and the dielectric layer. Therefore, the invention provides a preparation method of a dielectric layer, which comprises the following steps:
providing a substrate, wherein a groove is formed on the substrate;
forming a continuous dielectric layer on the substrate, wherein the dielectric layer covers the surface of the substrate and the bottom and the side wall of the groove, and the thermal expansion coefficients of the dielectric layer and the substrate are different;
removing the dielectric layer on the surface of the substrate and reserving the dielectric layer in the groove; and the number of the first and second groups,
an annealing process is performed.
In the preparation method of the dielectric layer, the dielectric layer on the surface of the substrate is removed while the dielectric layer in the groove is reserved, so that in the subsequent annealing process, even if the expansion degree between the dielectric layer and the substrate is different, the dielectric layer is not continuous on the substrate and has a smaller area, so that the stress generated due to the difference of the expansion degree can be effectively relieved, the probability of breakage of the dielectric layer is reduced, and the quality of the dielectric layer is improved.
The backside illuminated CMOS image sensor according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a schematic flow chart of a method for manufacturing a dielectric layer according to an embodiment of the present invention, and fig. 3a to fig. 3c to fig. 4 are schematic structural diagrams of a dielectric layer according to an embodiment of the present invention during a manufacturing process thereof. The process of forming the dielectric layer in this embodiment will be described in detail below with reference to fig. 2 and fig. 3a to 3c to 4.
First, step S110 is executed, and referring to fig. 3a in particular, a substrate 100 is provided, wherein a trench 110 is formed on the substrate 100. It should be understood that the substrate 100 may be a base, and may also include a base and other layers formed on the base, that is, the trench 110 may be directly formed in the base, or may be located in other layers on the base. Further, the substrate may be a silicon substrate (Si) or a Silicon On Insulator (SOI).
Next, step S120 is executed, and referring specifically to fig. 3b, a continuous dielectric layer 120 is formed on the substrate 100, where the dielectric layer 120 covers the surface of the substrate 100 and the bottom and the sidewall of the trench 110, and the thermal expansion coefficients of the dielectric layer 120 and the substrate 100 are different. Preferably, the difference between the thermal expansion coefficients of the dielectric layer 120 and the substrate 100 is greater than 2. Further, the dielectric layer 120 may be formed by a chemical vapor deposition process, and the specific deposition method may refer to the existing method, which is not described herein again.
As described above, the substrate 100 herein includes a base, and may further include other film layers formed on the base. When the substrate is only a base, the trench is directly formed in the base, and the dielectric layer 120 covers the surface of the base and the sidewalls and bottom of the trench, at this time, the thermal expansion coefficients of the dielectric layer 120 and the substrate 100 are different, that is, the thermal expansion coefficients of the dielectric layer 120 and the base are different. For example, if the dielectric layer 120 is a high-K dielectric layer (with a cte of 5.8) and the substrate is a silicon substrate (with a cte of 2.5), the cte difference between the dielectric layer and the silicon substrate is 3.3. Of course, when the substrate 100 includes a base and further includes other film layers formed on the base, the trench is formed in the film layer on the base, and the dielectric layer covers the film layer and the bottom and the sidewall of the trench, at this time, the thermal expansion coefficients of the dielectric layer 120 and the substrate 100 are different, that is, the thermal expansion coefficients of the dielectric layer 120 and the film layer on the base are different.
Next, step S130 is performed, specifically referring to fig. 3c-4, to remove dielectric layer 120 on the surface of substrate 100 and leave dielectric layer 120 in trench 110. That is, a continuous dielectric layer 120 is prevented from being formed on the substrate, so as to relieve the stress in the dielectric layer 120.
The following steps may be referred to as a method for removing the dielectric layer on the surface of the substrate 100.
In a first step, referring to fig. 3c-1 in particular, a sacrificial layer 121 is covered on the substrate 100, and the sacrificial layer 121 covers the dielectric layer 120 and fills the trench 110. The material of the sacrificial layer 121 may be the same as that of an anti-reflection layer (BARC), such as SiON; alternatively, the sacrificial layer 121 may be an organic insulating layer (ODL); or, the sacrificial layer 121 is a photoresist, and because the photoresist has fluidity, a flat upper surface can be formed while filling the trench 110, which is beneficial to the subsequent planarization process.
In a second step, referring to fig. 3c-2 in particular, a planarization process is performed on the substrate 100 to expose the dielectric layer 120 on the surface of the substrate 100, and at this time, the sacrificial layer 121 in the trench 110 is remained.
In this embodiment, the planarization process is a chemical mechanical polishing process. That is, a chemical mechanical polishing process is performed on the sacrificial layer 121 until the dielectric layer 120 on the surface of the substrate 100 is exposed.
In addition, in other embodiments, other planarization processes, such as an etch-back process, may be used. Specifically, before the etching-back process is performed, a filling layer may be further coated on the sacrificial layer 121, and a surface of the filling layer is smoother than a surface of the sacrificial layer 121. Since the sacrificial layer 121 covers the surface of the substrate 100 and fills the trench 110 on the substrate, the surface of the sacrificial layer 121 formed finally may exhibit an uneven phenomenon, and thus, a flat surface can be formed by filling the recess on the surface of the sacrificial layer with the filling layer. The material of the filling layer is preferably a material having fluidity, such as photoresist. After the filling layer is formed, a back etching process is performed on the filling layer and the sacrificial layer 121 until the dielectric layer on the surface of the substrate 100 is exposed, and in the back etching process, the difference between the etching rates of the filling layer and the sacrificial layer is not more than 10 nm/s. Due to the fact that the etching rates of the filling layer and the sacrificial layer are close to each other, the filling layer and the sacrificial layer have approximately the same consumption in the same etching time, and therefore the dielectric layer on the substrate can be exposed in the same time period. Of course, it should be appreciated that if the sacrificial layer 121 covering the surface of the substrate 100 and filling the trench 110 is made of a material that is preferably flowable, and a flat surface can be formed, the etching back process on the sacrificial layer 121 is not required to be performed to prepare the filling layer.
Referring to fig. 3c-2, when planarization is performed by a mechanical polishing process, the height of the sacrificial layer 121 located in the trench 110 is the same as the height of the dielectric layer 120 located on the surface of the substrate 100, as shown in a structural diagram of a in fig. 3 c-2; when the etching-back process is used for planarization, the etching parameters may be controlled, for example, the etching time is prolonged, so that after the dielectric layer 120 on the surface of the substrate 100 is exposed, the sacrificial layer 121 in the trench 110 is continuously etched to further expose the dielectric layer 120 on the corner region 110a at the top of the trench, as shown in the structure diagram B in fig. 3c-2, and thus when the exposed dielectric layer is removed by the subsequent etching process, the dielectric layer on the corner region 110a at the top of the trench can be more easily removed.
And a third step, specifically referring to fig. 3c-3, of performing an etching process to remove the exposed dielectric layer 120 located on the substrate 100. At this time, since the dielectric layer in the trench 110 is covered with the sacrificial layer 121, the dielectric layer 120 in the trench 110 is retained, thereby avoiding forming a continuous dielectric layer on the substrate.
In a fourth step, specifically referring to fig. 3c-4, the sacrificial layer 121 in the trench 110 is removed to expose the dielectric layer 120 in the trench.
Next, step S140 is performed to perform an annealing process to improve the quality of the dielectric layer 120. For example, oxygen vacancies in the dielectric layer 120 may be reduced by the annealing process, which may improve the bias temperature instability of the formed device. Specifically, for NMOS, the reduction of oxygen vacancies in the dielectric layer is beneficial to improving the Positive Bias Temperature Instability (PBTI); for PMOS, it is beneficial to improve the Negative Bias Temperature Instability (NBTI).
The annealing process is, for example, a peak annealing process (Spike annealing), a Laser annealing (Laser annealing), or a rapid thermal annealing process. Specifically, when a peak annealing process is adopted, the temperature range is preferably 800-1000 ℃; when a Laser annealing (Laser annealing) or rapid thermal annealing process is used, the temperature range is preferably 950 ℃ to 1150 ℃. In the process of performing the annealing process, the substrate 100 and the dielectric layer 120 are located in a high temperature environment, so that the substrate 100 and the dielectric layer 120 generate a thermal expansion phenomenon, however, because the thermal expansion coefficients of the substrate 100 and the dielectric layer 120 are different, and further, the expansion degrees of the substrate 100 and the dielectric layer 120 are different, so that a larger stress is generated in the dielectric layer 120, and when the contact area between the dielectric layer 120 and the substrate 100 is larger, the stress generated in the dielectric layer 120 is gradually increased due to being unable to be effectively relieved, so that cracks occur in the dielectric layer 120, and particularly, the stress borne by the dielectric layer on the corner region 110a at the top of the trench 110 is larger, so that the cracks are more easily generated. Therefore, before the annealing process is carried out, the area of the dielectric layer is reduced, so that the stress release of the dielectric layer is facilitated, and the phenomenon of fracture of the dielectric layer is improved; moreover, by removing the dielectric layer on the surface of the substrate 100, the dielectric layer on the sidewall of the trench 110 and the dielectric layer on the substrate are prevented from being connected with each other, so that the stress applied to the dielectric layer 120 on the corner region 110a at the top of the trench is reduced, and the probability of the dielectric layer breaking is further reduced.
As described above, when a semiconductor device is formed by using a gate last process, a problem that a dielectric layer in a trench gate is cracked or even broken may occur. Therefore, the invention also provides a preparation method of the post-grid process device, which is characterized in that before the annealing process is carried out on the dielectric layer formed on the substrate, part of the dielectric layer is preferentially removed, and only the dielectric layer in the grid groove is reserved, so that the phenomenon that the dielectric layer is broken in the subsequent annealing process is avoided.
The following describes in detail a method for manufacturing a backgate process device provided by the present invention with reference to fig. 4 and fig. 5a to 5d, and taking the formation of a FINFET device as an example, where fig. 4 is a schematic flow diagram of the method for manufacturing the backgate process device in an embodiment of the present invention, and fig. 5a to 5d are schematic structural diagrams of the backgate process device in the manufacturing process of the backgate process device in an embodiment of the present invention.
First, step S210 is executed, and referring to fig. 5a specifically, a substrate 200 is provided, wherein an isolation layer 210 and a gate trench 220 are formed on the substrate 200, and the isolation layer 210 is located at the periphery of the sidewall of the gate trench 220. The material of the isolation layer 210 may be silicon oxide.
In this embodiment, taking the formation of a FINFET device as an example, a plurality of fins 211 are formed on the substrate 200, the gate trenches 220 are formed above and on both sides of the fins 211, and fig. 5a only shows the portion of the gate trenches 220 above the fins 211. For example, in the present embodiment, NMOS transistors are correspondingly formed on the fins of the NMOS region 200N, and PMOS transistors are correspondingly formed on the fins of the PMOS region.
Further, a source and a drain are respectively formed on the fin 211 at two sides of the gate trench 220, wherein the gate trench 220 is formed after the source and the drain are formed.
Specifically, the method for forming the gate trench 220 may refer to the following method: a first step of forming a dummy gate structure (not shown) on the substrate 200, wherein a sidewall 230 is formed on a sidewall of the dummy gate structure, and the sidewall 230 may be made of silicon nitride; a second step of forming the isolation layer 210 on the substrate 200, wherein the isolation layer 210 fills the periphery of the dummy gate structure and covers the dummy gate structure; a third step of performing a planarization process on the isolation layer 210 to expose the dummy gate structure; and a fourth step of removing the dummy gate structure and reserving the sidewall spacers 230 to form the gate trench 220.
Next, step S220 is executed, and referring specifically to fig. 5b, a continuous dielectric layer 240 is formed on the substrate 200, where the dielectric layer 240 covers the surface of the isolation layer 210 and the bottom and the sidewall of the gate trench 220, and the thermal expansion coefficients of the dielectric layer and the isolation layer are different. The dielectric layer in the gate trench 220 constitutes a gate dielectric layer. Preferably, the dielectric layer 240 may be formed using a chemical vapor deposition process, or may be formed using an atomic layer deposition process.
In this embodiment, the sidewall spacers 230 are disposed on the sidewalls of the gate trenches 220, that is, the formed dielectric layer 240 also covers the sidewall spacers 230, and similarly, when there is a difference between the thermal expansion coefficients of the sidewall spacers 230 and the dielectric layer 240, a certain stress is correspondingly generated in the dielectric layer 240 on the sidewall spacers 230 in the annealing process, and the stress is further accumulated on the corner regions at the tops of the gate trenches 220, so that the dielectric layer on the corner regions is easily broken.
Further, the dielectric layer 240 is a high-K dielectric layer. As device dimensions continue to scale, the thickness of the gate dielectric layer must be reduced to maintain the capacitance between the gate and the channel, while a thinner silicon dioxide layer will result in a higher tunneling current. At this time, under the influence of the tunneling effect, the gate leakage current begins to become a non-negligible problem, and the gate leakage current caused by the quantum tunneling effect weakens the channel control of the gate and increases the gate dielectric leakage current, which greatly affects the reliability of the device integration level. For this reason, high-K dielectric layers, at 32nm technology nodes and below, eliminate the problem of leakage current caused by tunneling due to their large physical thickness, and have been adopted on a large scale to replace silicon dioxide. Specifically, the high-K dielectric layer is, for example, hafnium oxide (HFO2), which has a suitable dielectric constant (15-25), and has good thermodynamic stability with silicon, and thus is one of the important materials currently replacing silicon dioxide.
Next, step S230 is executed, and referring to fig. 5c specifically, the dielectric layer 240 on the surface of the isolation layer 210 is removed, and the dielectric layer 240 in the gate trench 220 is remained. In this step, the method for removing the dielectric layer 240 on the surface of the isolation layer 210 may refer to the method in the above embodiment, that is: forming a sacrificial layer covering the isolation layer 210 and filling the gate trench 220 on the substrate 200; performing a planarization process on the sacrificial layer to expose the dielectric layer on the isolation layer 210; the dielectric layer on the isolation layer 210 is removed by an etching process. The planarization process can be a chemical mechanical polishing process or a back etching process.
Next, step S240, specifically referring to fig. 5d, is performed to perform an annealing process, and a gate electrode 250 is formed in the gate trench 220. Since the dielectric layer above the isolation layer 210 is removed before the annealing process is performed, the dielectric layer 240 in the gate trench 220 is independent, and thus, in a high-temperature environment of the annealing process, stress generated in the dielectric layer 240 can be released in time due to differences in thermal expansion degrees between the dielectric layer 240 and other film layers, thereby avoiding the problem of cracks or even breakage in the dielectric layer 240. In the correspondingly formed device, the phenomenon of leakage current caused by cracks in the dielectric layer 240 can be avoided, and the performance of the device is effectively improved.
As described above, the annealing process is beneficial to improve the quality of the dielectric layer 240, so as to effectively improve the performance of the formed device, specifically, the problem of device failure caused by temperature bias instability can be improved. For example, in the case of a PMOS transistor failure due to a Negative Bias Temperature Instability (NBTI) effect, a negative bias is applied to the gate of the PMOS transistor, and as the stress time increases, dangling bonds are generated at the interface between the dielectric layer and the substrate, thereby forming interface states, which impair the performance of the PMOS transistor (e.g., negative drift of threshold voltage), and as the stress time accumulates, the PMOS transistor failure is caused. Therefore, after the dielectric layer is subjected to the annealing process, dangling bonds at the interface can be reduced, the interface state is improved, and therefore the negative bias temperature instability of the PMOS transistor can be improved. Accordingly, for positive bias temperature instability (NBTI), the annealing process can reduce oxygen vacancies in the dielectric layer, thereby improving the positive bias temperature instability of the NMOS transistor.
In an alternative scheme, before forming the gate electrode 250, the method further includes: a barrier layer is formed within the gate trench 220. Referring to fig. 5d specifically, a blocking layer 260 is formed in the gate trench 220 where the dielectric layer 240 is formed, and the blocking layer 260 may be used to protect the dielectric layer 240 and prevent damage to the dielectric layer 240 when the gate electrode layer 250 is formed subsequently. Preferably, the material of the blocking layer 260 may also adopt a work function material, so that the work function of a subsequently formed gate structure may also be adjusted. Specifically, the material of the barrier layer 260 is, for example, tantalum nitride (TaN), titanium nitride (TiN), or the like. After the formation of the blocking layer 260, a gate electrode 250 is formed in the gate trench 220, and further, the gate electrode 250 is a metal gate.
In the process of manufacturing the gate structure by adopting the gate-last process, before the gate structure is formed, the substrate is preferentially subjected to the ion implantation process of the source/drain region and the subsequent high-temperature annealing process, and then the gate structure is formed, so that the gate structure can be prevented from suffering from the high-temperature process in the annealing of the source/drain region. Therefore, compared with the front gate process, the back gate process can effectively improve the problem that the electrical performance of the formed device drifts.
In summary, in the method for forming the dielectric layer provided by the present invention, before the annealing process is performed on the dielectric layer, the dielectric layer on the substrate surface is preferentially removed while the dielectric layer in the trench is retained, so that the dielectric layer in the trench is independent, and thus when the annealing process is performed subsequently to improve the quality of the dielectric layer, the stress generated by the dielectric layer due to thermal expansion can be released in time, thereby effectively relieving the stress in the dielectric layer and reducing the probability of breakage of the dielectric layer. Furthermore, when the gate dielectric layer is formed by adopting a gate-last process, the leakage current phenomenon of the formed device can be improved because no crack or fracture is generated in the gate dielectric layer.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (19)

1. A preparation method of a dielectric layer is characterized by comprising the following steps:
providing a substrate, wherein a groove is formed on the substrate;
forming a continuous dielectric layer on the substrate, wherein the dielectric layer covers the surface of the substrate and the bottom and the side wall of the groove, and the thermal expansion coefficients of the dielectric layer and the substrate are different;
removing the dielectric layer on the surface of the substrate and reserving the dielectric layer in the groove, including: covering a sacrificial layer on the substrate, wherein the sacrificial layer covers the dielectric layer and fills the groove; performing a planarization process to expose the dielectric layer on the surface of the substrate, retain the sacrificial layer in the trench, and reduce the height of the sacrificial layer retained in the trench to expose the dielectric layer on the corner region at the top of the trench; performing an etching process to remove the exposed dielectric layers on the surface of the substrate and the corner region; and removing the sacrificial layer in the groove; and the number of the first and second groups,
an annealing process is performed.
2. The method of claim 1, further comprising, prior to performing the planarization process:
and coating a filling layer on the sacrificial layer, wherein the surface of the filling layer is smoother relative to the surface of the sacrificial layer.
3. The method of claim 2, wherein the planarization process comprises:
and performing a back etching process on the filling layer and the sacrificial layer until the dielectric layer on the surface of the substrate is exposed, and reserving the sacrificial layer in the groove, wherein the difference of the etching rates of the filling layer and the sacrificial layer is not more than 10 nm/s.
4. The method for preparing a dielectric layer according to claim 2, wherein the material of the filling layer is photoresist.
5. The method for preparing a dielectric layer according to claim 1, wherein the sacrificial layer is made of photoresist.
6. The method of claim 5, wherein the planarization process is a etchback process.
7. The method of claim 1, wherein the sacrificial layer is an anti-reflective layer.
8. The method of claim 1, wherein the sacrificial layer is an organic insulating layer.
9. The method of claim 1, wherein the difference in the coefficients of thermal expansion of the dielectric layer and the substrate is greater than 2.
10. The method of claim 1, wherein the substrate is a base.
11. The method of claim 1, wherein the substrate comprises a base and a film layer formed on the base.
12. A method for preparing a gate last process device is characterized by comprising the following steps:
providing a substrate, wherein an isolation layer is formed on the substrate, and a grid electrode groove is formed in the isolation layer;
forming a continuous dielectric layer on the substrate, wherein the dielectric layer covers the surface of the isolation layer and the bottom and the side wall of the grid groove, and the thermal expansion coefficients of the dielectric layer and the isolation layer are different;
removing the dielectric layer on the surface of the isolation layer and reserving the dielectric layer in the gate trench, including: covering a sacrificial layer on the isolation layer, wherein the sacrificial layer covers the dielectric layer and fills the grid groove; performing a planarization process to expose the dielectric layer on the surface of the isolation layer, retain the sacrificial layer in the gate trench, and reduce the height of the sacrificial layer retained in the gate trench to expose the dielectric layer on the corner region at the top of the gate trench; performing an etching process to remove the exposed dielectric layers on the surface of the isolation layer and the corner region; removing the sacrificial layer in the grid groove; and the number of the first and second groups,
and performing an annealing process, and forming a gate electrode in the gate trench.
13. The method of fabricating a gate last device of claim 12, wherein the method of forming the gate trench comprises:
forming a pseudo gate structure on the substrate, and forming a side wall on the side wall of the pseudo gate structure;
covering the isolation layer on the pseudo gate structure, and carrying out a planarization process on the isolation layer to expose the pseudo gate structure;
and removing the pseudo gate structure and reserving the side wall to form the gate groove.
14. The method of claim 13, wherein the sidewall spacers are made of silicon nitride.
15. The method of fabricating a gate last device of claim 12, further comprising, after performing the annealing process and before forming the gate electrode:
and forming a barrier layer in the gate trench.
16. The method of fabricating a back gate process device of claim 15, wherein said barrier layer is a tantalum nitride layer.
17. The method of making a back gate process device of claim 12, wherein the back gate process device is a FINFET device.
18. The method of making a back-gate process device of claim 12, wherein the dielectric layer is a high-K dielectric layer.
19. The method of making a gate last device of claim 12, wherein the gate electrode is a metal gate.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020102848A1 (en) * 2000-12-07 2002-08-01 Advanced Micro Devices, Inc. Damascene nisi metal gate high-k transistor
CN102347227A (en) * 2010-07-30 2012-02-08 中芯国际集成电路制造(上海)有限公司 Metal gate formation method
CN102956542A (en) * 2011-08-19 2013-03-06 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020102848A1 (en) * 2000-12-07 2002-08-01 Advanced Micro Devices, Inc. Damascene nisi metal gate high-k transistor
CN102347227A (en) * 2010-07-30 2012-02-08 中芯国际集成电路制造(上海)有限公司 Metal gate formation method
CN102956542A (en) * 2011-08-19 2013-03-06 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor devices

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