CN108616467B - Continuous time adaptive equalizer - Google Patents
Continuous time adaptive equalizer Download PDFInfo
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- CN108616467B CN108616467B CN201611139643.XA CN201611139643A CN108616467B CN 108616467 B CN108616467 B CN 108616467B CN 201611139643 A CN201611139643 A CN 201611139643A CN 108616467 B CN108616467 B CN 108616467B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03159—Arrangements for removing intersymbol interference operating in the frequency domain
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03178—Arrangements involving sequence estimation techniques
- H04L25/03184—Details concerning the metric
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Abstract
The invention provides a continuous time self-adaptive equalizer, which comprises an equalizing filter circuit, a limiting amplifier circuit, a high-pass filter circuit, a rectifying circuit, an error amplifier circuit and a power detection circuit and is characterized by also comprising a power detection circuit PD, wherein the output end of the equalizing filter is connected with the power detection circuit PD, the output end of the power detection circuit PD is connected with a gain control end (gctrl end) of the equalizing filter, and the equalizing filter adjusts the amplification gain of the low-frequency part of an input signal of the equalizing filter according to the detection result of the power detection circuit PD on the low-frequency power. The invention can improve the quality of received signals, does not need clock signals, has high reliability, can be applied to bus receivers such as Ethernet, 1393 and the like, and improves the correctness of data reception.
Description
Technical Field
The invention belongs to the electronic circuit design technology and relates to a high-speed signal continuous time self-adaptive equalizer. The invention is applicable to high-speed bus receivers.
Background
In a wired communication system, the channel exhibits a low-pass characteristic due to non-ideal factors such as skin effect and dielectric loss, and when the data rate far exceeds the channel bandwidth, intersymbol interference (ISI) is caused, resulting in a reduction in the pulse width and amplitude of the currently received bit. The non-ideal nature of the communication channel not only causes inter-symbol interference (ISI), but also severely limits transmission rate and transmission distance. Therefore, in order to increase the transmission rate or extend the transmission distance of the communication system, the receiving end of the communication system needs to perform equalization compensation on the received signal to suppress the influence of the inter-symbol interference.
In an actual wired communication system, the exact channel characteristics are not known in advance. Therefore, the pre-designed equalizer is not in an optimal state. For example, the length of the via may vary from application to application, or the loss profile of the via may vary from PCB manufacturing process to PCB manufacturing process. For the above reasons, the compensation coefficients of the equalizer need to be set adaptively.
A block diagram of a conventional Adaptive Equalizer is disclosed in the Jong-Sang Choi, Moon-Sang Hwang, Deog-Kyon Jeong, "A0.18-umCMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain control method," IEEE J.Solid-State Circuits, vol.39, pp.419-425, March 2004. paper. Although the typical adaptive equalization structure can implement the adaptive equalization function, it has two disadvantages: firstly, the power of the low-frequency signal cannot be adjusted; secondly, the self-adaptive adjusting range is narrow.
Disclosure of Invention
The invention provides a continuous time self-adaptive equalizer which can better overcome the defects of a typical structure and adjust the power of a low-frequency signal, thereby compensating the non-ideal characteristics of a channel, inhibiting the influence of intersymbol interference, improving the quality of a received signal, ensuring the correctness of bus receiving and reducing the error rate.
The invention adds a power detection circuit at the output of the equalizing filter, the power detection circuit is used for detecting the low-frequency power of the output signal of the equalizing filter, and the equalizing filter adjusts the amplification gain of the low-frequency part of the input signal of the equalizing filter according to the detection result of the low-frequency power.
The specific technical solution of the invention is as follows:
a continuous time self-adaptive equalizer comprises an equalizing filter, a power detection circuit PD, a limiting amplifier, two high-pass filters, a rectifying circuit and an error amplifier, wherein an in port of the equalizing filter receives an input signal Din, an output end of the equalizing filter is connected with input ends of the power detection circuit PD, a first high-pass filter and a limiting amplifier LA, an output end of the first high-pass filter is connected with a negative input end of the rectifying circuit, an output end of the limiting amplifier LA is connected with an input end of a second high-pass filter, an output end of the second high-pass filter is connected with a positive input end of the rectifying circuit, a negative output end of the rectifying circuit is connected with a negative end of the error amplifier EA, a positive output end of the rectifying circuit is connected with a positive end of the error amplifier, an output end of the error amplifier is connected with a zero point control end (zctrl end), the power detection circuit PD is characterized by further comprising a power detection circuit PD, the output end of the equalization filter is connected with the power detection circuit PD, the output end of the power detection circuit PD is connected with a gain control end (gctrl end) of the equalization filter, and the equalization filter adjusts the amplification gain of the low-frequency part of the input signal of the equalization filter according to the detection result of the power detection circuit PD on the low-frequency power.
The power detection circuit PD detects the power of the input signal, compares the detection result with a set power threshold, integrates the difference between the detection result and the power threshold, and outputs the integration result to the gain control terminal (gctrl terminal) of the equalizer filter. The equalizing filter adjusts the zero and pole frequencies of the equalizing filter according to the signal received by the gain control end (gctrl end), thereby realizing the amplification gain adjustment of the low-frequency part of the input signal of the equalizing filter.
The power detection circuit comprises: NMOS transistors M1, M2, M5, M6, M9, M10, M13, M14, M16, M17 and M19, PMOS transistors M3, M4, M7, M8, M11, M12, M15 and M18, integration capacitors CintWherein, in the step (A),
the input vip is connected to the grid electrode of the M1 tube, the input vin is connected to the grid electrode of the M2 tube, the source electrodes of the M1 tube and the M2 tube are connected to the ground through the current source 10, the drain electrode of the M1 tube is connected to the grid electrode and the drain electrode of the M3 tube, the drain electrode of the M2 tube is connected to the grid electrode and the drain electrode of the M4 tube, and the source electrodes of the M3 tube and the M4 tube are connected to the power supply VDDM7 pipe sourceA gate of the M7 tube is connected to a drain of the M4 tube, a drain of the M7 tube is connected to a drain of the M5 tube, a gate of the M5 tube is connected to the gate and the drain of the M5 tube, a source of the M5 tube is connected to ground, a drain of the M5 tube is connected to the drain of the M5 tube, a gate of the M5 tube is connected to the drain of the M5 tube, a source of the M5 tube is connected to the power supply, a source of the M5 tube is connected to the drain of the M5 tube, a drain of the M5 tube is connected to the M5 tube, and a drain of the M5 tube is connected to the M5 tube. The grid of the M14 tube is connected to the grid of the M15 tube, the source of the M14 tube is connected to the drain of the M13 tube, the grid of the M13 tube is connected to the drain of the M11 tube, the source of the M13 tube is connected to ground, the source of the M18 tube is connected to the power supply, the grid of the M18 tube is connected to the drain of the M11 tube, the drain of the M18 tube is connected to the drain of the M17 tube, the grid of the M17 tube is connected to the grid of the M18 tube, the source of the M17 tube is connected to the drain of the M16 tube, the grid of the M16 tube is connected to the drain of the M7 tube, the source of the M16 tube is connected to ground, the source of the M19 tube is connected to ground, the grid of the M19 tube is connected to the drains of the M15 and M18 tubes, the drain of the M19 tube is connected to the output end of the current source 9intIs connected to the output vo terminal, a capacitor CintIs connected to ground.
The invention has the advantages that:
1. the invention provides a continuous time self-adaptive equalizer, which is additionally provided with a power detection circuit, and an equalization filter adjusts the amplification gain of a low-frequency part of an input signal of the equalization filter according to a low-frequency power detection result. The gain adjustment of the low-frequency signal can be realized, and the self-adaptive adjustment range is enlarged, so that the compensation effect on the signal is better, and the quality of the received signal is effectively improved.
2. The power detection circuit provided by the invention can effectively detect the power of the signal, and the power fixed value is built in the power detection circuit, so that the power detection circuit is not required to be provided externally, and the number of circuit ports is not increased.
Drawings
FIG. 1 is a block diagram of a conventional adaptive equalizer architecture
FIG. 2 is a block diagram of a method implementation architecture of the present invention;
fig. 3 is a circuit diagram of the power detection circuit PD in the present invention;
1 is an equalizing filter, 2 is a power detection circuit, 3 is a limiting amplifier, 4 and 5 are high-pass filters, 6 is a rectifying circuit, 7 is an error amplifier, Din is an input signal end, Dout is an output signal end, 8, 9 and 10 are respectively a first current source, a second current source and a third current source,
m1, M2, M5, M6, M9, M10, M13, M14, M16, M17 and M19 are NMOS tubes, M3, M4, M7, M8, M11, M12, M15 and M18 are PMOS tubes, C is a metal oxide semiconductor (PMOS) tubeintIs an integrating capacitance, VDDIs a power source.
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and the specific embodiments.
A continuous time self-adaptive equalizer comprises an equalizing filter, a power detection circuit PD, a limiting amplifier, two high-pass filters, a rectifying circuit and an error amplifier, wherein an in port of the equalizing filter receives an input signal Din, an output end of the equalizing filter is connected with input ends of the power detection circuit PD, a first high-pass filter and a limiting amplifier LA, an output end of the first high-pass filter is connected with a negative input end of the rectifying circuit, an output end of the limiting amplifier LA is connected with an input end of a second high-pass filter, an output end of the second high-pass filter is connected with a positive input end of the rectifying circuit, a negative output end of the rectifying circuit is connected with a negative end of the error amplifier EA, a positive output end of the rectifying circuit is connected with a positive end of the error amplifier, an output end of the error amplifier is connected with a zero point control end (zctrl end), the power detection circuit PD is characterized by further comprising a power detection circuit PD, the output end of the equalization filter is connected with the power detection circuit PD, the output end of the power detection circuit PD is connected with a gain control end (gctrl end) of the equalization filter, and the equalization filter adjusts the amplification gain of the low-frequency part of the input signal of the equalization filter according to the detection result of the power detection circuit PD on the low-frequency power.
The power detection circuit PD detects the power of the input signal, compares the detection result with a set power threshold, integrates the difference between the detection result and the power threshold, and outputs the integration result to the gain control terminal (gctrl terminal) of the equalizer filter. The equalizing filter adjusts the zero and pole frequencies of the equalizing filter according to the signal received by the gain control end (gctrl end), thereby realizing the amplification gain adjustment of the low-frequency part of the input signal of the equalizing filter.
The invention provides a power detection circuit, which comprises the following working processes:
example 1
The number ratio of the M7 tubes and the M8 tubes is set,
number of M7 tubes: the number of M8 tubes is 4: 1
M of M7 tube was set to 4, and M of M8 tube was set to 1.
The number ratio of the M11 tubes and the M12 tubes is set,
number of M11 tubes: the number of M12 tubes is 4: 1
M of M11 tube was set to 4, and M of M12 tube was set to 1.
The current value of the current source 8 is set to 20mA, the current value of the current source 9 is set to 15mA, and the current value of the current source 10 is set to 0.5 mA.
Example 2
The number ratio of the M7 tubes and the M8 tubes is set,
number of M7 tubes: the number of M8 tubes is 6: 1
M6 for M7 tube and M1 for M8 tube.
The number ratio of the M11 tubes and the M12 tubes is set,
number of M11 tubes: the number of M12 tubes is 6: 1
M6 for M11 tube and M1 for M12 tube.
Current value setting of current sources 8 and 9
The current value of the current source 8 is set to 20mA, the current value of the current source 9 is set to 15mA, and the current value of the current source 10 is set to 0.5 mA.
As can be seen from examples 1 and 2, the internal self-established power threshold is realized by setting the quantity ratio of the differential pair transistors, external supply is not needed, and the quantity of circuit ports is not increased
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (2)
1. A continuous-time adaptive equalizer, characterized by: the device comprises an equalizing filter, a power detection circuit PD, a limiting amplifier, two high-pass filters, a rectifying circuit and an error amplifier, wherein an in port of the equalizing filter receives an input signal Din, input ends of a first high-pass filter and a limiting amplifier LA are connected, an output end of the first high-pass filter is connected with a negative input end of the rectifying circuit, an output end of the limiting amplifier LA is connected with an input end of a second high-pass filter, an output end of the second high-pass filter is connected with a positive input end of the rectifying circuit, a negative output end of the rectifying circuit is connected with a negative end of the error amplifier EA, a positive output end of the rectifying circuit is connected with a positive end of the error amplifier, an output end of the error amplifier is connected with a zero control end (zctrl end) of the equalizing filter, an output end of the limiting amplifier is connected with a data output end, the output terminal of the power detection circuit PD is connected to the gain control terminal (gctrl terminal) of the equalization filter, and the equalization filter applies the low frequency part of the input signal of the equalization filter according to the detection result of the power detection circuit PD on the low frequency powerThe amplification gain of (a) is adjusted, the power detection circuit comprising: NMOS transistors M1, M2, M5, M6, M9, M10, M13, M14, M16, M17 and M19, PMOS transistors M3, M4, M7, M8, M11, M12, M15 and M18, integration capacitors CintWherein, in the step (A),
the input vip is connected to the grid electrode of the M1 tube, the input vin is connected to the grid electrode of the M2 tube, the source electrodes of the M1 tube and the M2 tube are connected to the ground through the current source 10, the drain electrode of the M1 tube is connected to the grid electrode and the drain electrode of the M3 tube, the drain electrode of the M2 tube is connected to the grid electrode and the drain electrode of the M4 tube, and the source electrodes of the M3 tube and the M4 tube are connected to the power supply VDDA source of the M7 tube is connected to a power supply, a gate of the M7 tube is connected to a drain of the M7 tube, a drain of the M7 tube is connected to a drain of the M7 tube, a gate of the M7 tube is connected to the gate and the drain of the M7 tube, a source of the M7 tube is connected to ground, a drain of the M7 tube is connected to the drain of the M7 tube, a gate of the M7 tube is connected to the drain of the M7 tube, a source of the M7 tube is connected to the drain of the M7 tube, a drain of the M36, the grid of the M14 tube is connected to the grid of the M15 tube, the source of the M14 tube is connected to the drain of the M13 tube, the grid of the M13 tube is connected to the drain of the M11 tube, the source of the M13 tube is connected to ground, the source of the M18 tube is connected to the power supply, the grid of the M18 tube is connected to the drain of the M11 tube, the drain of the M18 tube is connected to the drain of the M17 tube, the grid of the M17 tube is connected to the grid of the M18 tube, the source of the M17 tube is connected to the drain of the M16 tube, the grid of the M16 tube is connected to the drain of the M7 tube, the source of the M16 tube is connected to ground, the source of the M19 tube is connected to ground, the grid of the M19 tube is connected to the drains of the M15 and M18 tubes, the drain of the M19 tube is connected to the output end of the current source 9intUpper pole plate connection ofTo the output vo terminal, capacitor CintIs connected to the ground and is,
setting the number of M7 tubes: the number of M8 tubes is 6: 1, and number of M11 tubes: the number of M12 tubes is 6: 1, setting the current value of a current source 8 to be 20mA, the current value of a current source 9 to be 15mA, and the current value of a current source 10 to be 0.5 mA;
or setting the number of M7 tubes: the number of M8 tubes is 4: 1, and number of M11 tubes: the number of M12 tubes is 4: 1, setting the current value of a current source 8 to be 20mA, the current value of a current source 9 to be 15mA, and the current value of a current source 10 to be 0.5 mA;
therefore, the power threshold is automatically established in the circuit through the number ratio of the PMOS pair tubes, and the power threshold does not need to be supplied from the outside.
2. The continuous-time adaptive equalizer according to claim 1, wherein the power detection circuit PD detects the power of the input signal, compares the detection result with a set power threshold, performs integration processing on the difference between the detection result and the set power threshold, and outputs the integration processing result to the gain control terminal (gctrl terminal) of the equalizer filter, and the equalizer filter adjusts the frequencies of the zero and the pole of the equalizer filter according to the signal received by the gain control terminal (gctrl terminal), thereby realizing the amplification gain adjustment of the low-frequency part of the input signal of the equalizer filter.
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