CN108598159B - Insulated gate bipolar transistor with wide band gap semiconductor material/silicon semiconductor material heterojunction and manufacturing method thereof - Google Patents
Insulated gate bipolar transistor with wide band gap semiconductor material/silicon semiconductor material heterojunction and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides an Insulated Gate Bipolar Transistor (IGBT) with a wide band gap semiconductor material/silicon semiconductor material heterojunction and a manufacturing method thereof, wherein the heterojunction IGBT device mainly combines the wide band gap material with the silicon material to form a heterojunction, an N + type wide band gap semiconductor material buffer layer with higher doping concentration is formed on a P + type substrate of the wide band gap semiconductor material in an epitaxial growth mode, an N type wide band gap semiconductor material epitaxial layer with lower doping concentration is further formed on the N + type wide band gap buffer layer, then the N type wide band gap semiconductor epitaxial layer is taken as a base to be combined with an N type silicon semiconductor layer by utilizing a crystal bonding technology, and an active region of the IGBT device is formed by adopting a silicon mature process. The invention can obviously improve the breakdown voltage of the IGBT and improve the performance of the device.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to an insulated gate bipolar transistor.
Background
The power semiconductor device is a high-power electronic device mainly used for an electric energy conversion and control circuit of power equipment. With the rapid development of power electronic technology, power semiconductor devices have been widely used in modern industrial control and defense equipment. insulated-Gate Bipolar transistors (IGBTs) are commonly used in power integrated circuits and power integrated systems due to their low on-resistance, reduced saturation voltage, high current handling capability, low loss, high input impedance, low drive power, fast switching speed, and other characteristics. In recent years, the characteristic optimization of the IGBT device is mainly to research the mature super junction process to realize the IGBT device with the super junction.
Disclosure of Invention
The invention provides a novel insulated gate bipolar transistor power device, and aims to further improve the breakdown voltage of an IGBT and improve the performance of the device.
The technical scheme of the invention is as follows:
the insulated gate bipolar transistor with the wide band gap semiconductor material/silicon semiconductor material heterojunction comprises:
a P + type substrate of wide bandgap semiconductor material;
an N + type buffer layer made of wide band gap semiconductor materials is epitaxially grown on the upper surface of the P + type substrate and is marked as an N + type wide band gap buffer layer;
epitaxially growing an N-type epitaxial layer made of a wide band gap semiconductor material on the upper surface of the N + type wide band gap buffer layer, and marking as the N-type wide band gap epitaxial layer;
combining an N-type bonding layer of a silicon material on the upper surface of the N-type wide band gap epitaxial layer by utilizing a crystal bonding technology, and marking as the N-type silicon bonding layer;
forming two P-type base regions in the left end region and the right end region of the upper part of the N-type silicon bonding layer respectively; a channel and an N + type source region are formed in each P type base region and are contacted with a P + channel substrate, wherein the N + type source region is adjacent to the channel, and the P + channel substrate contact is positioned at the far end of the channel relative to the N + type source region; the longitudinal boundary of the P-type base region extends into the wide band gap N-type epitaxial layer, namely a PN junction formed by the P-type base region and the N-type wide band gap epitaxial layer is positioned in the N-type wide band gap epitaxial layer, and the channel is still positioned in the N-type silicon bonding layer;
the gate oxide layer is positioned between the two P-type base regions and on the upper surfaces of part of the N + type source region and the corresponding channel, and the middle part of the gate oxide layer covers the upper surface of the N-type silicon bonding layer;
the grid is positioned inside the grid oxide layer;
two source electrodes covering the upper surface of the region where the corresponding P + channel substrate contact is connected with the N + type source region, wherein the two source electrodes are connected together;
the drain electrode is positioned on the lower surface of the P + type substrate;
the thickness and the doping concentration of the N-type wide band gap epitaxial layer are determined by the voltage-resistant requirement of the device, and the doping concentration of the N-type wide band gap epitaxial layer is lower than the doping concentrations of the N + type wide band gap buffer layer and the P + type substrate.
On the basis of the scheme, the invention further optimizes the following steps:
the wide band gap semiconductor material adopts silicon carbide or gallium nitride.
The doping concentration of the N-type wide band gap epitaxial layer is determined according to the designed breakdown voltage, the difference value of the N-type wide band gap epitaxial layer and the P + type substrate is about 4-6 orders of magnitude, and the N-type wide band gap epitaxial layer is 2-4 orders of magnitude smaller than the doping concentration of the N + type wide band gap buffer layer.
The thickness of the N-type silicon bonding layer is determined according to the design of a device, the typical value is about 1-5 microns, and the part of the P-type base region extending into the wide-band-gap N-type epitaxial layer is not more than two thirds.
The doping concentration of the N-type wide band gap epitaxial layer is (10)14-1016)cm-3。
Setting the doping concentration of the P + type substrate to 1 × 1020cm-3The doping concentration of the N + type wide band gap buffer layer is 1 multiplied by 1018cm-3(ii) a Then:
when the voltage withstand requirement is 1120V, the thickness of the N type wide band gap epitaxial layer is 10 microns, and the doping concentration of the N type wide band gap epitaxial layer and the N type silicon bonding layer is 2 multiplied by 1015cm-3；
When the withstand voltage requirement is 1570V, the thickness of the N type wide band gap epitaxial layer is 17 microns, and the doping concentration of the N type wide band gap epitaxial layer and the N type silicon bonding layer is 2 multiplied by 1015cm-3；
When the voltage withstanding requirement is 1650V, the thickness of the N-type wide band gap epitaxial layer is 17 μm, and the doping concentration of the N-type wide band gap epitaxial layer and the N-type silicon bonding layer is 1 × 1015cm-3。
The P-type base region, the N + type source region of the P-type base region, the P + channel substrate contact and the channel are formed on the upper portion of the N-type silicon bonding layer through ion implantation and double diffusion technologies.
The grid is a polysilicon grid, the source electrode is a metalized source electrode, and the drain electrode is a metalized drain electrode.
A method of fabricating the above-described insulated gate bipolar transistor having a wide bandgap semiconductor material/silicon semiconductor material heterojunction, comprising the steps of:
(1) preparing a P + type wide band gap semiconductor material as a P + type substrate;
(2) epitaxially growing an N + type wide band gap buffer layer on the upper surface of the P + type substrate of the wide band gap semiconductor material;
(3) epitaxially growing an N-type wide band gap epitaxial layer on the upper surface of the N + type wide band gap buffer layer;
(4) combining an N-type silicon bonding layer on the upper surface of the N-type wide band gap epitaxial layer by a room-temperature crystal bonding technology, and performing high-temperature annealing after bonding;
(5) oxidizing the upper surface of the N-type silicon bonding layer to form a silicon dioxide film, and etching the silicon dioxide film by adopting an anisotropic etching method under the protection of a mask to form an active region;
(6) further forming a gate oxide layer on the upper surface of the N-type silicon bonding layer, depositing polycrystalline silicon, etching the polycrystalline silicon and the gate oxide layer, and removing parts positioned at the left end region and the right end region to form a polycrystalline silicon grid;
(7) forming a P-type base region in the left end region and the right end region of the upper part of the N-type silicon bonding layer through boron ion injection and double diffusion technology, and ensuring that the longitudinal boundary of the P-type base region extends into the wide band gap N-type epitaxial layer in the process of well pushing, wherein the junction depth finally depends on the temperature and time of a well pushing, namely the PN junction formed by the P-type base region and the N-type wide band gap epitaxial layer is positioned in the N-type wide band gap epitaxial layer, and the channel is still positioned in the N-type silicon bonding layer;
(8) forming a heavily doped N + source region to be contacted with the P + channel substrate in an ion implantation mode, forming a corresponding channel by adopting a double diffusion technology, and shortening annealing time as much as possible after implantation;
(9) depositing a silicon oxide film on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
(10) depositing metal in the contact hole and etching to remove the rest silicon oxide film on the periphery to form a source electrode, and connecting the two source electrodes together;
(11) and forming a metalized drain on the lower surface of the P + type substrate.
The technical scheme of the invention has the following beneficial effects:
the invention combines a wide band gap material and a silicon material to form a heterojunction, firstly forms an N + type wide band gap buffer layer with higher doping concentration on the upper surface of a wide band gap P + type substrate material, further forms an N type wide band gap epitaxial layer with lower doping concentration on the upper surface of the N + type wide band gap buffer layer, then combines the N type wide band gap epitaxial layer with an N type silicon bonding layer by using a crystal bonding technology on the basis of the N type wide band gap epitaxial layer, and adopts a silicon mature process to manufacture a device active region on the silicon bonding layer. The high electric field peak generated by the P-type base region/N-type wide band gap epitaxial layer junction is positioned in the wide band gap material, the characteristic of the high critical breakdown electric field of the wide band gap material is utilized, the high electric field peak of the IGBT device near the gate is introduced into the wide band gap semiconductor material, the longitudinal electric field peak of the device is raised, the device can bear higher breakdown voltage, the limitation that the traditional silicon-based IGBT breakdown voltage is limited by the critical breakdown electric field of a single silicon material is broken through, and the breakdown voltage is greatly improved compared with the traditional IGBT under the condition that the thickness of the drift region of the device is the same and the concentration of the drift region of the; meanwhile, the high heat conductivity of the wide-band-gap material is beneficial to heat dissipation of the device, and the performance of the device is effectively improved.
Drawings
FIGS. 1-11 are schematic device fabrication flow diagrams of one embodiment of the present invention;
fig. 12 is a schematic structural diagram of an IGBT device according to an embodiment of the present invention.
Wherein, 101-source electrode; 102-a gate oxide layer; 103-a gate; 104-source; 105-P + channel substrate contacts (P + type body regions); a 106-N + type source region; 107-P type base region; 801-P + type substrate of wide band gap material; an 802-N + type wide band gap buffer layer; 803-N type wide band gap epitaxial layer; 804-an N-type silicon bonding layer; 108-drain.
Detailed Description
The present invention will be described below by taking an N-channel IGBT as an example with reference to the accompanying drawings.
As shown in fig. 1 to 11, the device can be specifically prepared by the following steps:
(1) preparing a P + -type wide band gap semiconductor material as a P + -type substrate 801 as shown in fig. 1;
(2) epitaxially growing an N + type wide band gap buffer layer 802 on the upper surface of the P + type substrate 801 of the wide band gap semiconductor material, as shown in fig. 2;
(3) an N-type wide band gap epitaxial layer 803 is epitaxially grown on the upper surface of the N + type wide band gap buffer layer 802, as shown in fig. 3. Wide bandgap semiconductorThe bulk materials are all silicon carbide or gallium nitride, and the doping concentration of the N-type wide band gap epitaxial layer 803 is (10)14-1016)cm-3The doping concentration of the N-type wide band gap epitaxial layer 803 is 4-6 orders of magnitude smaller than that of the P + type substrate 801 and 2-4 orders of magnitude smaller than that of the N + type wide band gap buffer layer 802;
(4) on the upper surface of the N-type wide band gap epitaxial layer 803, an N-type silicon bonding layer 804 is bonded by a room temperature crystal bonding technique, and high temperature annealing is performed after bonding is completed, as shown in fig. 4. The N-type silicon bonding layer 804 is a thin layer of 1-5 microns, and the part of the P-type base region 107 extending into the wide-bandgap N-type epitaxial layer 803 is not more than two thirds;
(5) oxidizing the upper surface of the N-type silicon bonding layer 804 to form a silicon dioxide film, and etching the silicon dioxide film by using an anisotropic etching method under the protection of a mask to form an active region (not shown in the figure), as shown in fig. 5;
(6) further forming a gate oxide layer 102 on the upper surface of the N-type silicon bonding layer 804, depositing polysilicon, etching the polysilicon and the gate oxide layer, removing the portions at the left and right end regions to form a polysilicon gate 103, as shown in fig. 6;
(7) forming a P-type base region 107 in the left and right end regions of the upper part of the N-type silicon bonding layer 804 by using boron ion implantation and double diffusion technology, and during the process of well pushing, the junction depth finally depends on the temperature and time of the well pushing, so as to ensure that the longitudinal boundary of the P-type base region 107 extends into the wide band gap N-type epitaxial layer 803, that is, the PN junction formed by the P-type base region 107 and the N-type wide band gap epitaxial layer 803 is located in the N-type wide band gap epitaxial layer 803, and the channel is still located in the N-type silicon bonding layer 804, as shown in fig. 7;
(8) forming heavily doped N + source region 106 and P + channel substrate contact 105 by ion implantation, and forming corresponding channel (not shown) by double diffusion technology, wherein annealing time is as short as possible after implantation, as shown in fig. 8;
(9) depositing a silicon oxide film on the surface of the device, and etching a contact hole at a position corresponding to the source electrode, as shown in FIG. 9;
(10) depositing metal in the contact hole and etching to remove the rest of the silicon oxide film on the periphery to form source electrodes 101 and 104, and connecting the two source electrodes together (not shown), as shown in fig. 10;
(11) a metalized drain 108 is formed on the bottom surface of the P + type substrate as shown in fig. 11.
As shown in fig. 12, the structure of the device mainly comprises:
a P + type substrate 801 of wide bandgap semiconductor material;
an N + type buffer layer made of a wide band gap semiconductor material epitaxially grown on the upper surface of the P + type substrate 801 is marked as an N + type wide band gap buffer layer 802;
an N-type epitaxial layer of a wide band gap semiconductor material epitaxially grown on the upper surface of the N + type wide band gap buffer layer 802 is denoted as an N-type wide band gap epitaxial layer 803;
an N-type bonding layer of silicon material is bonded on the upper surface of the N-type wide band gap epitaxial layer 803 by using a crystal bonding technology, and is marked as an N-type silicon bonding layer 804;
two P-type base regions 107 formed in the left and right end regions of the upper portion of the N-type silicon bonding layer 804, respectively; a channel, an N + type source region 106 and a P + channel substrate contact 105 are formed in each P type base region 107, wherein the N + type source region 106 is adjacent to the channel, and the P + channel substrate contact 105 is positioned at the far end of the channel relative to the N + type source region 106; the longitudinal boundary of the P-type base region 107 extends into the wide band gap N-type epitaxial layer 803, i.e., a PN junction formed by the P-type base region 107 and the N-type wide band gap epitaxial layer 803 is located in the N-type wide band gap epitaxial layer 803, and a channel is still located in the N-type silicon bonding layer 804;
the gate oxide layer is positioned between the two P-type base regions 107 and on the upper surfaces of part of the N + type source region 106 and the corresponding channel, and the middle part of the gate oxide layer covers the upper surface of the N-type silicon bonding layer 804;
a gate 103 located inside the gate oxide layer;
and the drain electrode 108 is positioned on the lower surface of the P + type substrate 801.
Compared with the traditional silicon-based IGBT device, the IGBT device disclosed by the invention combines the wide band gap semiconductor material with the silicon semiconductor material to form a heterojunction, and uses the wide band gap semiconductor material as part of the P-type base region, the drift region, the buffer layer and the substrate of the IGBT device.
ISE TCAD simulation shows that the performance of the device is improved compared with the traditional silicon-based IGBT, and the breakdown voltage of the device is improved by 5-7 times compared with the traditional silicon-based IGBT under the condition that the thicknesses of drift regions of the two devices are the same and the doping concentration of the drift regions is the same.
The IGBT of the present invention may also be a P-type channel, and its structure is equivalent to the above-mentioned N-channel IGBT, and should also be considered as belonging to the protection scope of the claims of the present application, and is not described herein again.
The material extending over the wide band gap semiconductor material in the present invention is a silicon semiconductor material, and should be understood in a broad sense, that is, other element semiconductor materials such as germanium and the like and the wide band gap semiconductor form an IGBT which is equivalent to the IGBT described in the present invention, and should also be considered as belonging to the protection scope of the claims of the present application, and the details thereof are not described herein again.
Claims (7)
1. An insulated gate bipolar transistor having a wide bandgap semiconductor material/silicon semiconductor material heterojunction, comprising:
a P + type substrate (801) of wide bandgap semiconductor material;
an N + type buffer layer made of wide band gap semiconductor materials is epitaxially grown on the upper surface of the P + type substrate (801), and is marked as an N + type wide band gap buffer layer (802);
epitaxially growing an N-type epitaxial layer made of a wide band gap semiconductor material on the upper surface of the N + type wide band gap buffer layer (802), and marking the N-type epitaxial layer as an N-type wide band gap epitaxial layer (803);
an N-type bonding layer of silicon materials is bonded on the upper surface of the N-type wide band gap epitaxial layer (803) by utilizing a crystal bonding technology and is marked as an N-type silicon bonding layer (804);
forming two P-type base regions (107) in the left end region and the right end region of the upper part of the N-type silicon bonding layer (804) respectively; forming a channel in each P-type base region (107), and an N + type source region (106) and a P + channel substrate contact (105), wherein the N + type source region (106) is adjacent to the channel, and the P + channel substrate contact (105) is located at a far end of the channel relative to the N + type source region (106); the longitudinal boundary of the P-type base region (107) extends into the N-type wide band gap epitaxial layer (803), namely a PN junction formed by the P-type base region (107) and the N-type wide band gap epitaxial layer (803) is positioned in the N-type wide band gap epitaxial layer (803), and a channel is still positioned in the N-type silicon bonding layer (804);
the doping concentration of the N-type wide band gap epitaxial layer (803) is 1014-1016cm-3(ii) a The doping concentration of the N-type wide band gap epitaxial layer (803) is 4-6 orders of magnitude smaller than that of the P + type substrate (801) and 2-4 orders of magnitude smaller than that of the N + type wide band gap buffer layer (802);
the gate oxide layer (102) is positioned between the two P-type base regions (107), part of the N + type source region (106) and the upper surface of the corresponding channel, and the middle part of the gate oxide layer covers the upper surface of the N-type silicon bonding layer (804);
a gate (103) located inside the gate oxide layer;
two source electrodes (101, 104) covering the upper surface of the region where the corresponding P + channel substrate contact (105) is connected with the N + type source region (106), wherein the two source electrodes (101, 104) are connected together;
a drain (108) located on a lower surface of the P + type substrate (801);
the thickness and the doping concentration of the N-type wide band gap epitaxial layer (803) are determined by the voltage withstanding requirement of the device, and the doping concentration of the N-type wide band gap epitaxial layer (803) is lower than the doping concentrations of the N + type wide band gap buffer layer (802) and the P + type substrate (801).
2. The insulated gate bipolar transistor of claim 1 having a wide bandgap semiconductor material/silicon semiconductor material heterojunction, wherein: the wide band gap semiconductor material is silicon carbide, gallium nitride or diamond.
3. The insulated gate bipolar transistor of claim 1 having a wide bandgap semiconductor material/silicon semiconductor material heterojunction, wherein: the doping concentration of the P + type substrate (801) is 1 x 1020cm-3The doping concentration of the N + type wide band gap buffer layer (802) is 1 multiplied by 1018cm-3；
When withstanding voltageWhen 1120V is obtained, the thickness of the N-type wide band gap epitaxial layer (803) is 10 μm, and the doping concentration of the N-type wide band gap epitaxial layer (803) and the N-type silicon bonding layer (804) is 2 x 1015cm-3；
When the withstand voltage is required to be 1570V, the thickness of the N-type wide band gap epitaxial layer 803 is 17 μm, and the doping concentration of the N-type wide band gap epitaxial layer 803 and the N-type silicon bonding layer 804 is 2X 1015cm-3；
When the withstand voltage requirement is 1650V, the thickness of the N-type wide band gap epitaxial layer (803) is 17 μm, and the doping concentration of the N-type wide band gap epitaxial layer (803) and the N-type silicon bonding layer (804) is 1 × 1015cm-3。
4. The insulated gate bipolar transistor of claim 1 having a wide bandgap semiconductor material/silicon semiconductor material heterojunction, wherein: the P-type base region (107) and the N + type source region (106) thereof, the P + channel substrate contact (105) and the channel are formed on the upper part of the N-type silicon bonding layer (804) by ion implantation and double diffusion technology.
5. The insulated gate bipolar transistor of claim 1 having a wide bandgap semiconductor material/silicon semiconductor material heterojunction, wherein: the gate (103) is a polysilicon gate, the sources (101, 104) are metalized sources, and the drain (108) is a metalized drain.
6. A method of fabricating an insulated gate bipolar transistor having a wide bandgap semiconductor material/silicon semiconductor material heterojunction, comprising the steps of:
(1) preparing a P + type wide band gap semiconductor material as a P + type substrate (801);
(2) epitaxially growing an N + type wide band gap buffer layer (802) on the upper surface of a P + type substrate (801) made of a wide band gap semiconductor material;
(3) epitaxially growing an N-type wide band gap epitaxial layer (803) on the upper surface of the N + type wide band gap buffer layer (802);
(4) combining an N-type silicon bonding layer (804) on the upper surface of the N-type wide band gap epitaxial layer (803) by a room temperature crystal bonding technology, and performing high-temperature annealing after bonding;
(5) oxidizing the upper surface of the N-type silicon bonding layer (804) to form a silicon dioxide film, and etching the silicon dioxide film by adopting an anisotropic etching method under the protection of a mask to form an active region;
(6) further forming a gate oxide layer (102) on the upper surface of the N-type silicon bonding layer (804), depositing polycrystalline silicon, etching the polycrystalline silicon and the gate oxide layer, removing parts located at the left end region and the right end region, and forming a polycrystalline silicon gate (103);
(7) forming a P-type base region (107) in the left end region and the right end region of the upper part of the N-type silicon bonding layer (804) through boron ion implantation and double diffusion technology, performing a trap pushing process, and finally ensuring that the longitudinal boundary of the P-type base region (107) extends into the N-type wide band gap epitaxial layer (803) depending on the temperature and time of a trap, namely a PN junction formed by the P-type base region (107) and the N-type wide band gap epitaxial layer (803) is positioned in the N-type wide band gap epitaxial layer (803) and a channel is still positioned in the N-type silicon bonding layer (804);
(8) forming a heavily doped N + source region (106) and a P + channel substrate contact (105) in an ion implantation mode, forming a corresponding channel by adopting a double diffusion technology, and annealing after the implantation is finished;
(9) depositing a silicon oxide film on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
(10) depositing metal in the contact hole and etching to remove the rest silicon oxide film on the periphery to form source electrodes (101, 104), and connecting the two source electrodes together;
(11) a metalized drain is formed on the lower surface of a P + type substrate (801).
7. The method of claim 6, wherein: the wide band gap semiconductor material is silicon carbide, gallium nitride or diamond.
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| CN107086243A (en) * | 2017-03-16 | 2017-08-22 | 西安电子科技大学 | The U MOSFET being combined with wide bandgap material and silicon materials |
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| CN107086243A (en) * | 2017-03-16 | 2017-08-22 | 西安电子科技大学 | The U MOSFET being combined with wide bandgap material and silicon materials |
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