CN108595295B - Method and system for testing micro instruction sequence - Google Patents
Method and system for testing micro instruction sequence Download PDFInfo
- Publication number
- CN108595295B CN108595295B CN201810380360.7A CN201810380360A CN108595295B CN 108595295 B CN108595295 B CN 108595295B CN 201810380360 A CN201810380360 A CN 201810380360A CN 108595295 B CN108595295 B CN 108595295B
- Authority
- CN
- China
- Prior art keywords
- execution
- micro instruction
- instruction sequence
- paths
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
A method and system for testing a sequence of micro instructions is provided. The provided test method comprises the following steps: generating one or more commands to access the NVM chip as stimuli to test the sequence of microinstructions; acquiring an execution track of a micro instruction sequence and a logic unit corresponding to the execution track; grouping the execution tracks according to the logic units corresponding to the execution tracks; extracting execution paths matched with possible execution paths of the micro instruction sequence from each group of execution paths as covered execution paths; and accumulating the plurality of covered execution paths extracted from each group of execution tracks to obtain all covered execution paths, and obtaining the execution path coverage rate through the ratio of all covered execution paths to all possible execution paths.
Description
Technical Field
The present application relates to a storage technology, and more particularly, to a method and apparatus for testing a media interface controller of a storage control chip, so as to accelerate a test process targeting coverage rate.
Background
Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capability for the host. The host and storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the storage device 102 via, for example, SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The Memory device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and optionally a firmware Memory 110. The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc. The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and firmware memory 110, and also for storage management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, either in software, hardware, firmware, or a combination thereof. The control component 104 may be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit ), or a combination thereof. The control component 104 can also include a processor or controller. The control component 104 loads firmware from the firmware memory 110 at runtime. Firmware memory 110 may be NOR flash, ROM, EEPROM, or may be part of NVM chip 105.
The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.
The memory Target (Target) is one or more Logic units (Logic units) of a shared Chip Enable (CE) signal within the NAND flash package. Each logical unit has a logical unit number (LUN, logic Unit Number). One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within a NAND flash memory chip may execute commands and report status independently of each other. In "Open NAND Flash Interface Specification (review 3.0)" available from http:// www.micron.com/-/media/Documents/Products/Other% 20Documents/ONFI3_0gold. Ashx, the meaning of target, logical unit, LUN, plane is provided as part of the prior art.
Data is typically stored and read on a storage medium on a page basis. While data is erased in blocks. A block (also called a physical block) contains a plurality of pages. A block contains a plurality of pages. Pages on a storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes.
In chinese patent application publication No. CN1414468A, a scheme is provided for processing CPU (Central Processing Unit ) instructions by executing a micro instruction sequence. When the CPU is to process the specific instruction, the conversion logic circuit converts the specific instruction into a micro instruction sequence corresponding to the specific instruction, and the function of the specific instruction is realized by executing the micro instruction sequence. The micro instruction sequence or a template of the micro instruction sequence is stored in a ROM (Read Only Memory). In the process of converting a specific instruction into a micro instruction sequence, the micro instruction sequence template can be filled so as to correspond to the specific instruction.
Micro-instruction execution methods and apparatus for flash memory interface controllers are provided in chinese patent applications CN201610009789.6 and CN201510253428.1, chinese patent application CN 201610861793.5 provides a micro-instruction sequence scheduling method and apparatus, chinese patent application CN 201611213754.0 provides an IO command processing method and solid state storage device, chinese patent application CN 201611213755.5 provides a high capacity NVM interface controller, and the entire contents thereof are incorporated herein. The flash interface controller is typically coupled to multiple NVM chips, which include multiple LUNs (Logic units) or dies that can respond to and access NVM commands in parallel. Also, since there may be multiple NVM commands to be processed on each LUN or die, the NVM controller needs to schedule the processing of multiple NVM commands to maintain multiple in-process or pending NVM commands, or to maintain execution of multiple micro instruction sequences for generating and processing NVM commands.
Disclosure of Invention
The sequences of microinstructions executed by the storage controller or its media interface controller need to be sufficiently tested to deliver high quality products. There are many possible ways in which the micro instruction sequence may be executed for different scenarios. In order to cover a plurality of possible execution modes in the test, a great deal of time is spent for developing test cases, executing the test, collecting execution results and analyzing the test coverage rate, which brings great challenges to the rapid convergence of the test.
According to a first aspect of the present application, there is provided a method of testing a sequence of microinstructions executed by a first memory controller according to the first aspect of the present application, comprising: generating one or more commands to access the NVM chip as stimuli to test the sequence of microinstructions; acquiring an execution track of a micro instruction sequence and a logic unit corresponding to the execution track; grouping the execution tracks according to the logic units corresponding to the execution tracks; extracting execution paths matched with possible execution paths of the micro instruction sequence from each group of execution paths as covered execution paths; and accumulating the plurality of covered execution paths extracted from each group of execution tracks to obtain all covered execution paths, and obtaining the execution path coverage rate through the ratio of all covered execution paths to all possible execution paths.
According to the method for testing the micro instruction sequence executed by the first storage controller of the first aspect of the present application, there is provided a method for testing the micro instruction sequence executed by the second storage controller of the first aspect of the present application, further comprising: and if the coverage rate of the execution path reaches a specified threshold, terminating the test.
According to the method for testing the micro instruction sequence executed by the first or the second storage controller of the first aspect of the present application, there is provided a method for testing the micro instruction sequence executed by the third storage controller of the first aspect of the present application, further comprising: if the coverage rate of the execution paths does not reach the specified threshold, generating a second stimulus according to the execution paths which are not covered in all possible execution paths, so that when the tested micro instruction sequence is executed to process the command corresponding to the generated second stimulus, executing the execution paths which are not covered in the tested micro instruction sequence.
According to one of the test methods of the micro instruction sequences executed by the first to third memory controllers of the first aspect of the present application, there is provided the test method of the micro instruction sequences executed by the fourth memory controller of the first aspect of the present application, wherein a plurality of commands accessing different logic units as stimuli are executed concurrently.
According to a fourth storage controller executed micro instruction sequence test method of the first aspect of the present application, there is provided a fifth storage controller executed micro instruction sequence test method of the first aspect of the present application, wherein the plurality of commands accessing different logic units as stimuli each have different parameters.
According to one of the test methods of the micro instruction sequences executed by the first to fifth memory controllers of the first aspect of the present application, there is provided the test method of the micro instruction sequences executed by the sixth memory controller of the first aspect of the present application, wherein a plurality of commands accessing the NVM chip are randomly generated as stimuli for testing the micro instruction sequences.
According to a test method of a micro instruction sequence executed by a sixth memory controller according to the first aspect of the present application, there is provided a test method of a micro instruction sequence executed by a seventh memory controller according to the first aspect of the present application, wherein a plurality of commands accessing the NVM chip are randomly generated as stimuli for testing the micro instruction sequence by specifying the frequency and order of each type of the plurality of types of commands generated and/or one or more constraints applied to the generated commands.
According to one of the test methods of the micro instruction sequences executed by the first to seventh memory controllers of the first aspect of the present application, there is provided the test method of the micro instruction sequences executed by the eighth memory controller of the first aspect of the present application, wherein the respective micro instruction sequences are executed by a plurality of processor cores to process the stimulus.
According to a test method of a micro instruction sequence executed by an eighth storage controller in the first aspect of the present application, there is provided a test method of a micro instruction sequence executed by a ninth storage controller in the first aspect of the present application, wherein a plurality of processor cores each execute the same micro instruction sequence; and each processor core is coupled to a different NVM chip.
According to a test method of a micro instruction sequence executed by a ninth storage controller of the first aspect of the present application, there is provided a test method of a micro instruction sequence executed by a tenth storage controller of the first aspect of the present application, wherein each micro instruction sequence executed by a processor core accesses a plurality of logic units.
According to one of the test methods of the micro instruction sequences executed by the eighth to tenth memory controllers according to the first aspect of the present application, there is provided the test method of the micro instruction sequences executed by the eleventh memory controller according to the first aspect of the present application, wherein different stimuli are applied to the respective processor cores.
According to a test method of a micro instruction sequence executed by an eleventh memory controller according to the first aspect of the present application, there is provided a test method of a micro instruction sequence executed by a twelfth memory controller according to the first aspect of the present application, wherein the stimulus applied to each processor core is a command of the same type having different parameters to access the NVM chip.
According to one of the test methods of the micro instruction sequences executed by the eighth to twelfth memory controllers of the first aspect of the present application, there is provided the test method of the micro instruction sequences executed by the thirteenth memory controller of the tenth aspect of the present application, wherein the execution trace of the micro instruction sequences and the logic unit corresponding to the execution trace are acquired from each of the plurality of processor cores.
According to one of the test methods of the micro instruction sequence executed by the first to thirteenth memory controllers of the first aspect of the present application, there is provided the test method of the micro instruction sequence executed by the fourteenth memory controller according to the tenth aspect of the present application, further comprising: analyzing the micro instruction sequence generates all possible execution paths of the micro instruction sequence.
According to a test method of a micro instruction sequence executed by a fourteenth memory controller in a first aspect of the present application, a test method of a micro instruction sequence executed by the fifteenth memory controller in the first aspect of the present application is provided, wherein a directed graph is generated according to the micro instruction sequence, wherein an address where a branch instruction is located, an address where a jump instruction is located, or a target address of a branch/jump in the micro instruction sequence is a node of the generated directed graph, and a directed edge between the nodes indicates an execution order of the micro instruction corresponding to the address corresponding to the node.
According to the test method of the micro instruction sequence executed by the fifteenth memory controller of the first aspect of the present application, there is provided the test method of the micro instruction sequence executed by the sixteenth memory controller of the first aspect of the present application, further comprising: two or more nodes in the directed graph are merged.
According to a fifteenth or sixteenth storage controller of the present application, there is provided a method for testing a sequence of micro instructions, further comprising: eliminating loops in the directed graph.
According to a seventeenth aspect of the present application, there is provided a method for testing a micro instruction sequence executed by an eighteenth storage controller according to the first aspect of the present application, wherein if two directed edges exist between a first node and a second node, and the first node and the second node are an exit point and an entry point, the directed edges from the second node to the first node are eliminated, so as to eliminate a loop, wherein an address corresponding to the second node is executed after an address corresponding to the first node.
According to a seventeenth or eighteenth aspect of the present application, there is provided a test method of a micro instruction sequence executed by a nineteenth storage controller according to the first aspect of the present application, wherein when a node of a directed graph is accessed a second time by traversing the generated directed graph, an edge causing the second access is canceled to eliminate a loop.
According to one of the test methods of the micro instruction sequence executed by the fifteenth to nineteenth storage controllers of the first aspect of the present application, there is provided the test method of the micro instruction sequence executed by the twentieth storage controller according to the tenth aspect of the present application, further comprising: traversing the directed graph, and acquiring all possible execution paths from a root node to leaf nodes of the directed graph as all possible execution paths of the micro instruction sequence.
According to one of the test methods of the micro instruction sequence executed by the fifteenth to twentieth memory controllers of the first aspect of the present application, there is provided the test method of the micro instruction sequence executed by the twentieth memory controller of the tenth aspect of the present application, wherein a first memory address identical to an address corresponding to a root node of the directed graph is obtained from an execution trace, a second memory address subsequent to the first memory address is obtained from the execution trace, one or more execution paths identical to the second memory address and corresponding to a next node corresponding to the root node of the directed graph are searched from all possible execution paths as candidate execution paths until a subsequent memory address obtained from the execution trace is identical to an address corresponding to a leaf node of one of the candidate execution paths, so as to obtain a matched execution path.
According to a twenty-first memory controller of the first aspect of the present application, there is provided a method for testing a micro instruction sequence executed by the twenty-second memory controller of the first aspect of the present application, wherein if a subsequent memory address obtained from an execution trace is different from an address corresponding to a next node with respect to a current node in any candidate execution path, the next subsequent memory address obtained from the execution trace is compared with an address corresponding to the next node in the candidate execution path until the obtained next subsequent memory address is the same as the address corresponding to the next node in the candidate execution path.
According to a second aspect of the present application, there is provided a method of testing a first sequence of microinstructions according to the second aspect of the present application, comprising: generating an excitation of the test micro instruction sequence; acquiring an execution track of a micro instruction sequence; extracting an execution path matched with a possible execution path of the micro instruction sequence from the execution track as an overlaid execution path; and accumulating the plurality of covered execution paths extracted from the execution track to obtain the coverage rate of the execution paths.
There is provided according to a third aspect of the present application a test system for a first sequence of microinstructions according to the third aspect of the present application, comprising: a stimulus generation module for generating one or more commands to access the NVM chip as a stimulus to test the micro instruction sequence; the excitation applying module is used for acquiring the excitation generated by the excitation generating module and applying the excitation to the tested storage controller; and the coverage rate analysis module acquires the execution track of the micro instruction sequence from the storage controller, extracts the execution path matched with the possible execution path of the micro instruction sequence from the execution track as a covered execution path, and accumulates a plurality of covered execution paths extracted from the execution track to obtain the coverage rate of the execution path.
According to a first micro instruction sequence test system of a third aspect of the present application, there is provided a test system of a second micro instruction sequence according to the third aspect of the present application, further comprising: and the evaluation unit is used for acquiring an execution result of the excitation from the storage controller, acquiring the excitation from the excitation generation module and comparing the execution result with an expected result of the excitation.
According to the first or second micro instruction sequence test system of the third aspect of the present application, there is provided the third micro instruction sequence test system of the third aspect of the present application, wherein the coverage rate analysis module further obtains logic units corresponding to execution tracks, and groups the execution tracks according to the logic units corresponding to the execution tracks; and extracting the execution paths matched with the possible execution paths of the micro instruction sequence from each group of execution paths as covered execution paths.
According to one of the first to third micro instruction sequence test systems of the third aspect of the present application, there is provided a test system of a fourth micro instruction sequence according to the third aspect of the present application, wherein the coverage test module further records all possible execution paths of the micro instruction sequence.
According to a fourth micro instruction sequence test system according to the third aspect of the present application, there is provided a test system according to the fifth micro instruction sequence according to the third aspect of the present application, wherein all possible execution paths are obtained by analyzing the micro instruction sequence.
According to one of the first to fifth micro instruction sequence test systems of the third aspect of the present application, there is provided a test system of the sixth micro instruction sequence according to the third aspect of the present application, wherein the coverage analysis module identifies that the execution path coverage reaches a specified threshold, instructing the test system to terminate the test.
According to one of the first to sixth micro instruction sequence testing systems of the third aspect of the present application, there is provided a seventh micro instruction sequence testing system according to the third aspect of the present application, further comprising: the coverage rate analysis module identifies that the coverage rate of the execution paths does not reach a specified threshold value, and indicates the excitation generation module to generate a second excitation according to the execution paths which are not covered in all possible execution paths, so that when the tested micro instruction sequence is executed to process a command corresponding to the generated second excitation, the execution paths which are not covered in the tested micro instruction sequence are executed.
According to one of the first to seventh micro instruction sequence test systems of the third aspect of the present application, there is provided the test system of the eighth micro instruction sequence according to the third aspect of the present application, wherein the memory controller concurrently executes a plurality of commands as stimuli accessing different logic units.
According to an eighth micro instruction sequence test system of the third aspect of the present application, there is provided the test system of the ninth micro instruction sequence of the third aspect of the present application, wherein the plurality of commands as stimuli accessing different logic units each have different parameters.
According to one of the first to ninth micro instruction sequence test systems of the third aspect of the present application, there is provided the test system of the tenth micro instruction sequence according to the third aspect of the present application, wherein the stimulus generation module randomly generates a plurality of commands to access the NVM chip as the stimulus for testing the micro instruction sequence.
According to a tenth micro instruction sequence test system of the third aspect of the present application, there is provided the test system of the eleventh micro instruction sequence of the third aspect of the present application, wherein the stimulus generation module randomly generates a plurality of commands accessing the NVM chip as the stimulus for the test micro instruction sequence by specifying the frequency and order of each type of the plurality of types of commands generated, and/or one or more constraints applied to the generated commands.
According to one of the first through eleventh micro instruction sequence test systems of the third aspect of the present application, there is provided a test system of the twelfth micro instruction sequence according to the third aspect of the present application, wherein the plurality of processor cores of the memory controller execute respective micro instruction sequences to process stimuli.
According to a twelfth micro instruction sequence test system of the third aspect of the present application, there is provided the test system of the thirteenth micro instruction sequence of the third aspect of the present application, wherein the plurality of processor cores of the memory controller each execute the same micro instruction sequence; and each processor core is coupled to a different NVM chip.
According to a thirteenth micro instruction sequence test system according to the third aspect of the present application, there is provided a test system according to the fourteenth micro instruction sequence of the third aspect of the present application, wherein each of the micro instruction sequences executed by the processor cores accesses a plurality of logic units.
One of the twelfth to fourteenth micro instruction sequence test systems according to the third aspect of the present application provides the test system according to the fifteenth instruction sequence of the third aspect of the present application, wherein the stimulus applying module applies different stimulus to each processor core.
According to a fifteenth instruction sequence test system of the third aspect of the present application, there is provided the test system of the sixteenth instruction sequence of the third aspect of the present application, wherein the stimuli applied to the respective processor cores are commands of the same type having different parameters to access the NVM chip.
One of the twelfth to sixteenth instruction sequence testing systems according to the third aspect of the present application provides the seventeenth instruction sequence testing system according to the third aspect of the present application, wherein the coverage analysis module acquires an execution trace of the microinstruction sequence and a logic unit corresponding to the execution trace from each of the plurality of processor cores.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 illustrates a block diagram of a prior art memory device;
FIG. 2A is a block diagram of a media interface controller of a control component according to an embodiment of the present application;
FIG. 2B is a block diagram of an NVM interface controller for a solid state disk controller in accordance with yet another embodiment of the present application
FIG. 3 is a schematic diagram of generating directed graph nodes from a sequence of microinstructions according to an embodiment of the application;
FIG. 4 illustrates a portion of a directed graph generated from a sequence of microinstructions;
FIG. 5A shows a directed graph derived from a sequence of microinstructions according to an embodiment of the application;
FIG. 5B illustrates all 4 possible execution paths traversing FIG. 5A;
FIG. 6 illustrates a test system according to an embodiment of the application;
FIG. 7 is a schematic diagram of execution traces of a fetched micro instruction sequence according to an embodiment of the application;
FIG. 8 is a schematic diagram showing matching of execution traces and execution paths of a micro instruction sequence;
FIG. 9 is a schematic diagram of a coverage test method according to an embodiment of the application; and
FIG. 10 is a schematic diagram of an excitation generation module according to an embodiment of the present application; and
fig. 11 is a schematic diagram of a coverage test method according to yet another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
FIG. 2A is a block diagram of a media interface controller of a control component according to an embodiment of the present application. The media interface controller in fig. 2A includes a message queue 210 and an NVM command processing unit 220. In the embodiment of fig. 2A, message queue 210 is used to receive messages from a control unit (see also control unit of fig. 1) to access the NVM chip. The messages from the control component may include messages indicating read, write, delete NVM chips, messages indicating read NV M chip status, read or set NVM chip Feature (Feature), and also user-defined messages. NVM command processing unit 220 retrieves the message from message queue 210 and sends NVM interface commands conforming to the NVM chip interface standard or receives data or status from NVM according to the NVM chip interface standard to the NVM chip according to the indication of the message. By way of example, the NVM command processing unit according to an embodiment of the present application performs scheduling of NVM interface commands by, for example, executing instructions or micro-instructions. Message queue 210 includes one or more message queues.
NVM command processing unit 220 includes, for example, 2 processor cores (core 1 and core 2) coupled to multiple NVM chips through the processor cores. In the embodiment of FIG. 2A, NVM command processing unit 220 is coupled to 4 NVM chips through 2 channels (CH 1 and CH 2), core 1 is coupled to a first channel, and core 2 is coupled to a second channel. Each NVM chip includes 2 LUNs. The NVM chips (NVM 0 and NVM 1) on channel CH1 provide LUN0 and LUN1, respectively, and the NVM chips (NVM 2 and NVM 3) on channel CH2 provide their LUN0 and LUN1, respectively. It will be appreciated that the NVM interface controller can couple more channels and access more NVM chips and more LUNs.
The media interface controller is capable of processing multiple messages from multiple message queues accessing the NVM chip in parallel. The NVM command processing unit may include multiple processor cores, each of which may run multiple threads, each of which may process multiple NVM interface commands in parallel. The processor cores or threads executing the sequences of micro instructions access respective NVM chips. The sequence of micro instructions that can be executed is called a thread. Since the same micro instruction sequence has its own execution state at each execution, multiple threads can be created based on the same micro instruction sequence. Execution state is also stored in NVM command processing unit 220 for each thread. According to an embodiment of the application, threads are created or used based on the LUNs to be accessed. For example, thread 1 is used to access LUN1, and/or thread 2 is used to access LUN2.
FIG. 2B is a block diagram of an NVM interface controller for a solid state disk controller in accordance with yet another embodiment of the present invention. The NVM interface controller in fig. 2B includes a command queue 201 and an NVM command processing unit 202.NVM processing unit 202 includes a plurality of processor cores (core 1 and core 2 are shown), each of which accesses a corresponding NVM chip by executing a sequence of microinstructions. Context resources are allocated for execution of the sequence of microinstructions. By way of example, the context resource corresponds to a LUN. For example, processor core 1 is responsible for accessing LUN0, LUN 1, LUN 2, and LUN 3. Context 1 is assigned to core 1 for accessing LUN0, and context 2 core 1 is assigned for accessing LUN 3. The microinstruction sequence executed by core 1 accesses LUN 1 using context 1 and LUN 3 using context 2. Fig. 2B uses two contexts used by core 1. Optionally, each LUN managed by core 1 is provided with a corresponding context resource. The context records the state of execution of the micro-execution sequence associated with the LUN, e.g., data cache, program counter for the micro-instruction sequence, timer, etc. Similarly, in the embodiment of FIG. 2B, the microinstruction sequence executed by core 2 accesses LUN 5 using context 3 and LUN 7 using context 4.
According to an embodiment of the present application, a sequence of micro instructions is analyzed to extract all possible execution paths of the sequence of micro instructions. And capturing the execution rule of the micro instruction of the processor core in the test process to identify which possible execution paths are executed and contract all the executed paths to obtain the code coverage rate of the micro instruction sequence.
FIG. 3 is a schematic diagram of a directed graph node generated from a sequence of microinstructions according to an embodiment of the application.
Referring to FIG. 3, the micro instruction sequence 310 includes a plurality of micro instructions, each of which may be located at a specified memory address (indicated by the "address" field of FIG. 3), having a specified micro instruction code, and the processor core identifies the specified micro instruction based on the micro instruction code and performs the operation specified by the micro instruction. The assembly code corresponding to each micro instruction is also shown in FIG. 3 to facilitate understanding of the meaning of the micro instruction by those skilled in the art.
Typically, the processor core executes each microinstruction in sequence of memory addresses (e.g., down in FIG. 3, or in an increasing order of addresses). Some microinstructions are branch/jump microinstructions, the order in which the microinstructions are executed changes as the branch/jump microinstructions are executed, and the processor core then executes the microinstructions at the memory address indicated by the branch/jump microinstruction. To obtain all possible execution paths of a sequence of micro instructions, the sequence of micro instructions is converted into a directed graph according to an embodiment of the present application. The directed graph includes points and edges, where a point indicates a micro instruction, or memory address where the micro memory is located. The edges of the directed graph have directions from the exit point to the entry point and mean that after execution of the microinstruction corresponding to the exit point, the microinstruction executed by the entry point will be executed. Optionally, there may be one or more other micro-instructions in the sequence of micro-instructions between the micro-instructions corresponding to the exit point and the entry point that will necessarily be executed without affecting the calculation of coverage of the micro-instruction execution path.
According to an embodiment of the application, a set of nodes 320 of a directed graph is generated from a sequence of micro instructions 310. In FIG. 3, the set of nodes of the directed graph is shown as a table, with each entry of the table showing the memory address corresponding to the microinstruction and its assembly code. It will be appreciated that assembly code is shown for purposes of understanding, and that each element of the directed graph's node set 320 may record only the memory address to which the microinstruction corresponds.
To generate the node set 320 of the directed graph, the branch microinstructions, the jump microinstructions, and the exit (exit), yield (Yield), etc. microinstructions having the meaning of branch/jump in the microinstruction sequence 310 are selected. Optionally, the target address of the branch/jump microinstruction in the microinstruction sequence 310 is also selected and added to the node set 320. The destination address is not necessary as an element of node set 320. The processor core continues to execute downward at the target address until execution of the branch/jump microinstruction to the next node as a directed graph.
From the directed graph node set 320, a directed graph is generated. Each element in the node set 320 is considered a node of the directed graph. Directed edges are established from one node of the directed graph to the other or both nodes, depending on the target address or addresses of the represented branches/hops for each element in the node set 320.
And optionally, two or more nodes in the resulting directed graph may be combined. For example, if there is only one directed edge between two nodes, and the exit point of the directed edge is not taken as the exit point of any other directed edge, the two nodes may be combined into one node. By way of example, two nodes that are executed sequentially will be merged.
Due to the presence of loop structures, the directed graph generated from the micro instruction sequence may have loops. Fig. 4 shows a schematic diagram of a directed graph elimination loop according to an embodiment of the application.
Referring to FIG. 4, a portion of a directed graph generated from a sequence of microinstructions is shown, including the directed graph nodes, and their edges, indicated by addresses "0x00000049", "0x0000004b", "0x0000004e", and "0x 00000052". Where nodes "0x0000004b" and "0x0000004e" form a loop structure, there is a directed edge from node "0x0000004b" to "0x0000004e" (410), while there is also a directed edge from node "0x0000004e" to "0x0000004b" (420). With this structure, the directed edges pointing from node "0x0000004e" to "0x0000004b" are deleted to eliminate loops in the directed graph. In general, traversing the directed graph, when a node of the directed graph (e.g., node "0x0000004 b") is accessed a second time, the edge (420) directed to that node (e.g., node "0x0000004 b") that caused the second access is canceled to eliminate the loop.
FIG. 5A shows a directed graph derived from a sequence of microinstructions according to an embodiment of the application.
The nodes of the directed graph shown in FIG. 5A are indicated by the addresses of the microinstructions in memory, and the directed graph has eliminated loops. In the nodes of the directed graph of fig. 5A, taking "0x00000000 (0)" as an example, the characters before the brackets "()" indicate the addresses of the microinstructions corresponding to the nodes in the memory, and the numbers in the brackets indicate the serial numbers of the nodes. The edges of the directed graph indicate the point of entry to which the edge is currently executed, and the point of entry to which the edge is executed next. Any path from the root node to the leaf node of the directed graph represents one possible execution path for the sequence of microinstructions.
Traversing the directed graph shown by FIG. 5A, all possible paths from the root node to the leaf nodes of the directed graph are obtained and are shown in FIG. 5B.
Fig. 5B shows all 4 possible execution paths traversing fig. 5A, each path starting with the root node "0x00000000 (0)" and ending with the leaf node of the directed graph.
FIG. 6 illustrates a test system according to an embodiment of the application.
The test system is used to test NVM command processing units 610 (see also fig. 2A or 2B for NVM command processing units). A stimulus generation module of the test system is configured to generate, as a stimulus for application to the NVM command processing unit, one or more commands for accessing the NVM chip, and optionally parameters for the commands and/or a sequence between the commands. The stimulus applying module 630 receives the stimulus provided by the stimulus generating unit 620, converts the stimulus into a format and an interface form receivable by the NVM command processing unit 610, and provides the format and the interface form to the NVM command processing unit 610. The execution result acquisition unit extracts the execution result of the NVM command processing unit 610 and supplies it to the evaluation unit 660. The evaluation unit 660 receives the execution result provided by the execution result acquisition unit 640, compares the execution result with the expected result corresponding to the stimulus provided by the stimulus generation unit 620, to evaluate the correctness of the response of the NVM command processing unit 610 to the generated stimulus.
The coverage analysis unit 650 obtains the execution trace of the execution micro instruction sequence by the NVM command processing unit 610 and identifies the path coverage for the test of the micro instruction sequence by the execution trace. The execution trace acquired by the coverage analysis unit 650 is, for example, a memory address sequence of each micro instruction in the order to be executed. Optionally, the memory address of each micro-instruction being executed is taken along with the processor core executing the micro-instruction, the context number, and/or the Logical Unit (LUN) accessed by the executing micro-instruction.
FIG. 7 is a schematic diagram of execution traces of a fetched micro instruction sequence according to an embodiment of the application.
Fig. 7 shows an execution trace, which is an execution trace acquired from the NVM command processing unit 610 in chronological order. The square identified by the numeral indicates the memory address of the microinstruction. The earlier the memory address corresponding to the left square is received, the later the memory address corresponding to the right square is received. The numbers in the boxes indicate, for example, the Logical Units (LUNs) accessed when the microinstructions are executed.
FIG. 7 illustrates an execution trace, intermixed with memory addresses of microinstructions accessing multiple Logical Units (LUNs). According to the Logic Units (LUNs) corresponding to the execution tracks, grouping the execution tracks, and accessing the same logic units by the microinstructions corresponding to the execution tracks of each group. Fig. 7 illustrates the execution trace of the access logical unit (LUN 0), the execution trace of the access logical unit (LUN 1), and the execution trace of the access logical unit (LUN 2). Each set of execution traces preserves the order in which the execution traces were acquired.
Alternatively, the execution traces that are acquired access only the same logical unit and thus belong to the same group.
Referring back to FIG. 6, the coverage analysis unit 650 will access, for example, the execution trace of logic unit 0, and match the possible execution paths resulting from the micro instruction sequence (see FIGS. 5A and 5B) to identify which one or more of the possible execution paths of the micro instruction sequence have been executed by the NVM processing unit, resulting in a path coverage of the micro instruction sequence.
For example, in FIGS. 5A and 5B, the execution paths of the micro instruction sequences start at address "0x 00000000". The memory address "0x00000000" is found from the execution trace accessing, for example, logic unit 0, and the subsequent execution trace is matched to the execution path of the micro instruction sequence in fig. 5A and 5B.
FIG. 8 is a schematic diagram showing matching of execution traces and execution paths of a micro instruction sequence.
In fig. 8, the left side shows the execution trace segment obtained from the NVM command processing unit starting at memory address "0x00000000" and ending at memory address "0x0000034 e". While the right side of fig. 8 illustrates all possible execution paths of a micro instruction sequence. From the execution trajectory, an intersection (for example, "0x 00000000") of the execution path is found as the start of the matching. The next execution trace is the memory address "0x00000001", the execution path whose second node is the memory address "0x00000001" is found out of all possible execution paths as a candidate execution path, and other execution paths (for example, the execution path whose second node is "0x 00000003") may be excluded from the search range. Next, the memory address "0x00000268" of the execution trace is searched for an execution path whose third node is the memory address "0x00000268" from all the remaining possible execution paths as a candidate execution path. In this way, until one of the candidate execution paths is completely matched, the completely matched execution path is marked as covered.
Optionally, the micro instruction sequence has a plurality of entries. Correspondingly, generating a directed graph corresponding to the micro instruction sequence according to each entry of the micro instruction sequence, and traversing each directed graph to obtain all possible execution paths of the micro instruction sequence. And when matching the execution trace with the execution path, taking any one of a plurality of entries of the micro instruction sequence as a start of the matching.
Optionally, some microinstructions are not in the execution paths shown in fig. 5A and 5B, since the nodes of the directed graph are merged, or the nodes of the directed graph include only branch/jump instructions and their target addresses. In the matching process of the execution trace and the execution path, the memory address from the execution trace that cannot be matched in any execution path is discarded.
And counting which of all possible execution paths of the micro instruction sequence are matched with the captured execution paths, and obtaining the execution path coverage rate of the micro instruction sequence through the ratio of the execution paths matched with the captured execution paths to all the possible execution paths.
Fig. 9 is a schematic diagram of a coverage test method according to an embodiment of the present application.
By way of example, the embodiment of FIG. 9 performs coverage testing on 4 processor cores (core 1, core 2, core 3, and core 4, respectively) of an NVM command processing unit. A stimulus (910) is generated for each of the processor cores, such as one or more commands to be processed by the processor cores to access the NVM chip. The generated stimulus is applied to the processor core. By way of example, a single stimulus is generated and applied to each processor core such that each processor core executes the same sequence of micro instructions, processes the same command as a stimulus, and accesses a different logical unit.
All possible execution paths are generated from the sequence of micro instructions executed by the processor core. For example, all possible execution paths thereof are generated from a sequence of micro instructions in the manner shown in FIGS. 3-5.
One of the processor cores is selected and an execution trace of the sequence of microinstructions is fetched 920 from the selected processor core. The execution trace is a sequence of micro instruction addresses in execution order and a logical unit identifier associated with each micro instruction address that is accessed by the processor core to execute the micro instruction sequence. Further, execution traces of the fetched micro instruction sequences are grouped by logical unit identification.
Execution paths matching the possible execution paths are extracted from execution traces of the sequence of micro instructions accessing the same logical unit as covered execution paths (930).
The method further includes summing a plurality of covered paths resulting from execution traces of the sequence of microinstructions accessing each of the plurality of logic units to obtain all covered execution paths, and deriving path coverage (940) based on a ratio of all covered execution paths to all possible execution paths.
Optionally, all covered execution paths and/or uncovered execution paths among all possible execution paths are also analyzed (950), and the generation of stimuli for coverage testing is directed (910) based on the analysis results. For example, if it is recognized from the analysis result that the execution path of the command corresponding to the first type of command to access the NVM chip is not covered, the proportion of the command of the first type of NVM chip is increased in the stimulus to be generated next. Alternatively or further, the path coverage reaching a specified threshold is used as a criterion for stopping the test.
FIG. 10 is a schematic diagram of an excitation generation module according to an embodiment of the application.
The stimulus generation module is for generating one or more commands, for example, to access the NVM chip. Commands for accessing the NVM chip are of various types, such as read commands, write commands, erase commands, parameter set commands, and reset commands. The excitation generation module generates commands corresponding to the command types according to each command type.
The excitation generation module comprises a read command test module, a write command test module, an erase command test module, a parameter setting command module and a reset command test module. The read command test module is used for generating a read command, the write command test module is used for generating a write command, the erase command test module is used for generating an erase command, the parameter setting command test module is used for generating a parameter setting command, and the reset command test module is used for generating a reset command. The read command test module, the write command test module, the erase command test module, the parameter setting command module and the reset command test module are all coupled to an excitation selector, and the excitation selector selects one or more commands generated by the read command test module, the write command test module, the erase command test module, the parameter setting command module and the reset command test module as outputs of the excitation generating module.
Optionally, the stimulus selector also maintains the order and/or weight (or frequency) of retrieving commands from the read command test module, the write command test module, the erase command test module, the parameter set command module, and the reset command test module to apply constraints to the generated stimulus. For example, a write command is applied to a specified address before a read command is issued to the specified address; before a write command is applied to a specified address, the memory cell where the specified address is located is erased.
The command to access the NVM chip has a specified format. For example, a read command may be set to the address of the read, the length of the data read, the type of read (read page buffer, read physical page, read redo, etc.). The time interval from when the read command is issued to when the result of the read command is queried may also be set. The time interval of two read commands, and the number of read commands to be generated, may also be set. These settable items are provided as a variety of constraints to the read command test module. The read command test module generates a read command as an incentive according to one or more constraints.
Similarly, a write command may be set to the address of the write, the length of the data written, the type of write (write command optimized for latency, write command optimized for lifetime, etc.). The time interval from when the write command is issued to when the result of the write command is queried may also be set. The time interval of two adjacent write commands, and the number of write commands to be generated, may also be set. These settable items are provided as a variety of constraints to the write command test module. The write command test module generates a write command as an incentive according to one or more constraints.
Similarly, the erase command may be set an address of erase, a type of erase (erase command optimized for latency, erase command optimized for lifetime, etc.). The time interval from when the erase command is issued to when the result of the erase command is queried may also be set. The time interval of two adjacent erase commands, and the number of erase commands to be generated, may also be set. These settable items are used as a variety of constraints to provide the erase command test module. The erase command test module generates an erase command as an incentive in accordance with one or more constraints.
Similarly, the parameter set command may be set with an address of the parameter, a value of the parameter, and/or a length of the parameter. The time interval between two adjacent parameter setting commands, the type of parameter setting command (the scope of action is a logic unit, the scope of action is a die, parameters are acquired, etc.), and the number of parameter setting commands to be generated may also be set. These settable items are provided as a variety of constraints to the parameter set command test module. The parameter setting command test module generates a parameter setting command as an incentive according to one or more constraints.
Similarly, the timing of generating the reset command, and/or the time interval of two adjacent reset commands may be set. These settable items are used as a variety of constraints to provide a reset command test module. The reset command test module generates a reset command as an excitation according to one or more constraints.
Further, the frequency of use of the one or more constraints, and/or fluctuations in the one or more constraints, is provided to the read command test module, the write command test module, the erase command test module, the parameter set command module, and/or the reset command test module. Thereby generating diversified commands. For example, addresses accessed by the generated plurality of read commands conform to a probability distribution.
Fig. 11 is a schematic diagram of a coverage test method according to yet another embodiment of the present application.
The embodiment of FIG. 11 performs coverage testing on 4 processor cores (core 1, core 2, core 3, and core 4, respectively) of an NVM command processing unit. Stimuli (1110, 1112, 1114, and 1116) are generated for each of the processor cores. The generated stimulus is applied to the processor core. According to the embodiment of FIG. 11, the stimulus generated for each processor core is different, thereby enabling the individual processor cores to execute different paths of the micro instruction sequence to expedite the coverage test process. Each processor core executes the same sequence of micro instructions, processes different commands as stimuli, and accesses different logical units. In response to processing different commands as stimuli, different paths of the sequence of microinstructions are executed on respective processor cores.
In an alternative embodiment, the same command (e.g., a read command or a write command) as the stimulus is applied to the respective processor cores, while different constraints are applied to the commands received by each processor core (see also FIG. 10). For example, constraints having a specified probability distribution are imposed on the addresses accessed by the read commands, such that the addresses accessed by the pending read commands received by the respective processor cores conform to the specified probability distribution.
All possible execution paths are generated from the sequence of micro instructions executed by the processor core. For example, all possible execution paths thereof are generated from a sequence of micro instructions in the manner shown in FIGS. 3-5.
For each processor core, execution traces (1120, 1122, 1124, and 1126) for the sequence of micro instructions are fetched from the processor core. The execution trace is a sequence of micro instruction addresses in execution order and a logical unit identifier associated with each micro instruction address that is accessed by the processor core to execute the micro instruction sequence. Further, execution traces of the fetched micro instruction sequences are grouped by logical unit identification.
Execution paths matching possible execution paths are extracted from execution traces of a sequence of microinstructions accessing the same logical unit as covered execution paths (1130, 1132, 1134, and 1136).
The multiple matched paths resulting from execution traces of the sequence of microinstructions accessing each of the multiple logic units are summed to obtain all covered execution paths, and a path coverage is obtained based on a ratio of all covered execution paths to all possible execution paths (1140).
Optionally, all covered execution paths and/or uncovered execution paths among all possible execution paths are also analyzed 1150, and based on the analysis results, a generation policy for stimuli for coverage testing of one or more processor cores is adjusted 910. The generation strategy of the stimulus includes, for example, the order and/or the weight (or frequency) by which the stimulus selector obtains the commands from the read command test module, the write command test module, the erase command test module, the parameter set command module, and the reset command test module, and the frequency with which the read command test module, the write command test module, the erase command test module, the parameter set command module, and/or the reset command test module provide for the use of one or more constraints, and/or the fluctuation of one or more constraints. Still alternatively, if it is recognized from the analysis result that the execution path of the command corresponding to the first type of command to access the NVM chip is not covered, the proportion of the command of the first type of NVM chip is increased in the stimulus to be generated next.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A method for testing a micro instruction sequence comprises the following steps:
generating an excitation of the test micro instruction sequence;
acquiring an execution track of a micro instruction sequence;
extracting an execution path matched with a possible execution path of the micro instruction sequence from the execution track as an overlaid execution path;
accumulating a plurality of covered execution paths extracted from the execution track to obtain an execution path coverage rate;
the execution track of the obtained micro instruction sequence comprises a micro instruction address sequence according to the execution sequence;
generating a directed graph according to the micro instruction sequence, wherein the directed graph comprises nodes and edges between the nodes, the nodes indicate micro instructions or memory addresses corresponding to the micro instructions, and the edges between the nodes indicate the execution sequence of the micro instructions corresponding to the nodes; traversing the directed graph, and acquiring all possible execution paths from a root node to leaf nodes of the directed graph as all possible execution paths of a micro instruction sequence;
The method comprises the steps of obtaining a first memory address which is the same as the address corresponding to a root node of a directed graph from an execution track, obtaining a second memory address which is subsequent to the first memory address from the execution track, searching one or more execution paths which are the same as the second memory address and are corresponding to the next node corresponding to the root node of the directed graph from all possible execution paths, and taking the one or more execution paths as candidate execution paths until the subsequent memory address which is obtained from the execution track is the same as the address corresponding to a leaf node of one of the candidate execution paths, so that a matched execution path is obtained.
2. A method of testing a sequence of microinstructions executed by a memory controller, comprising:
generating one or more commands to access the NVM chip as stimuli to test the sequence of microinstructions;
acquiring an execution track of a micro instruction sequence and a logic unit corresponding to the execution track;
grouping the execution tracks according to the logic units corresponding to the execution tracks;
extracting execution paths matched with possible execution paths of the micro instruction sequence from each group of execution paths as covered execution paths;
accumulating a plurality of covered execution paths extracted from each group of execution tracks to obtain all covered execution paths, and obtaining the coverage rate of the execution paths through the ratio of all covered execution paths to all possible execution paths;
The method comprises the steps of acquiring an execution track of a micro instruction sequence, wherein the acquisition of the execution track of the micro instruction sequence comprises acquisition of a micro instruction address sequence according to an execution sequence and a logic unit identifier which is associated with each micro instruction address and is accessed by executing the micro instruction;
generating a directed graph according to the micro instruction sequence, wherein the directed graph comprises nodes and edges between the nodes, the nodes indicate micro instructions or memory addresses corresponding to the micro instructions, and the edges between the nodes indicate the execution sequence of the micro instructions corresponding to the nodes; traversing the directed graph, and acquiring all possible execution paths from a root node to leaf nodes of the directed graph as all possible execution paths of a micro instruction sequence;
the method comprises the steps of obtaining a first memory address which is the same as the address corresponding to a root node of a directed graph from an execution track, obtaining a second memory address which is subsequent to the first memory address from the execution track, searching one or more execution paths which are the same as the second memory address and are corresponding to the next node corresponding to the root node of the directed graph from all possible execution paths, and taking the one or more execution paths as candidate execution paths until the subsequent memory address which is obtained from the execution track is the same as the address corresponding to a leaf node of one of the candidate execution paths, so that a matched execution path is obtained.
3. The method of claim 2, further comprising:
if the coverage rate of the execution paths does not reach the specified threshold, generating a second stimulus according to the execution paths which are not covered in all possible execution paths, so that when the tested micro instruction sequence is executed to process the command corresponding to the generated second stimulus, executing the execution paths which are not covered in the tested micro instruction sequence.
4. A method according to claim 2 or 3, wherein
Multiple commands accessing different logical units as stimuli are executed concurrently.
5. A method according to one of claims 2 or 3, wherein
A plurality of commands to access the NVM chip are randomly generated as stimuli to test the micro-instruction sequence.
6. The method of claim 5, wherein
Multiple commands accessing the NVM chip are randomly generated as stimuli to test the sequence of microinstructions by specifying the frequency and order of each type of multiple types of commands generated, and/or one or more constraints applied to the generated commands.
7. A test system for storing sequences of microinstructions executed by a controller, comprising:
a stimulus generation module for generating one or more commands to access the NVM chip as a stimulus to test the micro instruction sequence;
The excitation applying module is used for acquiring the excitation generated by the excitation generating module and applying the excitation to the tested storage controller;
the coverage rate analysis module acquires the execution track of the micro instruction sequence from the storage controller, extracts an execution path matched with the possible execution path of the micro instruction sequence from the execution track as a covered execution path, and accumulates a plurality of covered execution paths extracted from the execution track to obtain the execution path coverage rate;
the execution track of the obtained micro instruction sequence comprises a micro instruction address sequence according to the execution sequence;
generating a directed graph according to the micro instruction sequence, wherein the directed graph comprises nodes and edges between the nodes, the nodes indicate micro instructions or memory addresses corresponding to the micro instructions, and the edges between the nodes indicate the execution sequence of the micro instructions corresponding to the nodes; traversing the directed graph, and acquiring all possible execution paths from a root node to leaf nodes of the directed graph as all possible execution paths of a micro instruction sequence;
the method comprises the steps of obtaining a first memory address which is the same as the address corresponding to a root node of a directed graph from an execution track, obtaining a second memory address which is subsequent to the first memory address from the execution track, searching one or more execution paths which are the same as the second memory address and are corresponding to the next node corresponding to the root node of the directed graph from all possible execution paths, and taking the one or more execution paths as candidate execution paths until the subsequent memory address which is obtained from the execution track is the same as the address corresponding to a leaf node of one of the candidate execution paths, so that a matched execution path is obtained.
8. The test system of claim 7, further comprising:
and the evaluation unit is used for acquiring an execution result of the excitation from the storage controller, acquiring the excitation from the excitation generation module and comparing the execution result with an expected result of the excitation.
9. The test system of claim 7 or 8, wherein
The coverage rate analysis module is used for acquiring logic units corresponding to the execution tracks and grouping the execution tracks according to the logic units corresponding to the execution tracks; and extracting the execution paths matched with the possible execution paths of the micro instruction sequence from each group of execution paths as covered execution paths.
10. The test system of one of claims 7 or 8, wherein
The stimulus generation module randomly generates a plurality of commands accessing the NVM chip as a stimulus for testing the sequence of microinstructions by specifying the frequency and order of each type of the plurality of types of commands generated, and/or one or more constraints applied to the generated commands.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2017114476426 | 2017-12-27 | ||
| CN201711447642 | 2017-12-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108595295A CN108595295A (en) | 2018-09-28 |
| CN108595295B true CN108595295B (en) | 2023-09-12 |
Family
ID=63609827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810380360.7A Active CN108595295B (en) | 2017-12-27 | 2018-04-25 | Method and system for testing micro instruction sequence |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108595295B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979686A (en) * | 2005-12-06 | 2007-06-13 | 上海华虹Nec电子有限公司 | Safety detecting method for system integrated chip with built-in non-volatile memory |
| CN102902906A (en) * | 2012-09-26 | 2013-01-30 | 中国航天科技集团公司第九研究院第七七一研究所 | Microprocessor instruction set validation method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6981188B2 (en) * | 2001-08-16 | 2005-12-27 | Tower Semiconductor Ltd. | Non-volatile memory device with self test |
| US10877874B2 (en) * | 2007-12-28 | 2020-12-29 | Federal Home Loan Mortgage Corporation (Freddie Mac) | Systems and methods for modeling and generating test requirements for software applications |
| JP5107131B2 (en) * | 2008-04-28 | 2012-12-26 | 株式会社東芝 | Test case generation device, generation method thereof, and program for test case generation |
| US8352813B2 (en) * | 2009-09-30 | 2013-01-08 | Freescale Semiconductor, Inc. | Transition fault testing for a non-volatile memory |
| US8904355B2 (en) * | 2013-03-14 | 2014-12-02 | Accenture Global Services Limited | Test script generation system |
-
2018
- 2018-04-25 CN CN201810380360.7A patent/CN108595295B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979686A (en) * | 2005-12-06 | 2007-06-13 | 上海华虹Nec电子有限公司 | Safety detecting method for system integrated chip with built-in non-volatile memory |
| CN102902906A (en) * | 2012-09-26 | 2013-01-30 | 中国航天科技集团公司第九研究院第七七一研究所 | Microprocessor instruction set validation method |
Non-Patent Citations (1)
| Title |
|---|
| 郝焱,汪东升.嵌入式微处理器的软硬件协同验证.计算机工程与设计.2004,(第07期),1053-1058. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108595295A (en) | 2018-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9430288B2 (en) | Job scheduling based on historical job data | |
| WO2018120721A1 (en) | Method and system for testing user interface, electronic device, and computer readable storage medium | |
| CN106095866B (en) | The optimization method and device of application program recommended method, program starting speed | |
| CN111324427B (en) | Task scheduling method and device based on DSP | |
| US10089207B2 (en) | Identification of software phases using machine learning | |
| US10193969B2 (en) | Parallel processing system, method, and storage medium | |
| CN103106364A (en) | Program analyzing system and method | |
| CN106708752B (en) | Memory method for obligating and device | |
| CN110688168A (en) | Method, device and equipment for improving starting speed of application program and storage medium | |
| Schlagkamp et al. | Understanding user behavior: from HPC to HTC | |
| US10558391B2 (en) | Data processing system and data processing method | |
| US9940157B2 (en) | Computer readable medium, method, and management device for determining whether a virtual machine can be constructed within a time period determined based on historical data | |
| CN108628759B (en) | Method and apparatus for out-of-order execution of NVM commands | |
| CN108572932B (en) | Multi-plane NVM command fusion method and device | |
| CN110427259A (en) | A kind of task processing method and device | |
| CN108595295B (en) | Method and system for testing micro instruction sequence | |
| CN104933105B (en) | The analysis method and device of database access request | |
| CN112346962A (en) | Comparison data testing method and device applied to comparison testing system | |
| CN108563580B (en) | Method for extracting microcode execution path of medium interface controller | |
| US10990604B2 (en) | Non-transitory computer-readable storage medium, record data processing method, and record data processing apparatus | |
| CN111459796B (en) | Automated testing method, apparatus, computer device and storage medium | |
| CN107704362A (en) | A kind of method and device based on Ambari monitoring big data components | |
| US9342511B2 (en) | Fast selection in hardware or software | |
| CN113127369A (en) | Processing method and device for execution script | |
| Gomez-Sanchez et al. | Using AWS EC2 as Test-Bed infrastructure in theI/O system configuration for HPC applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |