CN108536611A

CN108536611A - Wear leveling in nonvolatile memory

Info

Publication number: CN108536611A
Application number: CN201810168238.3A
Authority: CN
Inventors: K.K.古纳姆
Original assignee: Western Digital Technologies Inc
Current assignee: Western Digital Technologies Inc
Priority date: 2017-03-03
Filing date: 2018-02-28
Publication date: 2018-09-14
Anticipated expiration: 2038-02-28
Also published as: DE102018104650A1; DE102018104650B4; CN108536611B

Abstract

Disclose the system and method for the wear leveling in nonvolatile memory (NVM).One such system includes：State of a control determiner is accumulated, is configured to determine the accumulation state of a control of the state of the Random Maps between the physical block address (PBA) and logical block address (LBA) of instruction NVM；Network is accessed, accumulation state of a control is configured to and LBA is converted into PBA；Backstage exchanges scheduler, is configured to state of a control to exchange the PBA for distributing to preselected LBA.One such method is related to：Determine the accumulation state of a control of the state of the Random Maps between the physical block address (PBA) and logical block address (LBA) of instruction NVM, based on accumulation state of a control LBA is converted into PBA, and the PBA for distributing to preselected LBA is exchanged based on state of a control.

Description

Wear leveling in nonvolatile memory

Cross reference to related applications

The application is the part continuation application for the U.S. Patent Application No. 15/449,612 submitted on March 3rd, 2017, Attorney docket is HGST-1010 (H20151149US4), entitled " ACCESS NETWORK FOR ADDRESS MAPPING IN NON-VOLATILE MEMORIES ", this application require the U.S. Provisional Application No. 62/360 submitted on July 11st, 2016, No. 916 priority and rights, attorney number is HGST-1011PROV (H20161077), entitled “GENERATION OF RANDOM ADDRESS MAPPING IN NON-VOLATILE MEMORIES USING LOCAL AND GLOBAL INTERLEAVING ", and be the U.S. Patent Application No. 14/967,169 submitted on December 11st, 2015 Part continuation application, attorney docket be HGST-1003 (H20151149US2), entitled " GENERATION OF RANDOM ADDRESS MAPPING IN NON-VOLATILE MEMORIES USING LOCAL AND GLOBAL INTERLEAVING ", it is required that the priority and power of the U.S. Provisional Application No. 62/192,509 submitted on July 14th, 2015 Benefit, attorney number are HGST-1003P (H20151149), entitled " SYSTEMS AND METHODS FOR PROVIDING DYNAMIC WEAR LEVELING IN NON-VOLATILE MEMORIES ", each application cited above Full content be incorporated herein by reference.

Technical field

All aspects of this disclosure are usually directed to wear leveling, and more particularly to the damage in nonvolatile memory Consumption is balanced.

Background technology

In various consumption electronic products, often substitutes or mend in conjunction with the solid state drive of nonvolatile memory (NVM) Fill traditional rotating hard disk drive for bulk storage.These nonvolatile memories may include one or more flash memories Flash memory device can logically be divided into block, and can each block be further logically divided into addressable pages by device Face.These addressable pages can be any in all size (for example, 512 bytes, 1 kilobytes, 2 kilobytes, 4 kilobytes) One kind can match or mismatch the logical block address size used by Host computing device.

During write operation, the individually addressable page in the block of flash memory device can be write data into.However, usually Entire block must be wiped, to wipe or rewrite the page.It certainly, can be more or less depending on the data being stored therein in Wipe the different masses in each flash memory device.Thus, due to the quantity in the service life and erasing period of the storage element of flash memory device Correlation is more equally distributed in so many solid state drives carry out wear leveling operation (static and dynamic) to wipe On all blocks of flash memory device.

In order to ensure equably using all physical pages in NVM (such as flash memory device), it is common practice to safeguard The table of the frequency of use of all logical page (LPAGE)s, and the logical address being most frequently visited by periodically is mapped to physical cord Road.However, these methods based on table indirect addressing can generate significant expense in table size.For example, for having The storage device of 2 terabytes (TB) of the page of 512 bytes uses tableaux method, it would be desirable to the table of 137 gigabytes (GB). This is not obviously practical.

Invention content

In one aspect, the disclosure provides the Nonvolatile memory system for being configured for wear leveling, the system packet It includes：State of a control determiner is accumulated, which is configured to determine instruction physical block address (PBA) and logic The accumulation state of a control of the state of Random Maps between block address (LBA)；Network is accessed, which is based on tired LBA is converted to PBA by product state of a control；Backstage exchanges scheduler, which exchanges scheduler and be configured to state of a control Exchange the PBA for distributing to preselected LBA.

On the other hand, the disclosure provides the method for the wear leveling in Nonvolatile memory system, the party Method includes：Determine that the accumulation of the state of the Random Maps between instruction physical block address (PBA) and logical block address (LBA) controls LBA is converted to PBA based on accumulation state of a control, the PBA for distributing to preselected LBA is exchanged based on state of a control by state.

On the other hand, the disclosure provides the Nonvolatile memory system for being configured for wear leveling, the system Including：Determine that the accumulation of the state of the Random Maps between instruction physical block address (PBA) and logical block address (LBA) controls shape LBA is converted to the device of PBA based on accumulation state of a control by the device of state, based on state of a control come exchange distribute to it is preselected LBA PBA device.

Description of the drawings

Fig. 1 is the frame according to the solid-state device (SSD) that can carry out local address mapping of one embodiment of the disclosure Figure.

Fig. 2 is according to the block diagram of the system for carrying out local address mapping of one embodiment of the disclosure, the system Including can be used for logical block address (LBA) being mapped to the access network and accumulation state calculation block of physical block address (PBA).

Fig. 3 is the flow chart according to the process for wear leveling of one embodiment of the disclosure.

Fig. 4 is according to the block diagram of the access network that LBA is mapped to PBA of one embodiment of the disclosure, the access net Network includes the selection logical block that can be used in the address mapping system of Fig. 2.

Fig. 5 is the flow chart according to the process for LBA to be mapped to PBA of one embodiment of the disclosure.

Fig. 6-Fig. 9 be according to the figure of the exemplary physical block address at discrete time of one embodiment of the disclosure, It illustrates the example values for PBA and moving index variable, the behaviour about the selection logic device that LBA is mapped to PBA Make.

Figure 10 is according to the block diagram of the accumulation state calculation block of one embodiment of the disclosure, and it includes can be Fig. 2's The bitonic network and bitonic sorting device used in address mapping system.

Figure 11 is the figure according to the bitonic network of one embodiment of the disclosure.

Figure 12 is according to the figure of the bitonic sorting device of one embodiment of the disclosure, which includes sorting unit table With comparative type table.

Figure 13 is to control shape according to the accumulation being used to determine for LBA to be mapped to PBA of one embodiment of the disclosure The flow chart of the process of state.

Figure 14 is controlled according to the accumulation being configured to determine for LBA to be mapped to PBA of one embodiment of the disclosure The block diagram of the example hardware realization method of the equipment of state.

Figure 15 is according to the block diagram of another system for local address mapping of one embodiment of the disclosure, this is System includes the one or more read-only memory (ROM) for accessing network and the accumulation state value for storing precomputation.

Figure 16 a, Figure 16 b, Figure 16 c are according to one embodiment of the disclosure for storing and can making in the system of Figure 15 The schematic diagram of state of a control value, accumulation state of a control value and the ROM using indicator.

Figure 17 is the flow chart according to the process for wear leveling of one embodiment of the disclosure.

Figure 18 is somebody's turn to do according to the block diagram of another access network that LBA is mapped to PBA of one embodiment of the disclosure It includes the selection logical block that can be used in the address mapping system of Figure 15 to access network.

Figure 19 is the block diagram according to the indirect table of one embodiment of the disclosure.

Figure 20 be according to one embodiment of the disclosure for using it is local interweave and it is global interweave execute randomly The block diagram of the overall system of location mapping.

Figure 21 is to be reflected according to the use global map of one embodiment of the disclosure and local intertexture to execute random address The flow chart for the process penetrated.

Figure 22 is bit reversal (G position) according to one embodiment of the disclosure using global map and locally interweaves Replace the block diagram that (N-G position) executes the system of random address mapping.

Figure 23 is the numerical value shown according to the use of one embodiment of the disclosure to the global map of the bit reversal of G position Exemplary table.

Figure 24 is the numerical value locally to interweave shown according to the use of one embodiment of the disclosure to the displacement of N-G position Exemplary table.

Figure 25 is to show that one embodiment according to the disclosure is shown using the global map of bit reversal and using displacement The table of the numerical example locally to interweave.

Figure 26 is to can be used for executing the multistage interconnection network (MIN) locally to interweave according to one embodiment of the disclosure Block diagram.

Figure 27 is the block diagram that can be used for executing the butterfly MIN locally to interweave according to one embodiment of the disclosure.

Figure 28 is the block diagram that can be used for executing the Benes MIN locally to interweave according to one embodiment of the disclosure.

Figure 29 is the block diagram that can be used for executing the Omega MIN locally to interweave according to one embodiment of the disclosure.

Figure 30 shows the Omega that can be used for executing the modification locally to interweave of one embodiment according to the disclosure The block diagram of MIN.

Specific implementation mode

Referring now to the drawings, the system and method for the wear leveling in nonvolatile memory (NVM) are shown.One System includes as a：State of a control determiner is accumulated, which is configured to determine the object of instruction NVM Manage the accumulation state of a control of the state of the Random Maps between block address (PBA) and logical block address (LBA)；Network is accessed, it should It is that LBA is converted to PBA based on accumulation state of a control to access network configuration；Backstage exchanges scheduler, which exchanges scheduler State of a control is configured to exchange the PBA for distributing to preselected LBA.One such method is related to：Determine instruction NVM Physical block address (PBA) and logical block address (LBA) between Random Maps state accumulation state of a control, based on accumulation LBA is converted to PBA by state of a control, and the PBA for distributing to preselected LBA is exchanged based on state of a control.

The embodiment of these mapped systems and corresponding method can consist essentially of less than above-described indirect table Hardware, more specifically, including less for managing the storage body that LBA is mapped to PBA.In addition, using such as Figure 20-figure Shown in 30 and local discussed further below and global intertexture, these mapped systems and method can combine non-volatile well Random address mappings work in memory.

Fig. 1 is can be according to the solid-state device (SSD) that can carry out local address mapping of one embodiment of the disclosure Block diagram.System 100 includes host 102 and the SSD storage devices 104 for being coupled to host 102.Host 102 is to SSD storage devices 104 provide order, with the transmission data between host 102 and SSD storage devices 104.For example, host 102 can be stored to SSD Device 104 provides writing commands, data are written to SSD storage devices 104；Or it is provided to SSD storage devices 104 and reads life It enables, to read data from SSD storage devices 104.Host 102 can be had for data storage or the demand fetched and be used for Any system or device of the compatible interface communicated with SSD storage devices 104.For example, host 102 can be computing device, Personal computer, portable computer or work station, server, personal digital assistant, digital camera, digital telephone etc..

SSD storage devices 104 include host interface 106, controller 108, memory 110 and nonvolatile memory 112. Host interface 106 is coupled to controller 108, and promotes the communication between host 102 and controller 108.Additionally, controller 108 are coupled to memory 110 and nonvolatile memory 112.Host interface 106 can be any kind of communication interface, all Such as integrated drive electronics (IDE) interface, universal serial bus (USB) interface, serial peripheral (SP) interface, advanced technology attachment Part (ATA) interface, small computer system interface (SCSI), IEEE 1394 (firewire) interface etc..In some embodiments, main Machine 102 includes SSD storage devices 104.In other embodiments, SSD storage devices are long-range relative to host 102, or packet It is contained in the remote computing system being communicatively coupled with host 102.For example, host 102 can link and SSD by radio communication Storage device 104 communicates.

Controller 108 controls the operation of SSD storage devices 104.In various embodiments, controller 108 is connect by host Mouth 106 is received from host 102 and is ordered, and executes order to transmit number between host 102 and nonvolatile memory 112 According to.Controller 108 can include that any kind of processing unit (microcontroller, embedded controller, patrol by such as microprocessor Collect circuit, software, firmware etc.) it is used to control the operation of SSD storage devices 104.

In some embodiments, some or all of the function described herein of being executed by controller 108 can substitute Ground is executed by another element of SSD storage devices 104.For example, SSD storage devices 104 can include microprocessor, microcontroller Device, embedded controller, logic circuit, software, firmware or any kind of processing unit, for execute it is described herein by One or more of function performed by controller 108.In some embodiments, described herein to be held by controller 108 One or more of capable function can be executed alternatively by host 102.In some embodiments, described herein by controlling One or more of the function that device 108 processed executes can be executed alternatively by another element, such as be deposited comprising non-volatile Memory element and the controller in the hybrid drive of magnetic storage element.

Memory 110 can be any memory, computing device or the system that can store data.For example, memory 110 Can be random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), flash memory, Erasable Programmable Read Only Memory EPROM (EPROM), electricity can Erasable programmable read-only memory (EPROM) (EEPROM) etc..In various embodiments, controller 108 uses memory 110 or part thereof To store data during the transmission data between host 102 and nonvolatile memory 112.For example, memory 110 or memory 110 part can be buffer memory.

Nonvolatile memory (NVM) 112 receives data from controller 108 and stores data.Nonvolatile memory 112 Can be any kind of nonvolatile memory, such as flash memory system, solid state drive, flash card, secure digital (SD) card, universal serial bus (USB) memory device, CompactFlash cards, SmartMedia devices, flash memory storage array Deng.

Controller 108 or NVM 112 are configurable to execute any the one of local address mapping scheme described herein It is a.

Solve the problems, such as that a kind of method that background section above is directed to the big indirect table that the NVM based on the page is discussed is to change Logical block address (LBA) is more specifically mapped to physical block address by the kind process that logical page (LPAGE) is mapped to physical page (PBA) process.

Local address for wear leveling maps

Fig. 2 is according to the block diagram of the system 200 for executing local address mapping of one embodiment of the disclosure, system 200 include the access network 202 and accumulation state that can be used for logical block address (LBA) being mapped to physical block address (PBA) Calculation block 204.System 200 also includes initial and second memory mapping block 206, backstage exchange scheduler 208 and mapping shape State generates and changes block 210.In one aspect, accessing network 202 can be with hardware realization (for example, having 3 cycle pipelines The ultralow delay of delay, low logic device and memory are equal to less than 10000 logic gates), and the remainder of system 200 Part can be with firmware and/or software realization.

It will be discussed in more detail accessing network 202 below, access network 202 and receive CCS1 from accumulation state of a control block 204 State of a control is accumulated with newest two in CCS2, and exchanges scheduler 208 from backstage and receives moving index (move index).Using these inputs, two undernets (for example, bitonic network or Benes networks) can be used by accessing network 202 It determines given logical block address (LBA) is mapped to which physical block address (PBA), each in two undernets One in two accumulation state of a controls is received to generate possible mapping.

Accumulation state calculation block 204 will be discussed in more detail below, accumulation state calculation block 204 is (for example, accumulation control shape State determiner) it is initial when from the state of a control in initial and second memory mapping block 206 reception cs1 and cs2 and CCS1. On one side, initial control state can have random value and can CCS1 be set as cs1.After the initial period, tire out Cumuliformis state calculation block 204 can generate change block 210 from mapping status and receive these inputs.Use these inputs, accumulation state Calculation block 204 can determine the second accumulation state of a control CCS2, be the function of CCS1 and cs2.State of a control cs1 and cs2 can For use as the input of main bitonic network or other suitable networks, and eventually for determining second accumulation state of a control CCS2. Accumulating state of a control CCS1 and CCS2 can be used by access network 202 with the current LBA of determination to PBA map.A side Face when mapping is periodically changed in system, can be existed when once system completes all transmission in backstage using main bitonic network Accumulation state is calculated in firmware.It can use new state of a control (for example, cs2) in the firmware with another bitonic network Scheduling backstage is mobile.

In several applications of such as wear leveling, change its random access memory from LBA to PBA on a periodic basis Mapping, system 200 may need to put calculating accumulation Random Maps at any given time so that given LBA can be accurate Ground is located at correct PBA.In an example it is assumed that it is depositing for 2^32 to have the size with mapping function f1 (t1) in time t1 The Random Maps of reservoir have the Random Maps that the size with mapping function f2 is the memory of 2^32, in the time in time t2 T3 has the Random Maps ..., have with mapping function fn in time tn that the size with mapping function f3 is the memory of 2^32 Size be 2^32 memory Random Maps.In operation, system 200 can calculate cumulative function (cfn) in time tn, Cfn=fn (cfm), wherein cfm is made to be the cumulative functions in time tm, and tm=tn-1.In one aspect, system 200 Random Maps can be generated using bitonic network and STOCHASTIC CONTROL switch seed (for example, using accumulation state calculation block 204) Function (fn).Bitonic network be configurable to using STOCHASTIC CONTROL switch seed (for example, cs1, cs2 ..., csn) come provide with Machine mapping function (fn).Present cumulative function (cfn) can be recorded in by main bitonic sorting device, and by the control position of the switch In sequencer procedure.It can come that programming data width is 1 and network size is 32 using these controls position of the switch CCSn now Bitonic network, to generate accumulation Random Maps (for example, using access network 202) for 2^32 entry.At any time, Any one of 2^32 entry can generate the address of a displacement by the network.It will be described in greater detail below More specifically these operations are described about Figure 10-Figure 13.

Backstage exchanges scheduler 208 and is configured to execute the periodical exchange for the data being stored at preselected PBA.One A aspect, backstage exchange scheduler 208 are configurable to every 100 hosts write-in and execute primary exchange.On the other hand, after Platform exchanges scheduler 208 and is configurable to every primary exchange of X host write-in execution, and wherein X is positive integer.In one aspect, Backstage exchange scheduler 208 is configured to basis and executes movement for the new mappings (exchange) of two pages, thus for every 200 Host write-in scheduling movement.Backstage, which exchanges scheduler 208, can safeguard mobile counter, and mobile counter can be for every 200 A host write-in increases by 1.In one aspect, with the lookup for the bitonic network for using new state of a control (for example, cs2), with object The structured way managed on memory completes movement.In one aspect, mobile counter (for example, moving index) rises to from 1 N/2.Mobile counter can be referred to as moving index, move_index, MOVE_INDEX, move_counter and move counter.For each value, dispatching exchange makes the physical storage at mobile counter be exchanged with the physical storage.Example Such as, in one embodiment, backstage exchanges scheduler 208 can execute exchange as follows：

Physical addr1=MOVE_INDEX；

Physical addr2=f_cs2 (Physical_addr1)；

SWAP(Physical Addr1,Physical Addr2)

In this case, f_cs2 is the random mapping function generated based on state of a control cs2.It below will be Figure 10's The determination of cs2 is more fully described in discussion.In one example, cs2 can be for having 32 inputs and 32 outputs Bitonic network length be 320 bit sequences generated at random.

In one embodiment, MOVE_INDEX is set as 0 in initial memory and second memory block 206, and also It is set as 0 in mapping status generates and change block 210.In backstage exchanges scheduler 208, any number of host is write Enter (for example, such as every 100 hosts write-in or the write-in of every 200 hosts or host write-in of other suitable quantity in fig. 2), MOVE_INDEX can increase by 1.In another embodiment, due to that may be easier with hardware tracking host write-in, so can To increase logic with hardware realization MOVE_INDEX.In this case, MOVE_INDEX can increase from MOVE_INDEX is realized The new hardware logic blocks communication of long logic exchanges scheduler 208 to backstage, and directly communicates MOVE_INDEX to access net Network block 202, rather than exchange scheduler 208 (for example, firmware) from backstage and communicate to access network 202 (for example, hardware).

In one aspect, these operations of backstage exchange scheduler 208 may cause 1% write-in to be amplified.A side Face, it is assumed that swap operation is atom.

Mapping status generates and changes block 210 and is configured to update state of a control and accumulation once completing all exchange transmission State of a control.In one aspect, when moving index be equal to N/2 when, then should complete from before be mapped to the institute currently mapped There is exchange.Once completing, then mapping status, which generates and change block 210, can generate new mappings.In one aspect, mobile counter (for example, moving index) can be reset (for example, to 0 or 1).When mapping, which changes, to be completed, it can calculate in firmware State of a control is accumulated, and accumulation state of a control can be supplied to hardware.It can slightly these values of forward scheduling in firmware (for example, in mapping status generates and change block 210) is to ensure the timely communication of hardware (for example, accessing network 202). On one side, old state of a control (cs1) can be set as to new state of a control (cs2), and can be by old accumulation control State (CCS1) processed is set as new accumulation state of a control (CCS2).

The aspect for accessing network 202 and accumulation state calculation block 204 will be discussed in more detail below.

Exemplary wear balancing procedure

Fig. 3 is the flow chart according to the process 300 for wear leveling of one embodiment of the disclosure.Implement at one Example in, process 300 can by Fig. 2 wear leveling system 200 or other wear leveling systems described herein any one A execution.

In block 302, which determines reflecting at random between instruction physical block address (PBA) and logical block address (LBA) The accumulation state of a control for the state penetrated.In some aspects, the action of block 302 can be realized by controller 108, or as schemed It is realized in conjunction with host 102 by controller 108 shown in 1.In some aspects, block 302 can include accumulation state by Fig. 2 Any combinations of the wear leveling system 200 of determiner 204, the controller 108 of Fig. 1 and/or those components are calculated to realize. On one side, block 302 can calculate determiner 204 to realize by accumulation state.

In block 304, which is based on accumulation state of a control and logical block address (LBA) is converted to physical block address (PBA).In some aspects, the action of block 304 can be realized by controller 108, or pass through controller as shown in Figure 1 108 realize in conjunction with host 102.In some aspects, block 304 can include the wear leveling system for accessing network 202 by Fig. 2 System 200, the controller 108 of Fig. 1 and/or those components any combinations realize.In one aspect, block 304 can pass through visit Network 202 is asked to realize.

In block 306, which exchanges the PBA for distributing to preselected LBA based on state of a control.In some aspects, block 306 action can be realized by controller 108, or be realized as shown in Figure 1 in conjunction with host 102 by controller 108. In some aspects, block 306 can pass through the control of the wear leveling system 200, Fig. 1 that scheduler 208 is exchanged comprising backstage of Fig. 2 Any combinations of device 108 and/or those components are realized.In one aspect, block 306 can exchange scheduler 208 by backstage To realize.

In one aspect, accumulation state of a control includes the first accumulation state of a control and the second accumulation state of a control, wherein controlling State processed includes the first state of a control and the second state of a control, and the wherein second accumulation state of a control is the first accumulation state of a control With the function of the second state of a control.Above with respect to Fig. 2 and below in relation to Figure 11 be more fully described accumulation state of a control (for example, CCS1 and CCS2) and state of a control (for example, cs1, cs2).

In one aspect, which is further included in after the PBA for exchanging pre-selected number, and first memory is mapped Second memory mapping is changed into, wherein first memory mapping and second memory mapping respectively contains pre-selected number PBA.In one aspect, this can be executed by the mapping status block 210 of Fig. 2.

In one aspect, the PBA for distributing to preselected LBA is exchanged based on state of a control included in non-volatile memories PBA is exchanged after the access of the pre-selected number of the nonvolatile memory of device system.In one aspect, the visit of pre-selected number Ask it can is 100 times of nonvolatile memory write-ins.

In one aspect, process 300 also includes to generate the first PBA candidates from LBA using first function, uses second function It is candidate that the 2nd PBA is generated from LBA, and based on exchanging and be stored in the with the backstage for the data being stored at the first PBA candidates The information of the backstage exchange correlation of data at two PBA candidates, selects the first PBA candidate or the 2nd PBA candidates visit for data It asks.In one aspect, these actions can be executed by the access network 202 of Fig. 2 or the access network 300 of Fig. 3.A side Face, at least one of first function or second function include by multistage interconnection or block cipher (block cipher) At least one execution function.In one aspect, the second accumulation state of a control reflection is for realizing the first accumulation state of a control Displacement sequence switch setting, wherein generating the displacement using the second state of a control.

Fig. 4 is to access net according to the block diagram of the access network 400 that LBA is mapped to PBA of one embodiment of the disclosure Network 400 includes the selection logical block 402 that can be used in the address mapping system of Fig. 2.In one aspect, network 400 is accessed It can be used as accessing network 202 in the system of figure 2.System 400 also includes the first bitonic network 404 and the second bitonic network 406.First bitonic network 404 can receive LBA and new accumulation state of a control (CCS2) and generate second may physical block Address (PBA2).Similarly, the second bitonic network 406 can receive LBA and old accumulation state of a control (CCS1) and generate First may physical block address (PBA1).Then selection logic device 402 can analyze the position of the possible PBA in the page, Determine which is correctly to map to use preselected algorithm.More specifically, selection logic device 402 can be by PBA2 It is compared with the quantity (N) of the PBA in the page divided by 2 (for example, N/2).If PBA2 is less than N/2, temporary variable (Pba_ Mc) it is set as PBA2.Otherwise, Pba_mc is set as PBA1.If Pba_mc, which is less than the backstage from Fig. 2, exchanges scheduler 208 Moving index (OVE_INDEX), then correct PBA (for example, output PBA) is PBA2.Otherwise, correct PBA is PBA1.With Under will be described with selection logic device 402 operation.

In one aspect, selection logical block 402 can effectively determine in two possible PBA (for example, PBA1 and PBA2) Which contain the real data corresponding to LBA of concern.Midpoint (for example, N/2) of the determination based on the PBA in the page and Moving index.When the address of PBA1 and PBA2 to be compared with midpoint and moving index, select logical block 402 effectively true Which of fixed two PBA contain the real data corresponded in given time LBA of concern.For example, below will more It in the Fig. 6 being discussed in detail, is stored in PBA 3 in period CF0, LBA9, is stored in PBA 8 in CF1, stored up in CFn-1 There are in PBA 14, and it is stored in PBA 4 in CFn.The system can track most latter two possible position PBA 14 and PBA 4, they are the output of the function of ccs1 and ccs2.Then selection logical block 402 can accurately determine and 9 relevant numbers of LBA According to being to be still present in PBA 14 or be moved to PBA 4.

In one aspect, the first bitonic network 404 and second pair of 406 adjusted can be respectively by first networks and the second network It replaces.In this case, first network is configurable to generate the first PBA candidates from LBA using first function, and configures To use second function to generate the 2nd PBA candidates from LBA.In one aspect, first function and/or second function can be by more The function that grade interference networks and/or block cipher execute.Multistage interconnection can use Benes networks, inverse Benes networks, double One or more of network, inverse bitonic network, Omega network, inverse Omega network, butterfly network or inverse butterfly network is adjusted It realizes.In one aspect, first function and/or second function can be comprising exclusive or (exclusive OR) function and by multistage mutual Network network and/or the function of block cipher execution

In one aspect, any of logic device 402, the first bitonic network 404 and/or the second bitonic network 406 is selected One can be that special purpose processor or any function for being technically configured to/being programmed to carry out in the application are (all Function as shown in Figure 5) other suitable hardware (such as application-specific integrated circuit or above-described other hardware).

Fig. 5 is the flow chart according to the process 500 for LBA to be mapped to PBA of one embodiment of the disclosure.One In a embodiment, process 500 can be by the access network 400 of Fig. 4 or other local address mapped systems described herein Any one execution.In block 502, which generates the first physical block address (PBA) candidate using first function from LBA. In one aspect, first function can be held by first network as described above (for example, first bitonic network 404 of Fig. 4) Capable function.In some aspects, the action of block 502 can be realized by controller 108, or pass through control as shown in Figure 1 Device 108 is realized in conjunction with host 102.In some aspects, block 502 can by the first bitonic network 404 of Fig. 4, Fig. 4 second Bitonic network 406, the selection logic device 402 of Fig. 4, the controller 108 of Fig. 1 and/or those components any combinations realize. In one aspect, block 502 can be realized by the first bitonic network 404.In one aspect, block 502 can indicate to use the One function generates the device of the first PBA candidates from LBA.

In block 504, which generates the second physical block address (PBA) candidate using second function from LBA.A side Face, second function can be the functions executed by the second network as described above (for example, second bitonic network 406 of Fig. 4). In some aspects, the action of block 504 can be realized by controller 108, or be combined as shown in Figure 1 by controller 108 Host 102 is realized.In some aspects, block 504 can pass through the first bitonic network 404 of Fig. 4, the second bitonic network of Fig. 4 406, any combinations of the selection logic device 402 of Fig. 4, the controller 108 of Fig. 1 and/or those components are realized.A side Face, block 504 can be realized by the second bitonic network 406.In one aspect, block 504 can indicate using second function from LBA generates the device of the 2nd PBA candidates.

In block 506, the process with the backstage for the data being stored at the first PBA candidates based on exchanging and be stored in second The information of the backstage exchange correlation of data at PBA candidates, selects the first PBA candidate or the 2nd PBA candidates are used for data access. In one aspect, which can be executed by the selection logic device 402 of Fig. 4.In some aspects, the action of block 506 can To be realized by controller 108, or realized as shown in Figure 1 in conjunction with such as host 102 by controller 108.In certain sides Face, block 506 can by Fig. 4 selection logic device 402, Fig. 1 controller 108 and/or those components any combinations come It realizes.In one aspect, block 506 can be realized by selecting logic device 402.In one aspect, block 506 can represent one A device, the device is based on exchanging and be stored at the 2nd PBA candidates with the backstage for the data being stored at the first PBA candidates The information of the backstage exchange correlation of data, selects the first PBA candidate or the 2nd PBA candidates are used for data access.

In one aspect, exchange with the backstage for the data being stored at the first PBA candidates and be stored in the 2nd PBA candidates The information of the backstage exchange correlation of the data at place includes to be stored in the state and storage that the backstage of the data at the first PBA candidates exchanges There are the states that the backstage of the data at the 2nd PBA candidates exchanges.In one aspect, the first PBA candidates and the 2nd PBA candidates can To be included in PBA map.In this case, the example of status data can include the 2nd PBA candidates relative to PBA map In the position at midpoint, the PBA movement counters of position based on the 2nd PBA candidates and/or the instruction of all entries reflected in PBA The moving index for the current location that PBA in penetrating is exchanged.Selection course and mapping status data will be described in further detail below The example used.

In one aspect, processor 500 can also include to use in back-end data movement or back-end data exchange at least One part by the physical address space containing selected PBA candidates is mapped to another portion of physical address space Point.In one aspect, which can exchange scheduler 208 by the backstage of Fig. 2 and execute.

In alternative embodiments, can use memory table (referring to the exemplary system 1200 of Figure 12, can be in ROM Or store various state of a controls in other suitable memories) to execute, the first PBA of selection is candidate or the 2nd PBA is candidate.

In one aspect, which enables the data access of NVM, and wherein data access can be that read access or write-in are visited It asks.

Fig. 6-Fig. 9 be according to the figure of the exemplary physical block address at discrete time of one embodiment of the disclosure, The example values for PBA and moving index variable are illustrated, the operation about the selection logic device that LBA is mapped to PBA.

Fig. 6 shows the operation of the addressing logic device of the example values with PBA and moving index variable, wherein meeting First condition is (for example, PBA2<N/2) and second condition is unsatisfactory for (for example, PBA_mc<Move_index) so that correctly PBA is PBA1 or slot 14.Figure 60 0 shows physical block address (PBA) storage in the different time stage (for example, CF0 to CFn) Device maps.Logic device is selected to be operated using most latter two memory mapping (CFn and CFn-1).Input variable includes mobile rope Draw the quantity (N=16) of the entry in (move_index=2), PBA map, the overall situation of this status (L=8) and displacement of displacement Position (G=1).Though it is shown that variables L and G, they can be used for selecting in logic device or being not used in selection logic dress In setting.Since PBA2 is the position not exchanged --- since it is less than moving index (for the example, move_index= 2), so to select logic device to effectively determine PBA2 incorrect and select it to know for correct PBA1.More specifically, In the first condition, logic device is selected to determine that PBA2=4 is less than N/2=8.Thus, Pba_mc is set as PBA2=4. In second of condition, logic device is selected to determine that Pba_mc=4 is not less than move_index=2, thus output PBA is set as PBA1=14.

In one aspect, thus it is possible to vary PBA1 to be compared (for example, PBA1 by first condition with N/2>=N/2)).

Fig. 7 shows the operation of the addressing logic device of the example values with PBA and moving index variable, wherein meeting First condition is (for example, PBA2<N/2) and meet second condition (for example, PBA_mc<Move_index) so that correct PBA It is PBA2 or slot 4.Figure 70 0 shows that physical block address (PBA) memory in the different time stage (for example, CF0 to CFn) reflects It penetrates.Logic device is selected to be operated using most latter two memory mapping (CFn and CFn-1).Input variable includes moving index (move_index=5), the quantity (N=16) of the entry in PBA map, this status (L=8) replaced and the global position replaced (G=1).Though it is shown that variables L and G, they can be used for selecting in logic device or being not used in selection logic device In.Since PBA2 is the slot exchanged --- since it is less than moving index (for the example, move_index=5), So selection logic device effectively determines PBA2 correctly and selects it.More specifically, in the first condition, selection is patrolled It collects device and determines that PBA2=4 is less than N/2=8.Thus, Pba_mc is set as PBA2=4.In second of condition, logic is selected Device determines that Pba_mc=4 is less than move_index=5, thus output PBA is set as PBA2=4.

Fig. 8 shows the operation of the addressing logic device of the example values with PBA and moving index variable, wherein meeting First condition is (for example, PBA2<N/2) and meet second condition (for example, PBA_mc<Move_index) so that correct PBA It is PBA1 or slot 5.Figure 80 0 shows that physical block address (PBA) memory in the different time stage (for example, CF0 to CFn) reflects It penetrates.Logic device is selected to be operated using most latter two memory mapping (CFn and CFn-1).Input variable includes moving index (move_index=2), the quantity (N=16) of the entry in PBA map, this status (L=8) replaced and the global position replaced (G=1).Though it is shown that variables L and G, they can be used for selecting in logic device or being not used in selection logic device In.Since PBA2 is the slot (for example, slot 10) not exchanged --- since it is more than moving index (for the example, move_ Index=2), so to select logic device to effectively determine PBA2 incorrect and select it to know for correct PBA1.More For body, in the first condition, logic device is selected to determine that PBA2=10 is not less than N/2=8.Thus, Pba_mc is set as PBA1=5.In second of condition, logic device is selected to determine that Pba_mc=5 is not less than move_index=2, thus will be defeated Go out PBA and is set as PBA1=5.

Fig. 9 shows the operation of the addressing logic device of the example values with PBA and moving index variable, wherein discontented Sufficient first condition is (for example, PBA2<N/2) and second condition is unsatisfactory for (for example, PBA_mc<Move_index) so that correct PBA be PBA2 or slot 10.Figure 90 0 shows that the physical block address (PBA) in the different time stage (for example, CF0 to CFn) is deposited Reservoir maps.Logic device is selected to be operated using most latter two memory mapping (CFn and CFn-1).Input variable includes movement Index the complete of (move_index=6), the quantity (N=16) of entry in PBA map, this status (L=8) of displacement and displacement Office position (G=1).Though it is shown that variables L and G, they can be used for selecting in logic device or being not used in selection logic In device.Since PBA2 is the slot (for example, slot 10) exchanged --- since PBA1 is exchanged to PBA2 (move-index =6 are more than PBA1=5), so selection logic device effectively determines PBA2 correctly and selects it.More specifically, In a kind of condition, logic device is selected to determine that PBA2=10 is not less than N/2=8.Thus, Pba_mc is set as PBA1=5. In two kinds of conditions, logic device is selected to determine that Pba_mc=5 is less than move_index=6, thus output PBA is set as PBA2 =10.

Accumulation state sample calculation

Figure 10 is according to the block diagram of the accumulation state calculation block 1000 of one embodiment of the disclosure, and it includes can scheme The bitonic network 1002 and bitonic sorting device 1004 used in 2 address mapping system.Accumulation state calculation block 1000 also includes Mapping block 1006 is accumulated, accumulation mapping block 1006 can adjust net with some initial mappings of generation/execution and via feedback reception is double Next output of network 1002.Time-varying network bitonic network 1002 can also be the main bitonic network in the system, receive tired The output of product mapping block 1006 and state of a control (cs) and generate new accumulation mapping.Bitonic sorting device 1004 receives new tired Product maps and determines that being mapped to new accumulation from initial build maps required switch setting (for example, accumulation state of a control Or CCS2).

In one aspect, at any given time, system can store the last two values of CCS (for hardware or access Access in network determines) and CS current value (for moving).So in one example, state of a control memory is only big About 960 (for example, 320x 3).In this case, it is possible to need the global map position for preserving these three mappings (that is, three A more positions).

Use (described in the discussion of figure 4 above) for the bitonic network compared with Benes networks, bitonic network There can be log2 (L/2) * (log2 (L/2)+1)/2*L/2 switch, and Benes networks can have 2*log2 (L/2) * L/ 2 switches.For example, value=32 of L so that L/2=16, Benes network can be with 8 (=2*log2 (16)) a switches Grade, wherein each grade is made of a switches of 16 (=L/2).In this case, bitonic network have 20 (=4* (4+1)/2 (= Log2 (16) * (log2 (16)+1)/2) a switch grade, wherein each grade is made of a switches of 16 (=L/2).Therefore, double tune Network may need more assembly lines to realize an address search of a cycle.Therefore, in one aspect, bitonic network Required 2 quantity for multiplying 2 switches can be thus 320, and in contrast, Benes networks are 128, still very little.At one Aspect, there are two 1 bit multiplexed devices for each switch tool, and each switch needs 3 doors (2 AND gate and 1 OR). Therefore, it appears that can use about 2000 doors relative to about 700 doors (accurately calculate be 6 doors of 320x relative to 128x 6 doors) realize each network.In one aspect, this may lead to 4000 doors of bitonic network, relative to Benes 1400 doors of network.However, for bitonic network, firmware may be much simpler.

The aspect of bitonic sorting device and bitonic network will be described in further detail below.In one aspect, both parts can With the Random Maps to generate for wear leveling that work together, while it being also provided back to the path of any one given mapping, Which physical address is any logical address can be mapped to to accurately determine later.In one aspect, bitonic network works To generate Random Maps, and the work of bitonic sorting device is to generate " key " (for example, accumulation state of a control or CCS) to return to later Random Maps.

Figure 11 is the figure according to the bitonic network 1100 of one embodiment of the disclosure.In the embodiment illustrated, double It is the network that 8 with 8 inputs and 8 output multiply 8 types to adjust network 1100.In other embodiments, bitonic network can be with Outputting and inputting with different number.Bitonic network 1100, which includes 24 2, multiplies 2 switch (Sn) 1102, wherein each switching 1102 in by configuring 1102a or cross-over configuration 1102b.By configuring in 1102a, corresponding input is connected to corresponding It exports (for example, A is transferred to A ' and B is transferred to B ').In cross-over configuration 1102b, input is connected to the output (example of non-corresponding Such as, A is transferred to B ' and B is transferred to A ').Each switch 1102 receives the control input " C " for determining switchgear distribution.

In operation, bitonic network 1100 can receive 8 inputs (it can be the first randomly ordered list) and each The switch of switch 1102 setting (it can be random switching setting), and bitonic network 1100 can be set using random switching and The displacement (for example, first randomly ordered list) of input is determined, wherein displacement (output) is the second randomly ordered list.At one Aspect, 8 inputs or the first randomly ordered list can be initial build state of a control (CCS) or subsequent CCS.A side Face can be set according to current state of a control (CS) come configuration switch.

Figure 12 is according to the figure of the bitonic sorting device 1200 of one embodiment of the disclosure, and bitonic sorting device 1200 includes row Sequence device table 1202 and comparative type table 1204.Bitonic sorting device can have log2 (L/2) * (log2 (L/2)+1)/2*L/2 Comparator.Such as L=8, thus L/2=4.In this case, bitonic sorting device can have six grades of comparators, wherein Log2 (8) * (log2 (8)+1)/2=3* (3+1)/2=6, every grade is made of 4 (=L/2) a comparators.

Comparative type table 1204 or " cmp_type " are the matrixes for having following size：Wherein capable quantity is equal to log2 (L/2) * (log2 (L/2)+1)/2 (for example, equal to comparator grade quantity=6), and arrange quantity be equal to L/2 (for example, Equal to quantity=4 of the comparator in each grade).Therefore, for L=8, in Working Examples, cmp_type 1204 be the matrix that size is 6x 4.The first row (or in general i-th row) in the cmp_type matrixes 1204 corresponds to The comparator-type of the comparator comparator of i-stage (or in general) of the first order in Figure 120 0.Comparator-type 0 (for example, Row 1, the row 1 of cmp_type 1204) mean comparator 1206 (" Comp Type 0 ") using two inputs (A, B) and is in Existing two outputs (out1, out2) so that the first output be among being inputted at two smaller number (for example, out1=minimum (A, B) or Min (A, B)), and second output be at two input among bigger number (for example, out2=maximum (A, B) Or Max (A, B)).This is shown with the down arrow in Figure 120 0.In one aspect, if input A is less than input B, comparator 1206 give the carry-out bit (for example, " c ") equal to 1.On the other hand, occur (for example, out1=B, out2 if exchanged =A), then comparator can also provide the carry-out bit equal to 1, if not exchanging generation (for example, out1=A and out2= B), then comparator can also provide the carry-out bit equal to 0.This respect is not shown in Figure 120 0.

Comparator-type 1 (for example, row 1, row 2 of cmp_type 1204) means (" the Comp Type of comparator 1208 1 ") two inputs (A, B) are used and two outputs (out1, out2) are presented so that the first output is among being inputted at two The number (for example, out1=maximum (A, B) or Max (A, B)) of bigger, and the second output is smaller among being inputted at two Number (for example, out2=minimum (A, B) or Min (A, B)).This in Figure 120 0 to upward arrow to show.A side Face, if input A is more than input B, comparator 1208 gives the carry-out bit (for example, " c ") equal to 1.On the other hand, (for example, out1=B, out2=A) occurs if exchanged, then comparator 1208 gives the carry-out bit equal to 1, if do not handed over Raw (for example, out1=A, out2=B) is changed, then comparator 1208 gives the carry-out bit equal to 0.This respect is not being schemed It is shown in 1200.

Sorting unit table 1202 or " sorter_ind " are the matrixes for having following size：Wherein capable quantity is equal to log2 (L/2) * (log2 (L/2)+1)/2 (for example, equal to quantity or 6 of the grade of comparator), and the quantity arranged is equal to L (for example, waiting In the quantity or 8) of the input of each grade of comparator.Therefore, for L=8, in Working Examples, sorter_ind 1202 be the matrix that size is 6x 8.The first row (or in general i-th row) in the sorter_ind matrixes 1202 is corresponding In the port numbers of the input for each grade for being connected to bitonic network.

In one aspect, the then monotone decreasing if sequence is increased monotonically, or if it can be by cyclic shift with list It adjusts and is incremented by then monotone decreasing, then sequence can be double adjusts.

In one aspect, bitonic network can have topology identical with bitonic sorting device 1200, in addition to comparator is by having Have control input 2 multiply 2 switches replacement.

Figure 13 is to control shape according to the accumulation being used to determine for LBA to be mapped to PBA of one embodiment of the disclosure The flow chart of the process 1300 of state.In one embodiment, which is determined for address of cache system described herein The accumulation state of a control of any one of system, includes the accumulation state meter of the accumulation state calculation block 204 of such as Fig. 2 and Figure 10 Calculate block 1000.In block 1302, which generates first switch setting at random.In one aspect, generating random number can be used Device sets to generate first switch.In one aspect, it can use above for the control shape in the system described in Fig. 2 and Figure 10 State (CS) sets to generate first switch.In block 1304, which receives the first randomly ordered list and first switch setting. In block 1306, which generates the displacement of the first randomly ordered list using first switch setting, wherein displacement includes the Two randomly ordered lists.In one aspect, which generates the second randomly ordered list.In one aspect, block 1304 and 1306 Action can by Figure 10 bitonic network 1002 or Figure 11 bitonic network 1100 (wherein can by first switch set apply In switch 1102, and the first randomly ordered apply the lists to can be inputted In1 to In8) it executes.

In block 1308, the process is using bitonic sorting come to the second randomly ordered list ordering.In one aspect, the row Sequence can be risen.In one aspect, which can decline.In one aspect, which can be natural order Sequence.In one aspect, which is related to generating natural ordering list.In one aspect, the natural ordering list include from 0 to The number of M-1, wherein M are the quantity to the input of bitonic network.In block 1310, which determines for realizing bitonic sorting Second switch setting, wherein second switch setting limit accumulation state of a control (CCS).In one aspect, 1308 He of block 1310 action can execute by the bitonic sorting device 1004 of Figure 10 or the bitonic sorting device 1200 of Figure 12, wherein second switch " c " carry-out bit of setting corresponding to the comparator (1206,1208) of Figure 12.In block 1312, which uses accumulation control shape State determines the PBA of nonvolatile memory (NVM), to enable the data access of corresponding LBA.In one aspect, block 1312 Action can be executed by the access network 202 of Fig. 2 or the access network 400 of Fig. 4.In one aspect, NVM can be the NVM of Fig. 1 112。

Figure 14 is controlled according to the accumulation being configured to determine for LBA to be mapped to PBA of one embodiment of the disclosure The block diagram of the example hardware realization method of the equipment 1400 of state.Equipment 1400 can be presented as or realize in solid state drive It is interior, in NVM or support wear leveling some other types of memory devices.

Equipment 1400 include host interface (for example, the circuit communicated with host or controller) 1402, storage medium 1404, User interface 1406, memory device (for example, memory circuit of such as NVM) 1408 and processing circuit 1410 are (for example, at least One processor).In various implementations, user interface 1406 can include one of the following or multiple：Keyboard, display Device, loud speaker, microphone, touch-screen display, some other electricity for receiving input from user or being exported to user's transmission Road.

These components (can usually be indicated) coupling via signal bus or other suitable components by the connecting line in Figure 14 It closes each other and/or is placed in and telecommunication each other.Depending on the specific application and overall design constraints of processing circuit 1410, signal Bus can include any amount of interconnection bus and bridge.Signal bus links together various circuits so that host interface 1402, each of storage medium 1404, user interface 1406 and memory device 1408 be coupled to processing circuit 1410 and/or With 1410 telecommunication of processing circuit.The signal bus can also link various other circuit (not shown), such as timing source, periphery Equipment, voltage regulator and electric power management circuit, these are well known in the art, therefore be will not be described again.

Host interface 1402 provides the means communicated with miscellaneous equipment by transmission medium.In one aspect, host interface 1402 can be implemented as the host interface 106 of Fig. 1.

Memory device 1408 can indicate one or more memory devices.In one aspect, memory device 1408 It can be implemented as NVM, the NVM 112 of such as Fig. 1.In one aspect, memory device 1408 can contain production (production) or user data.In some implementations, memory device 1408 and storage device 1404 are embodied as altogether Same memory member.Memory device 1408 can be also used for storing other by some of processing circuit 1410 or equipment 1400 The data that component manipulates.

Storage medium 1404 can represent one or more computer-readable, machine readable and/or processor readable devices, For storing program, such as processor executable code or instruction (for example, software, firmware), electronic data, database or other Digital information.Storage medium 1404 can be also used for the data that storage is manipulated by processor 1410 when executing a program.Storage is situated between Matter 1404 can be any usable medium that can be accessed by general processor or application specific processor, including RAM, NVM, portable Or stationary storage means, light memory device and the various other media that can store, contain or carry program.In one aspect, Storage device 1404 can be implemented as the memory 110 of Fig. 1.

It as example rather than limits, storage medium 1404 can include magnetic storage device (for example, hard disk, floppy disk, magnetic Item), CD (for example, compact disk (CD) or digital versatile disc (DVD)), smart card, flash memory device (for example, card, stick or Keyed actuator), random access memory (RAM), read-only memory (ROM), programming ROM (PROM), erasable PROM (EPROM), electric erasable PROM (EEPROM), register, moveable magnetic disc and for store can by computer access and read Any other suitable medium of the software and/or instruction that take.Storage medium 1404 can be presented as product (for example, computer Program product).As an example, computer program product can include the computer-readable medium in encapsulating material.In view of above, In some implementations, storage medium 1404 can be non-transitory (for example, tangible) storage medium.

Storage medium 1404 may be coupled to processing circuit 1410 so that processing circuit 1410 can be from storage medium 1404 Information is read, and information is written to storage medium 1404.That is, storage medium 1404 may be coupled to processing circuit 1410 so that storage medium 1404 can at least be accessed by processing circuit 1410, including wherein at least one storage medium and processing The example and/or wherein at least one storage medium and processing circuit 1410 of 1410 one of circuit separate (for example, being located at equipment In 1400, outside equipment 1400, be distributed in it is multiple physically etc.) example.

When the program stored by storage medium 1404 is executed by processing circuit 1410, which causes processing circuit 1410 Execute one or more of various functions described herein and/or processing operation.For example, storage medium 1404 can include Such operation is configured to adjust the operation at one or more hardware blocks of processing circuit 1410, and uses them Respective communication protocol is communicated using host interface 1402 with host.

Processing circuit 1410 is commonly available to handle, including executing this program being stored on storage medium 1404.Such as Used herein, term " code " or " program " should be broadly interpreted as including but not limited to instruction, instruction set, number According to, code, code segment, program code, program, programming, subprogram, software module, application program, software application, software Packet, routine, subroutine, object, executable file, execution thread, process, function etc., no matter they be referred to as software, firmware, Middleware, microcode, hardware description language or other.

Processing circuit 1410 is arranged as acquisition, processing and/or transmission data, controls data access and storage, publication order And control other desired operations.In at least one example, processing circuit 1410 can include and be arranged for carrying out by suitable Media provide desired program circuit.For example, processing circuit 1410 can be implemented as one or more processors, one Or multiple controllers and/or be configured to execute executable program other structures.The example of processing circuit 1410 can include logical With processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array (FPGA) or other Programmable logic units, discrete door or transistor logic device, discrete hardware component are designed as executing described herein Function any combination thereof.General processor can include microprocessor and any conventional processors, controller, microcontroller Device or state machine.Processing circuit 1410 is also implemented as the combination of calculating unit, if the combination of such as DSP and microprocessor, Dry microprocessor, the one or more microprocessors in conjunction with DSP core, ASIC and microprocessor or any other quantity are not Same configuration.These examples of processing circuit 1410 are merely to illustrate, and other suitable configurations within the scope of the disclosure It is expected.

According to the one or more aspects of the disclosure, processing circuit 1410 is applicable to execute equipment described herein The feature of any one or all, process, function, any one or all of operation and/or routine.For example, processing circuit 1410 are configurable to execute any step, function and/or the process about described in Fig. 1-Figure 13 and Figure 15-Figure 30.As herein Used in, the term " being suitable for " about processing circuit 1410 can refer to processing circuit 1410 and be arranged to, is presented as, be real It is now and/or is programmed to carry out according in the particular procedure of various features described herein, function, operation and/or routine It is one or more.

Processing circuit 1410 can be application specific processor, such as application-specific integrated circuit (ASIC), be used as executing combining and scheme Any one device (for example, structure) of operation described in 1- Figure 13, Figure 15-Figure 30.Processor circuit 1410 is used as executing One example of the device of wherein discribed function.In various implementations, processing circuit 1410 can be incorporated to the control of Fig. 1 Device 108 or NVM 112 (for example, the processor wherein contained) processed, Fig. 2 accumulation state calculation block 204 or access network 202, The bitonic network 1002 or bitonic sorting device 1004 of Figure 10, the bitonic network 1100 of Figure 11 or the bitonic sorting device 1200 of Figure 12 Function.

According at least one example of equipment 1400, processing circuit 1410 can include one of the following or multiple：With In the circuits/modules 1420 of generation first switch setting at random, for receiving the first randomly ordered list and first switch setting Circuits/modules 1422, the circuits/modules for setting the displacement to generate the first randomly ordered list using first switch 1424, the circuits/modules 1426 for being ranked up to the second randomly ordered list using bitonic sorting, for determination be used for Realize the circuits/modules 1428 of the setting of the second switch of bitonic sorting or for non-to determine using accumulation state of a control The PBA of volatile memory (NVM) to enable the data access of corresponding LBA circuits/modules 1429.

In various implementations, it is used to generate the circuits/modules 1420 of first switch setting at random, for receiving first It is the circuits/modules 1422 of randomly ordered list and first switch setting, random to generate first for being set using first switch The circuits/modules 1424 of the displacement of sorted lists, for what is be ranked up to the second randomly ordered list using bitonic sorting Circuits/modules 1426 for realizing the circuits/modules 1428 of the setting of the second switch of bitonic sorting or are used for determination In determining the PBA of nonvolatile memory (NVM) to enable the electricity of the data access of corresponding LBA using accumulation state of a control Road/module 1429 can correspond at least partially to Fig. 1 controller 108 or NVM 112 (for example, the processing wherein contained Device), the accumulation state calculation block 204 of Fig. 2 or access network 202, the bitonic network 1002 of Figure 10 or bitonic sorting device 1004, figure The function of 11 bitonic network 1100 or the bitonic sorting device 1200 of Figure 12.

As the above mentioned, when the program stored by storage medium 1404 is executed by processing circuit 1410, the program Processing circuit 1410 is caused to execute one or more of various functions described herein and/or process operation.For example, when should When program is executed by processing circuit 1410, which may cause processing circuit 1410 to execute herein with reference to Fig. 1-Figure 13, Figure 15- Various functions, step and/or process in Figure 30 described in various embodiments.Go out as shown in Figure 14, storage medium 1404 can be with Including one of the following or multiple：For generating the code 1430 of first switch setting at random, being arranged at random for receiving first The code 1432 of sequence table and first switch setting generates setting for the first randomly ordered list for being set using first switch The code 1434 that changes, the code 1436 for being ranked up to the second randomly ordered list using bitonic sorting, for determining For realizing the setting of the second switch of bitonic sorting code 1438 or for using accumulation state of a control come determine it is non-easily The PBA of the property lost memory (NVM) to enable the data access of corresponding LBA code 1440.

In various implementations, it can execute or in other ways using the generation for generating first switch setting at random Code 1430, for receiving code 1432 that the first randomly ordered list and first switch set, for using first switch to set Come generate the first randomly ordered list displacement code 1434, for using bitonic sorting come to the second randomly ordered list into The code 1436 of row sequence for realizing the code 1438 of the setting of the second switch of bitonic sorting or is used for for determination Determine the PBA of nonvolatile memory (NVM) to enable the code of the data access of corresponding LBA using accumulation state of a control 1440 so that provide function described herein for circuits/modules：Circuits/modules for generating first switch setting at random 1420, for receiving the circuits/modules 1422 of the first randomly ordered list and first switch setting, for being set using first switch It is fixed come generate the displacement of the first randomly ordered list circuits/modules 1424, for using bitonic sorting come to the second random row Circuits/modules 1426 that sequence table is ranked up, setting for determining the second switch for realizing bitonic sorting circuit/ Module 1428 or for determining the PBA of nonvolatile memory (NVM) to enable corresponding LBA using accumulation state of a control Data access circuits/modules 1429.

It is mapped using the local address of the state of a control of pre-stored

Figure 15 be according to another block diagram of the system 1500 for local address mapping of one embodiment of the disclosure, System 1500 includes to access the read-only storage of one or more of network 1502 and the accumulation state of a control value for storing precomputation Device (ROM) (1504a, 1504b, 1504c).System 1500 also include backstage mapping scheduler device 1508 and mapping status generate and Change block 1510.In one aspect, it accesses network 1502 and ROM (1504a, 1504b, 1504c) can be with hardware realization (example Such as, the ultralow delay with the delay of 3 cycle pipelines, low logic device and memory are equivalent to less than 10000 logic gates) And the remainder of system 1500 can be realized with firmware.In operation, the system that the block of system 1500 can be similar to Fig. 2 Those of 200 blocks operate.However, the main distinction in system 1500 is that accumulation state is to use main bitonic network or other Suitable network carrys out off-line calculation, then stores (for example, in table) in ROM (1504a, 1504b, 1504c).A side Face, compared with the system of Fig. 2, this method can be related to using a small amount of annex memory.

The nonvolatile memory of block 1504a representative storage CCS values (for example, CCS1 and CCS2) be (such as CCS_ROM's ROM).Block 1504b represents the nonvolatile memory (ROM of such as CS_ROM) of storage CS values (for example, cs1 and cs2).Block 1504c represents nonvolatile memory (for example, programming ROM of such as USE_PROM), effectively store CS_ROM and Which of CCS_ROM lines are currently being used, to prevent there are power down.Effectively, USE_PROM can be used for depositing non-volatile State of a control is preserved in memory space, to restore in the case of power down.Stored state of a control value can include MOVE_ INDEX、cs2、ccs1、ccs2、bg_transfer_address1、bg_transfer_address2、bg_transfer_ Status and/or ROM_row_index.In one aspect, once power recovery, system 1500 can use USE_PROM (examples Such as, using indicator) entry and state of a control execute consistency check, and after restoring mapping status and continuing any interruption Platform transmits.

Figure 16 a be one embodiment of the disclosure the system that can be used for storing Figure 15 in the state of a control (CS) that uses The schematic diagram of the ROM (CS_ROM) 1600 of value.Figure 16 a show the nonvolatile memory that can be used for storing state of a control value A kind of possible realization method.On the other hand, other realization methods can also be used.

Figure 16 b be one embodiment of the disclosure the system that can be used for storing Figure 15 in the accumulation state of a control that uses (CCS) schematic diagram of the ROM (CCS_ROM) 1602 of value.Figure 16 b, which are shown, can be used for storing the non-easy of accumulation state of a control value A kind of possible realization method of the property lost memory.On the other hand, other realization methods can also be used.

Figure 16 c be one embodiment of the disclosure the system that can be used for storing Figure 15 in the state of a control (CS) that uses The schematic diagram of the PROM (USE_PROM) 1604 of value.More specifically, USE_PROM 1604 can be used in non-volatile memories Storage and the relevant index in current location or placeholder information in CS_ROM and CCS_ROM in device space, in the feelings of power down Restore under condition.Figure 16 c, which are shown, can be used for storing index information into a kind of possible realization into the nonvolatile memory of ROM Mode.On the other hand, other realization methods can also be used.

In one aspect, whenever mapping is used, ROM_row_index can be increased by 1 by the system 1500 of Figure 15, wherein ROM_row_index can be the address of CS_ROM and CCS_ROM.System can also program 1 entry in USE_PROM For 1 to indicate that this bar line is used.

Figure 17 is the flow chart according to the process 1700 for wear leveling of one embodiment of the disclosure.In a reality It applies in example, it can be by any one of the wear leveling system 1600 or other wear leveling systems described herein in Figure 16 Implementation procedure 1700.

In block 1702, the process by multiple accumulation state of a controls (each of which instruction physical block address (PBA) with patrol Collect the state of the Random Maps between block address (LBA)) and the storage of multiple state of a controls is in the nonvolatile memory.Certain The action of aspect, block 1702 can be realized by controller 108, or combine host by controller 108 as shown in Figure 1 102 realize.In some aspects, block 1702 can be by comprising in ROM 1604a, ROM 1604b, ROM 1604c, Figure 16 The wear leveling system 1600 of Figure 16 of other ROM, the controller 108 of Fig. 1 and/or any combinations of those components are realized. In one aspect, block 1702 can be realized by ROM 1604a, ROM 1604b and/or controller 108.

In block 1704, the process be based on multiple accumulation state of a controls by logical block address (LBA) with being converted to physical block Location (PBA).In some aspects, the action of block 1704 can be realized by controller 108, or pass through control as shown in Figure 1 Device 108 is realized in conjunction with host 102.In some aspects, block 1704 can by include access network 1602 Figure 16 loss Any combinations of equal balance system 1600, the controller 108 of Fig. 1 and/or those components are realized.In one aspect, block 1704 can To be realized by accessing network 1602.

In block 1706, which exchanges the PBA for distributing to preselected LBA based on multiple state of a controls.Certain The action of aspect, block 1706 can be realized by controller 108, or combine host by controller 108 as shown in Figure 1 102 realize.In some aspects, block 1706 can pass through the wear leveling system of Figure 16 comprising backstage exchange scheduler 1608 1600, any combinations of the controller 108 of Fig. 1 and/or those components are realized.In one aspect, block 1706 can be by rear Platform exchanges scheduler 1608 to realize.

In one aspect, accumulation state of a control includes the first accumulation state of a control and the second accumulation state of a control, wherein controlling State processed include the first state of a control and the second state of a control, wherein second accumulation state of a control be the first accumulation state of a control and The function of second state of a control.Above with respect to Fig. 2 and below in relation to Figure 12 be more fully described accumulation state of a control (for example, CCS1 and CCS2) and state of a control (for example, cs1, cs2).

In one aspect, which is further included in after the PBA for exchanging pre-selected number, and first memory is mapped Second memory mapping is changed into, wherein each in first memory mapping and second memory mapping includes preselected number The PBA of amount.In one aspect, this can be executed by the mapping status block 1610 of Figure 16.

In one aspect, the PBA for distributing to preselected LBA is exchanged included in non-volatile memories based on state of a control PBA is exchanged after the access of the pre-selected number of the nonvolatile memory of device system.In one aspect, the visit of pre-selected number Ask it can is 100 times of nonvolatile memory write-ins.

In one aspect, process 1700 also includes to generate the first PBA candidates from LBA using first function, uses the second letter It is candidate that number from LBA generates the 2nd PBA, and based on exchanging and be stored in the backstage for the data being stored at the first PBA candidates The information of the backstage exchange correlation of data at 2nd PBA candidates, selects the first PBA candidate or the 2nd PBA candidates are used for data It accesses.In one aspect, these actions can be executed by the access network 1602 of Figure 16 or the access network 400 of Fig. 4.At one Aspect, at least one of first function or second function include to be held by least one of multistage interconnection or block cipher Capable function.In one aspect, the sequence for the displacement that the second accumulation state of a control reflection accumulates state of a control for realizing first Switch setting, wherein generating the displacement using the second state of a control.

Figure 18 is to access network 1800 according to the block diagram of another access network 1800 of one embodiment of the disclosure and wrap Containing the selection logical block 1802 that can be used in the address mapping system of Figure 15.In one aspect, accessing network 1800 can be with It is used as accessing network 1502 in the system of Figure 15.System 1800 also includes the first bitonic network 1804 and the second bitonic network 1806.System 1800 can be operated substantially identically as the system of Fig. 4 400, in addition to be from ROM (for example, 1504a, 1504b, 1504c) rather than receive accumulation state of a control value (CCS1, CCS2) from online accumulation state of a control (block 204 of such as Fig. 2).

The above-described system and method for executing local address mapping can interweave with the local and overall situation is used It is used in combination using the wear leveling scheme of random address mapping.Following sections describes this method.

It is local/global to interweave

Figure 19 is the block diagram according to the indirect table 1900 of one embodiment of the disclosure.For example, as depicted in figure 19, In the driver with the M page/sector, indirect table has M entry.In this case, each entry is N, Middle N is log2 (M).For the 2TB drivers with 512 byte pages, M=2x 10^12B/512B=3.9x10^9, thus N Equal to 32.Therefore, the required memory in the position of table can be M x log2M=125GB (~15GB).Use the frequency of table Similar space (~15GB) can be consumed.Therefore, for the metadata, total demand is about 30GB.In some realization methods In, metadata may must be replicated with 2+1 redundancies (two plus one redundancy), to increase complexity To 90GB.In this case, which accounts for about the 4.5% of disk space.Therefore, this method is usually unreal Border.

Figure 20 be according to one embodiment of the disclosure for using it is local and it is global interweave reflected to execute random address The block diagram for the overall system penetrated.System 2000 includes look-up table 2002, and it is 2^G and width that look-up table 2002, which can be used for storing depth, Degree is the 2^G entry of G.System 2000 can also include the multistage interconnection for the displacement that may be used to provide data acquisition system (MIN) 2004 and can be used for control MIN 2004 state of a control block 2006.System 2000 shows overall framework, By the way that N logical address spaces are mapped to N physical spaces by the address bit division position of position G and N-G position first.It is logical Often, any G position in N number of position can be selected using another fixed network.In such a scenario, fixed network can letter It is singly the fixed and arranged of line to reach specific network.Compared with multi-stage programmable interference networks, fixed network may not It is programmable.For simplicity, selected G position is N number of highest effectively position (significant) (MSB). Therefore, system can execute mapping in block 2002 to 2^G entry, and to N-G position execution position displacement in block 2004. G position can be mapped using 2^G entry mapping table 2002.In one aspect, mapping can be executed so that there are one-to-one Unique mapping, and input not equal to output.Moreover, in one aspect, G is selected to make 1<=G<=N.In one aspect, G <=6 the case where may be of special interest.If G=N, such case can be equal to conventional mapping table method.

In one embodiment, global map can meet one or more properties.For example, in one aspect, the overall situation is reflected It can be one-one function to penetrate.On the other hand, can execute global map makes input not equal to output.In another side Face can execute and exchange so that the global map of digital (k) is equal to kk, and the global map of kk is equal to k.Therefore, it is used for the overall situation The suitable function of mapping can include bit reversal mapping, random exchange, certainty exchanges and other suitable functions.It can select It selects bit reversal mapping and is used for simple hardware implementation mode.If using table, the largest amount of required table can be 2^G A entry, wherein each entry has the width of G position.Since G is not more than 7 in this example, so table method is also suitable 's.

In one embodiment, local mapping can meet one or more properties.For example, in one aspect, locally reflecting It can be one-one function to penetrate.For the suitable function that locally maps can include that certainty is mapped and/or reflected at random It penetrates.In one aspect, Random Maps can be selected.Certainty maps or Random Maps can use table or Omega network, butterfly Network, Benes networks or other suitable networks are realized.In one aspect, selection Benes networks are (for example, MS master-slave Benes Network) because it has for calculating the required minimal complexity of on off state.In the network, bitonic sorting can be It is realized on main Benes networks in sequence with certain characteristics, to export the on off state for subordinate Benes networks. In one embodiment, local address mapping can be used above in association with appointing in the local address mapping scheme described in Fig. 1-Figure 18 What one executes.

In one embodiment, the wear-leveling algorithm realized using random address mapping can be related in address space Middle operation, setting address space partition zone and the local in address space and global intertexture.In one aspect, wear leveling is calculated Method can be related to being mapped to the gradual certainty conversion that another memory maps from a memory.

Figure 21 is to be reflected according to the use global map of one embodiment of the disclosure and local intertexture to execute random address The flow chart for the process penetrated.In one embodiment, which can be used for appointing for the Random Maps system described herein Wear leveling in what one or the mapping of other random address.In block 2102, the process identifier nonvolatile memory (NVM) Physical address space in several positions (N).In block 2104, in N number of position of the process choosing physical address space at least One (G) interweaves for global, and wherein G is less than N.In block 2106, which determines that several positions for subtracting G (N-G) equal to N are used for It is local to interweave.

In block 2108, which maps G position using the mapping function for global intertexture.In one embodiment In, the mapping function can be bit reversal mapping function, random commuting mappings function, certainty commuting mappings function and/or its Its suitable mapping function.

In block 2110, the process is using the interleaving function for locally interweaving come a position (N-G) that interweaves.Implement at one In example, interleaving function being to determine property interleaving function, random interleaving function and/or other suitable interleaving functions.At one In embodiment, interleaving function can use Omega network, butterfly network, Benes networks, MS master-slave Benes networks and/or other Suitable interleaving function is realized.

In some embodiments, it is bit reversal mapping function for the mapping function of global map, and interleaving function makes It is realized with MS master-slave Benes networks.In one such embodiment, G position is that the highest of the physical address space of NVM is effective Position, and bit reversal mapping function be related to invert G position in each.

In block 2112, which generates the mapping of G position of containment mapping and the combination of (N-G) a of intertexture. In one embodiment, the mapping of combination constitutes the physical address of mapping (see, for example, following Figure 25 that will be discussed in more detail In row 2506).

Figure 22 is bit reversal (G position) according to one embodiment of the disclosure using global map and locally interweaves Replace the block diagram that (N-G position) executes the system of random address mapping.System 2200 includes that can be used for reverse logic address The bit reversal block 2202 of selected position.In one aspect, for example, as described in the block 2108 in Figure 21, bit reversal block 2202 are used for mapping G position for the mapping function of global map, and wherein mapping function is bit reversal function.System System 2200 also includes the multistage for the displacement (displacement of the selected position of such as logical address) that may be used to provide data acquisition system Interference networks (MIN) 2204.In one aspect, as described in the block of Figure 21 2110, MIN2204 is used for for this The interleaving function that ground interweaves is come the N-G position that interweave.System 2200 also includes the state of a control block that can be used for controlling MIN 2204 2206。

The system 2200 also includes processor 2208, and processor 2208 can be used for controlling and/or execution position inverse block The calculating of 2202 and MIN 2204.Under the scene, processor 2208 refer to be able to carry out series of instructions any machine or The selection of logic device, and be considered as including but not limited to general purpose microprocessor, special microprocessor, central processing list First (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), signal processor, microcontroller and other suitable Circuit.In addition, it is to be understood that term processor, microprocessor, circuit, controller and other this terms refer to energy Enough execute logic, order, instruction, software, firmware, function or other such information any kind of logic device or electricity Road.In one aspect, as described in the frame of Figure 21 2102, processor 2208 can be used for identifying nonvolatile memory (NVM) several positions (N) in physical address space select at least one of positions N of physical address space position (G) to be used for entirely Office interweaves, wherein as described in the frame 2104 of Figure 21, G is less than N, and/or as described in the block 2106 in Figure 21, determine etc. Several positions for subtracting G (N-G) in N interweave for local.In one aspect, as described in the block 2112 in Figure 21, processor 2208 can be also used for generating the combinatorial mapping of (N-G) a of G position of containment mapping and intertexture.In one embodiment, Combinatorial mapping is alternatively generated by block 2202 and/or block 2206.

In a simple examples for illustrating address spatial operation, as shown in Figure 22, it is assumed that the number of the page in NVM It is 16 (that is, M=16 pages) to measure (M).In this case, the quantity (N) of address bit may be calculated the ground N=log2 (M)=4 Location position.In this case, the parameter of configuration is for example following：G=1 (2^G subregion), L=N-G=4-1=3 (3x3 network). The simple example will be realized by Figure 23 to Figure 25.

Figure 23 is the example shown according to the use of one embodiment of the disclosure to the global map of the bit reversal of G position Table 2300.In one aspect, the table 2300 of Figure 23 can be considered as the example of the global map shown in the block 2202 of Figure 22. In the simple example of continuation, G is 1 (that is, most significant bit (MSB) of 4 address bits).In the example of Figure 23, table 2300 show the initial address in left column, are shown with the decimal system and binary system.Table 2300 is also shown in use to G position Final address after the global map of the bit reversal of (that is, MSB) in the right row of address, is shown with the decimal system and binary system. As visible in fig 23, the global map using bit reversal is one-one function, and is inputted not equal to output.The realization side Formula is consistent with the one or more of possible design feature discussed above.

Figure 24 is the example locally to interweave shown according to the use of one embodiment of the disclosure to the displacement of N-G position Table 2400.Interweave more particularly, for the local of address bit, it is assumed that 3 address bits ([x2x1x0]) are replaced into [x2x0x1].In the example of Figure 24, table 2400 shows the initial address in left column, is shown with the decimal system and binary system.Table 2400 also show the final address in the right row of address after the part mapping using selected displacement, with the decimal system It is shown with binary system.The use of the local intertexture of displacement is one-one function as visible in fig. 24.The realization method is with more than The one or more of the possible design feature discussed is consistent.In one aspect, the table 2400 of Figure 24 can be considered as Figure 22's The example locally mapped shown in block 2204.

Figure 25 is the global map using bit reversal for showing one embodiment according to the disclosure and the sheet using displacement The exemplary table 2500 that ground interweaves.Most left row 2502 show original address with the decimal system.Middle column 2504 illustrates only the overall situation The effect of mapping/intertexture, and match the final row (for example, result) of Figure 23.Most right row 2506 are shown using bit reversal Global map and both local intertexture using selected displacement caused by physical address.The simple examples show figure A kind of possible operation of the system and method for 20- Figure 22.More specifically, the table 2500 of Figure 25 can be considered as by Figure 22's Manage device 2208, the example for the combinatorial mapping that any combinations of block 2202 and 2204 generate.

Figure 26 is to can be used for executing local intertexture (for example, the block in Figure 22 according to one embodiment of the disclosure 2204) block diagram of multistage interconnection network (MIN) 2600.For generating being somebody's turn to do for Random Maps from logical space and physical space The MIN methods multistage interconnection or MIN of 2^N entry (for example, with) may may very big but reality due to storage size Now get up expensive.

More specifically, in one aspect, mobile project must be based on the particular order defined by mapping to complete.It is right It in reading process, must be used to distinguish which chip selection (CS), need to safeguard another table and often of 2^N entry The width of a entry.In contrast, CS chip memory devices are equal to log2 (N) * N/2 for Omega network, for Benes nets Network is equal to log2 (N) * N.

Figure 27 is the frame that can be used for executing the butterfly MIN2700 locally to interweave according to one embodiment of the disclosure Figure.For generating the MIN methods of Random Maps (for example, the butterfly about 2^N entry from logical space and physical space MIN it is) suitable multistage interconnection, can be used for the MIN 2004 of the MIN 2204 or Figure 20 of such as Figure 22.

In the case of insignificant equal to 1 of the shuffling of physical space (shuffle), network is not needed, because being easy Find out mapping.In this case, shuffle address can be limited to the left loopy moving of physical address, be binary-coded character String.Consider that for example the stage 1 arrives M.In stage k, the physical address of logical address by (xn-1, xn-2, xn-3, xn-k ..., x1, X0 it) gives, is converted to (via reversion) (Xn-1, Xn-2, Xn-3, Xn-k-1 ... x1, x0).In one aspect, another is more Simple situation can include that the butterfly displacement for wherein exchanging MSB with LSB, any of which i-th bit and position 0 (for example, LSB) are handed over The super displacement that the replacement displacement changed and any of which i-th bit are exchanged with MSB.On the other hand, it is local interweave can be related to pair Any switch combination is used in each stage.

In general, MIN can be used for one in both of which.For example, in route pattern, the switchgear distribution in MIN is The desired mapping from input port to output port is realized in one or many transmission.In this case, each defeated Inbound port uses the word of multiple positions (such as m), and each output port provides m words, there are it is N number of input with it is N number of defeated Go out.In second mode --- in intertexture pattern, the switchgear distribution in MIN is to use random seed.This is generated in single transmission Random Maps from input port to output port.At several aspects, interleaver described herein or intertexture can interweave MIN is used in pattern, with the preselected position that interweaves as desired.

Figure 28 is to can be used for executing the Benes MIN 2800 locally to interweave according to one embodiment of the disclosure Block diagram.For generating the MIN methods of Random Maps from logical space and physical space (for example, about 2^N entry Benes MIN) it is suitable multistage interconnection, it can be used for the MIN 2004 of the MIN 2204 or Figure 20 of such as Figure 22.

Figure 29 is to can be used for executing the Omega MIN 2900 locally to interweave according to one embodiment of the disclosure Block diagram.For generating the MIN methods of Random Maps from logical space and physical space (for example, about 2^N entry Omega MIN) it is suitable multistage interconnection, it can be used for the MIN 2004 of the MIN 2204 or Figure 20 of such as Figure 22. In one aspect, Omega network can only be capable of providing the subset for being possible to displacement of switch, and Benes networks can energy All possible displacement is enough provided.In one aspect, it if necessary to desired displacement, then is likely difficult to solve Benes networks Chip selection setting.In order to solve the problems, such as that this is potential, a realization method of Benes networks is related to setting chip at random Selection setting, this can make chip selection algorithm much simpler.That is, when generation chip selection setting reduction calculates at random Between demand and/or solve chip selection and set required calculatings to challenge.

Figure 30 shows (8x8) that can be used for executing the modification locally to interweave of one embodiment according to the disclosure The block diagram of Omega MIN 3000.In general, Omega network is to determine that (N × N) of size is multistage interconnected according to 2 integer power Network.Thus, Omega network has the sizes such as N=2,4,8,16,32,64,128.In addition, the quantity of the grade in Omega network L is equal to log2 (N), and the quantity of (2 × 2) switch of each grade is equal to N/2.

Omega network 3000 is (8 × 8) network, and the network is in eight input terminal A [0:7] eight input values are received at, And eight input values are mapped to eight leading-out terminal B [0:7].Each input value can be any suitable value, such as singly There are one soft value (such as Viterbi logarithms of hard decision position and at least one confidence value position for a position, Duo Gewei, sampling or tool Likelihood ratio (LLR) value).Eight input values are mapped to eight leading-out terminals, wherein i using log2 (8)=3 configurable grade i =1,2,3, each of which includes 8/2=4 (2 × 2) a switch.

Each grade i is via realizing the fixation interconnection system shuffled to the perfection of eight input values (for example, 3002,3004 and 3006), eight input values are received or in the case of grade 1 from input terminal A [0 from grade before:7] eight inputs are received Value.Perfection, which is shuffled, to be comparable to (i) and is divided to the identical heap in position two and (ii) by two identical heaps with identical side deck Formula is washed together so that the board in the first heap and the alternate process of board from the second heap.

For example, grade 1 via fixed interconnection system 3002 from input terminal A [0:7] eight input values are received.Fixation mutually links System 3002 is by will be in input terminal A [0:7] eight input values received at are divided into corresponding to input terminal A [0:3] first Gather and correspond to input terminal A [4:7] second set, execution shuffle to the perfection of eight input values.Similarly, fixed mutual It links 3004 execution of system to shuffle to the perfection of the output of the switch from grade 1, and the output shuffled is provided to the switch of grade 2, And the fixed execution of interconnection system 3006 shuffles to the perfection of the output of the switch of grade 2, and switchs what offer was shuffled to grade 3 Output.

In addition to receiving eight input values, each configurable grade i receives four from control signal storage (for example, ROM) Control signal Ci [0:3], wherein different one of four 2 × 2 switches in each position configuration stage of four control signals.Cause And the switch of grade 1 is configured based on the value of control bit C1 [0], C1 [1], C1 [2] and C1 [3], the switch of grade 2 is based on control bit C2 [0], C2 [1], C2 [2] and C2 [3] value configure, the switchgear distribution of grade 3 is based on control bit C3 [0], C3 [1], C3 [2] It is configured with the value of C3 [3].

It is 1 that control bit, which is set as value, and corresponding switchgear distribution is interconnection by this so that (i) will be above defeated The value for entering reception is supplied to following output and (ii) will be supplied to output above in the value of following input reception.It will control It is 0 that position processed, which is set as value, and corresponding switchgear distribution is straight-through connection by this so that (i) puies forward the value received in input above It supplies the value that output and (ii) above will be received in following input and be supplied to following output.

In signal processing applications, the multistage interconnection of such as Omega network 3000 is frequently used for routing purpose, will Processor on one end of network is connected to the memory component on the other end.However, multistage interconnection can also be in signal In processing application for other purposes, such as continuous data flow of replacing or interweave.

Figure 30 shows the realization method for the suitable Omega MIN for being configured to interweave.In other embodiments In, other realization methods of suitable Omega MIN can also be used.

Although above description contains many specific embodiments of the present invention, these are not necessarily to be construed as the model for the present invention The limitation enclosed, but the example of its specific embodiment.Correspondingly, the scope of the present invention should not be only true by shown embodiment It is fixed, and should be determined by the attached claims and their equivalent.

Above-described various features and process can be used independently of each other, or can combine in various ways.Institute Possible combination and sub-portfolio are intended to and fall within the scope of the disclosure.If in addition, may be omitted in some implementation methods Drying method, event, state or procedure block.Method and process described herein are also not necessarily limited to any specific sequence, and with Its relevant piece or state can be executed with other suitable sequences.For example, the task or time can be in addition to tools The disclosed sequence of body executes, or can be by multiple combinations in single block or state.Example tasks or event can it is serial, It executes parallel or in other suitable manners.Task or event can be added into disclosed exemplary embodiment, or From wherein removal task or event.Exemplary system and component described herein is configurable to be different from described.Example Such as, compared with disclosed exemplary embodiment, element can be added, element is removed or rearranges element.

Claims

1. a kind of Nonvolatile memory system being configured for wear leveling, the system comprises：

State of a control determiner is accumulated, is configured to determine between instruction physical block address (PBA) and logical block address (LBA) The accumulation state of a control of the state of Random Maps；

Network is accessed, the access network configuration is that LBA is converted to PBA based on the accumulation state of a control；And

Backstage exchanges scheduler, is configured to state of a control to exchange the PBA for distributing to preselected LBA.

2. the system as claimed in claim 1,

The wherein described accumulation state of a control includes the first accumulation state of a control and the second accumulation state of a control；

The wherein described state of a control includes the first state of a control and the second state of a control；And

The wherein described second accumulation state of a control is the function of the first accumulation state of a control and second state of a control.

3. system as claimed in claim 2, wherein the second accumulation state of a control includes for realizing first accumulation The switch of the sequence of the displacement of state of a control is set, wherein generating the displacement using second state of a control.

4. the system as claimed in claim 1 further includes：

Mapping status generator, the mapping status generator are configured to platform in the rear and exchange scheduler exchange pre-selected number PBA after, from first memory mapping change into second memory mapping；

The wherein described first memory mapping and each in second memory mapping include the PBA of pre-selected number.

5. the system as claimed in claim 1, wherein the backstage exchanges scheduler configuration to the nonvolatile memory PBA is exchanged after the access of the pre-selected number of the nonvolatile memory of system.

6. system as claimed in claim 5, wherein the access of pre-selected number includes that 100 times of nonvolatile memory are write Enter.

7. the system as claimed in claim 1, wherein the access network is additionally configured to：

Using first function the first PBA candidates are generated from LBA；

Using second function the 2nd PBA candidates are generated from the LBA；And

Based on exchanging and be stored at the 2nd PBA candidates with the backstage for the data being stored at the first PBA candidates The information of the backstage exchange correlation of data, selects the first PBA candidate or the 2nd PBA candidates are used for data access.

8. system as claimed in claim 7, wherein：At least one of the first function or the second function include by The function that at least one of multistage interconnection or block cipher execute.

9. a kind of method for the loss equalization in Nonvolatile memory system, the method includes：

Determine that the accumulation of the state of the Random Maps between instruction physical block address (PBA) and logical block address (LBA) controls shape State；

LBA is converted into PBA based on the accumulation state of a control；And

The PBA for distributing to preselected LBA is exchanged based on state of a control.

10. method as claimed in claim 9,

11. method as claimed in claim 10, wherein the second accumulation state of a control includes tired for realizing described first The switch setting of the sequence of the displacement of product state of a control, wherein generating the displacement using second state of a control.

12. method as claimed in claim 9, further includes：

After the PBA for exchanging pre-selected number, second memory mapping is changed into from first memory mapping；

13. method as claimed in claim 9, wherein exchanging the PBA for distributing to preselected LBA based on the state of a control The access for being included in the pre-selected number of the nonvolatile memory to the Nonvolatile memory system exchanges PBA later.

14. method as claimed in claim 13, wherein the access of pre-selected number includes 100 times of nonvolatile memory Write-in.

15. method as claimed in claim 9, further includes：

Using first function the first PBA candidates are generated from LBA；

Using second function the 2nd PBA candidates are generated from the LBA；And

16. method as claimed in claim 15, wherein at least one of the first function or the second function include The function executed by least one of multistage interconnection or block cipher.

17. a kind of Nonvolatile memory system being configured to wear leveling, the system comprises：

Determine that the accumulation of the state of the Random Maps between instruction physical block address (PBA) and logical block address (LBA) controls shape The device of state；

LBA is converted to the device of PBA based on the accumulation state of a control；And

The device for the PBA for distributing to preselected LBA is exchanged based on state of a control.

18. system as claimed in claim 17,

19. system as claimed in claim 18, wherein the second accumulation state of a control includes tired for realizing described first The switch setting of the sequence of the displacement of product state of a control, wherein generating the displacement using second state of a control.

20. system as claimed in claim 17, further includes：

After the PBA for exchanging pre-selected number the device that second memory maps is changed into from first memory mapping；

21. system as claimed in claim 17, wherein distributing to preselected LBA's based on the state of a control to exchange The device of PBA is included in after the access of the pre-selected number of the nonvolatile memory to the Nonvolatile memory system Exchange the device of PBA.

22. system as claimed in claim 21, wherein the access of pre-selected number includes 100 times of nonvolatile memory Write-in.

23. system as claimed in claim 17, further includes：

The device of the first PBA candidates is generated from LBA using first function；

The device of the 2nd PBA candidates is generated from the LBA using second function；And

Based on exchanging and be stored at the 2nd PBA candidates with the backstage for the data being stored at the first PBA candidates The information of the backstage exchange correlation of data selects the first PBA candidate or the 2nd PBA candidates are for data access Device.

24. system as claimed in claim 23, wherein generating the device of the first PBA candidates from LBA using first function or making At least one of the device for generating the 2nd PBA candidates from LBA with second function includes in multistage interconnection or block cipher It is at least one.