CN108509255B

CN108509255B - Method and device for processing hardware interrupt

Info

Publication number: CN108509255B
Application number: CN201710103980.1A
Authority: CN
Inventors: 高巨鑫; 李雪峰; 高翔
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2017-02-24
Filing date: 2017-02-24
Publication date: 2021-01-22
Anticipated expiration: 2037-02-24
Also published as: CN108509255A

Abstract

The embodiment of the invention provides a method and a device for processing hardware interrupt, which are applied to an MIPS framework, wherein the method comprises the following steps: receiving a hardware interrupt trigger signal of a preset hardware interrupt interface; judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is the interrupt triggered by the timer; if so, mapping the data sampled in the PMU from the LINUX kernel space to the user space. According to the embodiment of the invention, when the PMC overflows and can not trigger interruption, the Perf of the user space can be ensured to continuously monitor the specified hardware performance event, and the system reliability and the user experience are effectively improved.

Description

Method and device for processing hardware interrupt

Technical Field

The present invention relates to the technical field of LINUX systems, and in particular, to a method and an apparatus for processing hardware interrupts.

Background

Perf (Performance Event) is a Performance profiling tool built into the LINUX kernel source code tree. Perf is based on the event sampling principle, and can realize the performance analysis of the relevant performance indexes of the processor and the relevant performance indexes of the operating system on the basis of performance events. In practical applications, the Perf can be used for performance bottleneck search and hot spot code location of a processor and an operating system.

In the prior art, the principle of Perf monitoring hardware performance events is as follows: the method comprises the steps that Perf calls a sys _ Perf _ event _ open function through a LINUX system, a Performance Counter for Monitoring a specified hardware Performance event is registered in a LINUX kernel, and the LINUX kernel initializes a PMC (Performance Monitoring Counter) on a PMU (Performance Monitoring Unit) according to parameter information of the specified hardware Performance event provided by Perf. PMC is automatically accumulated as specified hardware performance events occur. When PMC overflows, the PMC is reset, and the PMU triggers a PMI (Performance monitoring interrupt) interrupt. The LINUX kernel processes the sampled data of the PMU through a processing function corresponding to PMI interruption, and puts the processed sampled data into Ring Buffer (cache), wherein the Ring Buffer is used for communicating with a user space. And reading the sampling data from the Ring Buffer by a Perf analysis program in the user space by adopting a mmap (mapping a file or other objects into a memory) mechanism, analyzing the sampling data, and displaying the analyzed result on an application layer Perf interface.

The above-mentioned principle of Perf monitoring hardware performance events has the following disadvantages: when PMC overflow in the LINUX system can not trigger interruption, no monitoring information is displayed on a Perf interface of an application layer, so that the Perf of a user space can not monitor a specified hardware performance event.

Disclosure of Invention

In view of the foregoing problems, an embodiment of the present invention provides a method and a device for processing a hardware interrupt, so as to solve the problem that a user cannot monitor a specified hardware performance event when a PMC overflow in a LINUX system cannot trigger an interrupt in the prior art.

In order to solve the above problem, an embodiment of the present invention discloses a method for processing a hardware interrupt, which is applied to an MIPS architecture (Microprocessor with interleaved pipeline stages architecture, a processor architecture adopting a reduced instruction set), and includes the following steps: receiving a hardware interrupt trigger signal of a preset hardware interrupt interface; judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is the interrupt triggered by the timer; if so, mapping the data sampled in the PMU from the LINUX kernel space to the user space.

In order to solve the above problem, an embodiment of the present invention further discloses a device for processing hardware interrupts, which is applied to an MIPS architecture, and includes: the signal receiving module is used for receiving a hardware interrupt trigger signal of a preset hardware interrupt interface; the judging module is used for judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is the interrupt triggered by the timer; and the interrupt module is used for mapping the data sampled in the PMU from the LINUX kernel space to the user space when the hardware interrupt corresponding to the hardware interrupt trigger signal is judged to be the interrupt triggered by the timer.

The embodiment of the invention has the following advantages: under the condition that PMC overflow cannot trigger interrupt, if a hardware interrupt trigger signal of a preset hardware interrupt interface is received, judging whether a hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by a timer, and if so, mapping data sampled in a PMU from a LINUX kernel space to a user space. Therefore, when the PMC overflows and cannot trigger interruption, timer interruption is achieved to replace PMC overflow to trigger interruption, the fact that the Perf of the user space can still obtain sampling data of the hardware performance event to be monitored is guaranteed, then the application layer Perf interface can display the sampling data, namely the fact that the Perf of the user space can continue to monitor the specified hardware performance event is achieved, and system reliability and user experience are effectively improved.

Drawings

FIG. 1 is a flow chart of the steps of a method embodiment of the present invention for handling a hardware interrupt;

FIG. 2 is a flow chart of steps in another embodiment of a method for handling a hardware interrupt of the present invention;

FIG. 3 is a block diagram of an embodiment of a hardware interrupt processing apparatus according to the present invention;

FIG. 4 is a block diagram of another embodiment of a hardware interrupt handling apparatus according to the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

The hardware interrupt processing method and the hardware interrupt processing device of the embodiment of the invention can be applied to an MIPS framework.

Example one

Referring to fig. 1, a flowchart illustrating steps of an embodiment of a method for processing a hardware interrupt according to the present invention is shown, which may specifically include the following steps:

step 10, receiving a hardware interrupt trigger signal of a preset hardware interrupt interface.

Specifically, when the Perf monitors a hardware performance event to be monitored, the Perf calls a sys _ Perf _ event _ open function through a LINUX system, and then a performance counter for monitoring the hardware performance event to be monitored is registered in a LINUX kernel, and the LINUX kernel initializes a PMC on the PMU according to parameter information of the hardware performance event to be monitored, which is provided by the Perf. The PMC is automatically accumulated as hardware performance events to be monitored occur. If step 10 receives a hardware interrupt trigger signal for presetting a hardware interrupt interface under the condition that the PMC overflows and cannot trigger the interrupt, step 20 may be entered.

Specifically, the LINUX system includes a LINUX kernel and a processor (including PMU and timer), and the processor may receive a hardware interrupt trigger signal through HW 0-HW 5 hardware interrupt interfaces. The PMC overflow cannot trigger the interrupt, and the PMU may not output a hardware interrupt trigger signal when the PMC overflows. In addition, each time a hardware performance event to be monitored occurs, the PMU samples relevant data (for example, data such as a current function name, a current time, a current PMC count value, and the like) at the time of the hardware performance event to be monitored.

Preferably, the PMU outputs a hardware interrupt trigger signal through HW5 hardware interrupt interface when PMC overflows in case that the PMC overflows to trigger an interrupt. Therefore, when the PMC overflow cannot trigger the interrupt, the preset hardware interrupt interface in step 10 may be set to be the HW5 hardware interrupt interface, so that the interface where the timer triggers the interrupt and the interface where the PMC overflow triggers the interrupt multiplex the HW5 hardware interrupt interface, thereby avoiding the timer interrupt occupying other hardware interrupt interfaces and saving hardware resources. In this case, step 10 only needs to monitor whether the HW5 hardware interrupt interface receives the hardware interrupt trigger signal.

Specifically, after step 10, the processor saves the field information. The saving field information may be processor instruction address, current timestamp, and PID (Process Identifier), TID (Tag Identifier), and comm (command) information of the current Process when the saving timer triggers the interrupt.

And 20, judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is the interrupt triggered by the timer.

Specifically, in step 20, it may be determined, by the LINUX kernel analysis program, whether the hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer. When the timer triggers the interrupt, the timer sends a hardware interrupt trigger signal to a preset hardware interrupt interface.

And step 30, if so, mapping the data sampled in the PMU from the LINUX kernel space to the user space.

Specifically, the process of mapping the data sampled in the PMU from the LINUX kernel space to the user space in step 30 may be: the data sampled by the PMU can be taken out by calling the PMI to interrupt the corresponding processing function, the data sampled by the PMU is processed (for example, statistical analysis processing) according to the type of the hardware performance event to be monitored, and the processed data is put into the Ring Buffer. And reading data from the Ring Buffer by a Perf analysis program in the user space by adopting a mmap mechanism, analyzing the read data, and displaying an analyzed result on an application layer Perf interface. Wherein, when performing statistical analysis processing on the data sampled by the PMU according to the type of the hardware performance event to be monitored, the statistical analysis processing may be: and respectively counting the total times of occurrence of each function causing the performance event of the hardware to be monitored, and further processing the counted data, for example, respectively calculating the proportion of each total time in the current PMC count value.

Further, step 30 may also place the saved field information into Ring Buffer for display on the application layer Perf interface.

The embodiment of the invention has the following advantages: under the condition that PMC overflow cannot trigger interrupt, if a hardware interrupt trigger signal of a preset hardware interrupt interface is received, judging whether a hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by a timer, and if so, mapping data sampled in the PMU from a LINUX kernel space to a user space according to the type of a hardware performance event to be monitored. Therefore, when the PMC overflows and cannot trigger interruption, timer interruption is achieved to replace PMC overflow to trigger interruption, the fact that the Perf of the user space can still obtain sampling data of the hardware performance event to be monitored is guaranteed, then the application layer Perf interface can display the sampling data, namely the fact that the Perf of the user space can continue to monitor the hardware performance event to be monitored is achieved, and system reliability and user experience are effectively improved.

Example two

Referring to fig. 2, it shows a flowchart of steps of another embodiment of a hardware interrupt processing method according to the present invention, which may specifically include the following steps:

step 101, receiving a hardware interrupt trigger signal of a preset hardware interrupt interface.

Specifically, after step 101, the processor stores the field information and changes the value of the cause register, where the value of the cause register is the value of the hardware interrupt corresponding to the hardware interrupt trigger signal. The saving field information can be processor instruction address, current timestamp, and PID, TID, and comm of the current process when the saving timer triggers the interrupt.

And 102, judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is the interrupt triggered by the timer.

Referring to fig. 2, the step 102 of determining whether the hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer may include the following steps:

step 1021, reading the value of the cause register.

Specifically, bits 8 to 15 (i.e., IP7-0) of a CAUSE register in the LINUX kernel are used to store values corresponding to each hardware interrupt, including values of timer interrupts, where values of different CAUSE registers correspond to values of different hardware interrupts. For example, assuming that the value corresponding to the timer interrupt in the CAUSE register is 0, i.e., 00000000, before the timer triggers the interrupt, the processor may change the value corresponding to the timer interrupt in the CAUSE register to 1, i.e., 00000001, when the timer triggers the interrupt.

When the step 101 receives a hardware interrupt trigger signal of a preset hardware interrupt interface, the step 1021 may read the value of the cause register through the LINUX kernel parser.

Wherein, after reading the value of the cause register at step 1021, the processor may reset the value of the cause register. For example, when the timer triggers the interrupt, after the processor changes the value corresponding to the timer interrupt in the CAUSE register to be 1, if the value corresponding to the timer interrupt in the CAUSE register in the LINUX kernel is read in step 1021, the processor may reset the value corresponding to the timer interrupt in the CAUSE register to be 0 to prepare for the next interrupt.

And step 1022, judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer according to the value of the cause register.

For example, if the value corresponding to the timer interrupt in the CAUSE register is 1, step 1022 determines that the hardware interrupt corresponding to the hardware interrupt trigger signal is a timer-triggered interrupt.

And 103, if so, mapping the data sampled in the PMU from the LINUX kernel space to the user space.

And step 104, resetting the timer when the hardware interrupt corresponding to the hardware interrupt trigger signal is judged to be the interrupt triggered by the timer.

It should be noted that, in practical applications, step 104 may ensure that the Perf of the user space may obtain the sampling data of the hardware performance event to be monitored at intervals. Assuming that the timing time of the timer is 1S, triggering an interrupt every 1S timer, so that data sampled in the PMU is mapped from the LINUX kernel space to the user space every 1S step 103, and the application layer Perf interface displays the sampled data.

Wherein, step 103 and step 104 can be performed simultaneously.

In addition, another embodiment of the hardware interrupt processing method according to the present invention may further include the following steps:

receiving a timing time setting instruction; the timing time setting instruction includes a first timing time determined according to a user sampling requirement.

Setting the timing time of the timer as a first timing time.

The timing setting instruction can be directly input into the LINUX kernel. In addition, receiving the timing time setting instruction may occur at an arbitrary time.

The above steps set the timing time of the timer according to the sampling requirement of the user, and the sampling frequency of the Perf can be changed, thereby realizing the change of the sampling accuracy of the Perf. Wherein the user sampling requirements may include sampling frequency requirements. Therefore, the sampling frequency of the Perf can be changed at any time, the sampling accuracy of the Perf is further changed, and the sampling requirement of a user is met.

Specifically, in one embodiment of the present invention, the principle of Perf monitoring hardware performance events is as follows:

under the condition that interruption cannot be triggered by PMC overflow, when Perf monitors a hardware performance event to be monitored, the Perf calls a sys _ Perf _ event _ open function through a LINUX system, a performance counter for monitoring the hardware performance event to be monitored is further registered in a LINUX kernel, and the LINUX kernel initializes a PMC on a PMU according to parameter information of the hardware performance event to be monitored, wherein the parameter information is provided by the Perf. The PMC is automatically accumulated as hardware performance events to be monitored occur. When PMC overflows, PMC overflows and cannot trigger an interrupt.

At this time, if the hardware interrupt trigger signal of the preset hardware interrupt interface is received in step 101, the processor stores the field information, and changes the value of the cause register accordingly, and then the process proceeds to step 102. Each time a hardware performance event to be monitored occurs, the PMU samples relevant data (for example, data such as a current function name, a current time, a current PMC count value, and the like) at the time of the hardware performance event to be monitored. Step 102 judges whether the hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer, and in the process, the processor can reset the value of the cause register. If so, step 103 maps the sampled data in the PMU from LINUX kernel space to user space, while step 104 resets the timer.

Step 103 may take out PMU sampled data by calling a processing function corresponding to PMI interrupt, process the PMU sampled data according to the type of the hardware performance event to be monitored (e.g., statistical analysis processing), and place the processed data in Ring Buffer. And reading data from the Ring Buffer by a Perf analysis program in the user space by adopting a mmap mechanism, analyzing the read data, and displaying an analyzed result on a Perf interface of an application layer, so that a user can intuitively monitor a specified hardware performance event.

In the process, the timing time of the timer can be set at any moment according to the sampling requirement of the user, so that the sampling accuracy can be changed at any time, and the sampling requirement of the user can be better met. Therefore, when the PMC overflows and cannot trigger interruption, timer interruption is achieved to replace PMC overflow to trigger interruption, the Perf of the user space can still obtain sampling data of the hardware performance event to be monitored at intervals, the application layer Perf interface can display the sampling data, the Perf of the user space can continue to monitor the hardware performance event to be monitored, and system reliability and user experience are effectively improved.

The embodiment of the invention has the following advantages: under the condition that PMC overflow cannot trigger interrupt, if a hardware interrupt trigger signal of a preset hardware interrupt interface is received, judging whether a hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by a timer, if so, mapping data sampled in the PMU from a LINUX kernel space to a user space according to the type of a hardware performance event to be monitored, and resetting the timer. Therefore, when the PMC overflows and cannot trigger interruption, interruption is triggered by timer interruption instead of PMC overflow, and therefore the Perf of the user space can still obtain sampling data of the hardware performance event to be monitored at intervals, the application layer Perf interface can display the sampling data, the Perf of the user space can continue to monitor the hardware performance event to be monitored, and system reliability and user experience are effectively improved.

It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

EXAMPLE III

Referring to fig. 3, a block diagram of a hardware interrupt processing apparatus according to an embodiment of the present invention is shown, which may specifically include the following modules:

the signal receiving module 10 is configured to receive a hardware interrupt trigger signal of a preset hardware interrupt interface.

Preferably, the PMU outputs a hardware interrupt trigger signal through HW5 hardware interrupt interface when PMC overflows in case that the PMC overflows to trigger an interrupt. Therefore, when the PMC overflow cannot trigger the interrupt, the preset hardware interrupt interface in step 10 may be set to be the HW5 hardware interrupt interface, so that the interface where the timer triggers the interrupt and the interface where the PMC overflow triggers the interrupt multiplex the HW5 hardware interrupt interface, thereby avoiding the timer interrupt occupying other hardware interrupt interfaces and saving hardware resources.

The judging module 20 is configured to judge whether a hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer.

The mapping module 30 is configured to map the data sampled in the PMU from the LINUX kernel space to the user space when the determining module 20 determines that the hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer.

The third embodiment of the invention has the following advantages: under the condition that PMC overflow cannot trigger interrupt, if a hardware interrupt trigger signal of a preset hardware interrupt interface is received, judging whether a hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by a timer, and if so, mapping data sampled in the PMU from a LINUX kernel space to a user space according to the type of a hardware performance event to be monitored. Therefore, when the PMC overflows and cannot trigger interruption, timer interruption is achieved to replace PMC overflow to trigger interruption, the fact that the Perf of the user space can still obtain sampling data of the hardware performance event to be monitored is guaranteed, then the application layer Perf interface can display the sampling data, namely the fact that the Perf of the user space can continue to monitor the hardware performance event to be monitored is achieved, and system reliability and user experience are effectively improved.

Example four

Referring to fig. 4, a block diagram of another embodiment of the hardware interrupt processing apparatus according to the present invention is shown, and specifically includes the following modules:

the signal receiving module 101 is configured to receive a hardware interrupt trigger signal of a preset hardware interrupt interface.

Specifically, after the signal receiving module 101, the processor stores the field information, and changes the value of the cause register, where the value of the cause register is the value of the hardware interrupt corresponding to the hardware interrupt trigger signal.

The determining module 102 is configured to determine whether a hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer.

Referring to fig. 4, the determining module 102 may include:

and a data reading unit 1021 for reading the value of the cause register.

When the signal receiving module 101 receives a hardware interrupt trigger signal of a preset hardware interrupt interface, the data reading unit 1021 may read a value of the cause register through the LINUX kernel analysis program.

Wherein the processor may reset the value of the cause register after the data reading unit 1021 reads the value of the cause register. For example, when the timer triggers an interrupt, after the processor changes the value corresponding to the timer interrupt in the CAUSE register to be 1, if the data reading unit 1021 reads the value corresponding to the timer interrupt in the CAUSE register in the LINUX kernel, the processor may reset the value corresponding to the timer interrupt in the CAUSE register to be 0 to prepare for the next interrupt.

The determining unit 1022 is configured to determine whether a hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer according to the value of the cause register.

For example, if the value corresponding to the timer interrupt in the CAUSE register is 1, the determining unit 1022 determines that the hardware interrupt corresponding to the hardware interrupt trigger signal is the timer-triggered interrupt.

The mapping module 103 is configured to map, when the determining module 102 determines that the hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer, data sampled in the PMU from the LINUX kernel space to the user space.

The resetting module 104 is configured to reset the timer when the determining module 102 determines that the hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by the timer.

It should be noted that, in practical applications, the reset module 104 may ensure that the Perf of the user space may obtain the sampling data of the hardware performance event to be monitored at intervals. Assuming that the timing time of the timer is 1S, triggering an interrupt every 1S timer, so that data sampled in the PMU is mapped from the LINUX kernel space to the user space every 1S step 103, and the application layer Perf interface displays the sampled data.

Wherein the mapping module 103 and the resetting module 104 may be performed simultaneously.

In addition, another embodiment of the apparatus for processing a hardware interrupt according to the present invention may further include:

the instruction receiving module is used for receiving a timing time setting instruction; the timing time setting instruction includes a first timing time determined according to a user sampling requirement.

And the time setting module is used for setting the timing time of the timer as the first timing time.

The timing time setting instruction can be directly input into the LINUX kernel, namely, the instruction receiving module is arranged in the LINUX kernel. In addition, receiving the timing time setting instruction may occur at an arbitrary time.

The fourth embodiment of the invention has the following advantages: under the condition that PMC overflow cannot trigger interrupt, if a hardware interrupt trigger signal of a preset hardware interrupt interface is received, judging whether a hardware interrupt corresponding to the hardware interrupt trigger signal is an interrupt triggered by a timer, if so, mapping data sampled in the PMU from a LINUX kernel space to a user space according to the type of a hardware performance event to be monitored, and resetting the timer. Therefore, when the PMC overflows and cannot trigger interruption, interruption is triggered by timer interruption instead of PMC overflow, and therefore the Perf of the user space can still obtain sampling data of the hardware performance event to be monitored at intervals, the application layer Perf interface can display the sampling data, the Perf of the user space can continue to monitor the hardware performance event to be monitored, and system reliability and user experience are effectively improved.

For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The hardware interrupt processing method and the hardware interrupt processing apparatus provided by the present invention are described in detail above, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A processing method of hardware interrupt is applied to MIPS architecture, and is characterized by comprising the following steps:

under the condition that a hardware performance counter PMC overflows and cannot trigger interrupt, a processor receives a hardware interrupt trigger signal of a preset hardware interrupt interface;

judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is the interrupt triggered by the timer or not through a LINUX kernel analysis program;

if yes, mapping the data sampled in the PMU from the LINUX kernel space to the user space.

2. The method according to claim 1, wherein the determining whether the hardware interrupt corresponding to the hardware interrupt trigger signal is a timer-triggered interrupt comprises:

reading the value of a cause register;

and judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is the interrupt triggered by the timer or not according to the value of the cause register.

3. The method of claim 1, wherein the predetermined hardware interrupt interface is a HW5 hardware interrupt interface.

4. The method of claim 1, further comprising the steps of:

receiving a timing time setting instruction; the timing time setting instruction comprises a first timing time determined according to the sampling requirement of a user;

and setting the timing time of the timer as the first timing time.

5. The method of claim 1, further comprising the steps of:

and resetting the timer when the hardware interrupt corresponding to the hardware interrupt trigger signal is judged to be the interrupt triggered by the timer.

6. A hardware interrupt processing device applied to MIPS architecture is characterized by comprising:

the signal receiving module is used for receiving a hardware interrupt trigger signal of a preset hardware interrupt interface by the processor under the condition that the PMC overflows and cannot trigger interrupt;

the judging module is used for judging whether the hardware interrupt corresponding to the hardware interrupt triggering signal is the interrupt triggered by the timer or not through the LINUX kernel analysis program;

and the mapping module is used for mapping the data sampled in the PMU from the LINUX kernel space to the user space when the judging module judges that the hardware interrupt corresponding to the hardware interrupt triggering signal is the interrupt triggered by the timer.

7. The apparatus of claim 6, wherein the determining module comprises:

the data reading unit is used for reading the value of the cause register;

and the judging unit is used for judging whether the hardware interrupt corresponding to the hardware interrupt trigger signal is the interrupt triggered by the timer according to the value of the cause register.

8. The apparatus of claim 6, wherein the predetermined hardware interrupt interface is a HW5 hardware interrupt interface.

9. The apparatus of claim 6, further comprising:

the instruction receiving module is used for receiving a timing time setting instruction; the timing time setting instruction comprises a first timing time determined according to the sampling requirement of a user;

10. The apparatus of claim 6, further comprising:

and the resetting module is used for resetting the timer when the judging module judges that the hardware interrupt corresponding to the hardware interrupt triggering signal is the interrupt triggered by the timer.