CN108508950B - Circuit for improving output direct current level of transimpedance amplifier stage in TIA - Google Patents
Circuit for improving output direct current level of transimpedance amplifier stage in TIA Download PDFInfo
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- CN108508950B CN108508950B CN201810208897.5A CN201810208897A CN108508950B CN 108508950 B CN108508950 B CN 108508950B CN 201810208897 A CN201810208897 A CN 201810208897A CN 108508950 B CN108508950 B CN 108508950B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
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Abstract
The invention relates to a circuit for improving the output direct current level of a transimpedance amplifier stage in TIA, which comprises the transimpedance amplifier stage, a differential amplifier stage, a level lifting unit and a direct current recovery loop; the input end of the transimpedance amplifier stage is used for inputting a photocurrent signal, and the output end of the transimpedance amplifier stage is directly connected with the input end of the differential amplifier stage. According to the invention, the level lifting unit and the direct current recovery loop are introduced to realize the lifting of the output direct current level of the transimpedance amplifier stage, so that the aim of matching with the input direct current level of the differential amplifier stage is fulfilled, and the stability of the whole circuit is improved.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a circuit for improving the output direct current level of a transimpedance amplifier stage in a TIA.
Background
In optical communication, a transimpedance amplifier circuit (TIA) at a receiving front end mainly comprises a transimpedance amplifier stage and a differential amplifier stage. The transimpedance amplification stage converts the photocurrent signal into a voltage signal, and the differential amplification stage further amplifies the output voltage signal of the front stage so as to meet the requirement of the output voltage amplitude. The transimpedance amplifier stage is usually formed by a single-ended circuit, the output direct current level of the transimpedance amplifier stage cannot be matched with the input direct current level of the differential amplifier stage, and other circuit structures are needed to be added to realize level matching.
As shown in FIG. 1, a transimpedance amplifier stage composed of an NMOS transistor MN1, a PMOS transistor MP1 and an adjustable resistor RF has an output DC level of V1, and is shown in I in When=0, v1=vgs MN1 . Fig. 2 shows an input stage of a differential amplifier stage, which requires an input dc level of v2=vgs due to an increase in tail current Itail1 MN5 +Vtail. Due to VGS MN1 ≈VGS MN5 V1 and V2 differ by a voltage of Vtail, and are not well connected directly. The current method is to use CS amplifying stage composed of NMOS tube MN3 and resistor R3 to raise V1 level and then to match with differential amplifying stageAnd (3) connecting.
The bias current of the CS amplifier stage formed by the NMOS transistor MN3 and the resistor R3 is determined by the transimpedance amplifier stage. If the production process deviates or I in Not equal to 0, V1 will change, and the bias current of the CS stage will also change, so that the bandwidth and gain of the entire TIA will also change, affecting the stability of the overall circuit operation.
Disclosure of Invention
The invention aims to provide a circuit for improving the output direct current level of a transimpedance amplifier stage in a TIA, which can realize direct current level matching between the transimpedance amplifier stage and a differential amplifier stage without introducing an additional intermediate stage and improve the stability of the whole circuit.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a circuit for improving the output direct current level of a transimpedance amplifier stage in a TIA comprises the transimpedance amplifier stage, a differential amplifier stage, a level lifting unit and a direct current recovery loop; the input end of the transimpedance amplifying stage is used for inputting a photocurrent signal, and the output end of the transimpedance amplifying stage is directly connected with the input end of the differential amplifying stage;
the DC recovery loop comprises a pseudo-transimpedance amplifier stage, a first filter unit, a second filter unit, a DC recovery operational amplifier and a DC passage unit, wherein the transimpedance amplifier stage and the pseudo-transimpedance amplifier stage are connected in parallel between a power supply VDD and a level lifting unit, the output end of the transimpedance amplifier stage is connected with the inverting input end of the DC recovery operational amplifier through the first filter circuit, the output end of the pseudo-transimpedance amplifier stage is connected with the non-inverting input end of the DC recovery operational amplifier through the second filter unit, the output end of the DC recovery operational amplifier is connected with the DC passage unit, and the DC passage unit is also connected with the input end of the transimpedance amplifier stage.
The level lifting unit comprises a tail current source Itail and a capacitor C3, wherein the tail current source Itail and the capacitor C3 are connected in parallel, one end of the tail current source Itail is connected with a transimpedance amplifier stage and a pseudo transimpedance amplifier stage, and the other end of the tail current source Itail is grounded.
The pseudo-transimpedance amplifier stage comprises a PMOS tube MP2, an NMOS tube MN2 and a resistor Rdummy, wherein the source electrode of the PMOS tube MP2 is connected with a power supply VDD, the grid electrode is connected with one end of the resistor Rdummy, and the drain electrode is connected with the other end of the resistor Rdummy; the grid electrode of the NMOS tube MN2 is connected with one end of the grid electrode of the PMOS tube MP2 through a resistor Rdummy, the drain electrode of the NMOS tube MN2 is connected with one end of the drain electrode of the PMOS tube MP2 through the resistor Rdummy, the source electrode of the NMOS tube MN2 is connected with the level lifting unit, the drain electrode of the PMOS tube MP2 is connected through the resistor Rdummy, and one end of the drain electrode of the NMOS tube MN2 is used as an output end of the pseudo-transimpedance amplifier stage to be connected to the second filter unit.
The DC path unit comprises an NMOS tube MN0, wherein the grid electrode of the NMOS tube MN0 is connected with the output end of the DC recovery operational amplifier, the drain electrode of the NMOS tube MN0 is connected with the input end of the transimpedance amplifier stage, and the source electrode of the NMOS tube MN0 is grounded.
The direct current recovery operational amplifier comprises a PMOS tube MP7, an NMOS tube MN7, a PMOS tube MP8, an NMOS tube MN8, a PMOS tube MP9, a resistor Rc, a capacitor Cc, a tail current source Itail2 and a tail current source Itail3, wherein the grid electrode of the NMOS tube MN7 is connected with the inverting input end of the direct current recovery operational amplifier, the source electrode is grounded through the tail current source Itail2, the drain electrode is connected with the drain electrode of the PMOS tube MP7 on one hand, the drain electrode of the NMOS tube MN7 is also connected with the grid electrode of the PMOS tube MP7, and the source electrode of the PMOS tube MP7 is connected with a power supply VDD;
the grid electrode of the NMOS tube MN8 is connected with the non-inverting input end INP of the direct current recovery operational amplifier, the source electrode is grounded through the tail current source Itail2, the drain electrode is connected with the drain electrode of the PMOS tube MP8 on one hand, and the drain electrode is connected with the output end of the direct current recovery operational amplifier through the resistor Rc and the capacitor Cc on the other hand in sequence; the grid electrode of the PMOS tube MP8 is connected with the grid electrode of the PMOS tube MP7, and the source electrode of the PMOS tube MP8 is connected with the power supply VDD;
the grid electrode of the PMOS tube MP9 is connected with the drain electrode of the PMOS tube MP8, the source electrode of the PMOS tube MP9 is connected with the power supply VDD, the drain electrode of the PMOS tube MP9 is grounded through the tail current source Itail3 on one hand, and on the other hand, the drain electrode of the PMOS tube MP9 is connected with the output end of the direct current recovery operational amplifier.
The transimpedance amplifier stage comprises a PMOS tube MP1, an NMOS tube MN1 and a variable resistor RF, wherein the grid electrode of the PMOS tube MP1 is connected with the input end IN of the transimpedance amplifier stage, the source electrode is connected with a power supply VDD, and the drain electrode is connected with the output end of the transimpedance amplifier stage; the grid electrode of the NMOS tube MN1 is connected with the input end of the transimpedance amplifier stage, the source electrode is connected with the level lifting unit, and the drain electrode is connected with the output end of the transimpedance amplifier stage; one end of the variable resistor RF is connected with the input end of the transimpedance amplifier stage, and the other end of the variable resistor RF is connected with the output end of the transimpedance amplifier stage.
The first filter circuit comprises a resistor R1 and a capacitor C1, one end of the resistor R1 is connected with the output end of the transimpedance amplifier stage, the other end of the resistor R1 is grounded through the capacitor C1, and meanwhile, one end of the resistor R1 connected with the capacitor C1 is also connected with the inverting input end of the direct current recovery operational amplifier; the second filtering unit comprises a resistor R2 and a capacitor C2, one end of the resistor R2 is connected with the output end of the pseudo-transimpedance amplifier stage, the other end of the resistor R2 is grounded through the capacitor C2, and meanwhile, one end of the resistor R2 connected with the capacitor C2 is also connected with the non-inverting input end of the direct current recovery operational amplifier.
After the scheme is adopted, the tail current source Itail is introduced into the transimpedance amplifier stage to improve the output direct current level of the transimpedance amplifier stage, so that the output direct current level of the transimpedance amplifier stage is matched with the input direct current level of the differential amplifier stage. In order to avoid the problem of mismatch between the output DC level of the transimpedance amplifier stage and the input DC level of the differential amplifier stage caused by the change of the input current of the transimpedance amplifier stage, the invention adds the DC recovery loop, and if the input current of the transimpedance amplifier stage is increased to change, the DC part of the input current of the transimpedance amplifier stage is led into the ground potential under the clamping action of the DC recovery loop, so that the output DC level of the transimpedance amplifier stage is recovered, the output DC level of the transimpedance amplifier stage and the input DC level of the differential amplifier stage are matched again, and the stability of the whole circuit is improved.
Drawings
FIG. 1 is a prior art transimpedance amplifier stage circuit diagram;
FIG. 2 is a circuit diagram of a differential amplifier stage of the prior art;
FIG. 3 is a circuit diagram of a transimpedance amplifier stage according to the present invention;
fig. 4 is a circuit diagram of a DC-RESTORE op-amp of the present invention.
Detailed Description
The invention discloses a circuit for improving the output direct current level of a transimpedance amplifier stage in TIA, which realizes the improvement of the output direct current level of the transimpedance amplifier stage by introducing a level improving unit 2 and a direct current recovery loop 3, thereby achieving the aim of matching with the input direct current level of a differential amplifier stage.
Specifically, the circuit for improving the output direct current level of the transimpedance amplifier stage IN the TIA comprises a transimpedance amplifier stage 1, a differential amplifier stage, a level lifting unit 2 and a direct current recovery loop 3 (DC-RESTORE loop), wherein the input end IN of the transimpedance amplifier stage 1 is connected with a photodiode L1 for inputting a photocurrent signal, and the output end out1 of the transimpedance amplifier stage 1 is directly connected with the input end of the differential amplifier stage. The specific circuit connection relationships of the transimpedance amplifier stage 1, the level-raising unit 2 and the dc-restoration loop 3 will be described in detail below, but for the differential amplifier stage, since it is a prior art, the description thereof will be omitted.
As shown IN fig. 3, the transimpedance amplifier stage 1 includes a PMOS transistor MP1, an NMOS transistor MN1, and a variable resistor RF, where a gate of the PMOS transistor MP1 is connected to an input terminal IN of the transimpedance amplifier stage 1, a source is connected to a power supply VDD, and a drain is connected to an output terminal out1 of the transimpedance amplifier stage 1; the gate of the NMOS tube MN1 is connected with the input end IN of the transimpedance amplifier stage 1, the source is grounded through the level lifting unit 2, and the drain is connected with the output end out1 of the transimpedance amplifier stage 1; one end of the variable resistor RF is connected to the input terminal IN of the transimpedance amplifier stage 1, and the other end is connected to the output terminal out1 of the transimpedance amplifier stage 1.
The direct current recovery loop 3 specifically includes a pseudo-transimpedance amplifier stage 31, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a direct current recovery operational amplifier 32 (DC-RESTORE operational amplifier), and an NMOS tube MN0, wherein the pseudo-transimpedance amplifier stage 31 includes a PMOS tube MP2, an NMOS tube MN2, and a resistor Rdummy, a source electrode of the PMOS tube MP2 is connected to a power supply VDD, a gate electrode is connected to one end of the resistor Rdummy, and a drain electrode is connected to the other end of the resistor Rdummy; the grid electrode of the NMOS tube MN2 is connected with one end of the resistor Rdummy connected with the grid electrode of the PMOS tube MP2, the drain electrode of the NMOS tube MN2 is connected with one end of the resistor Rdummy connected with the drain electrode of the PMOS tube MP2, and the source electrode of the NMOS tube MN2 is grounded through the level lifting unit 2.
One end of the resistor Rdummy connected with the PMOS tube MP2 and one end of the NMOS tube MN2 are connected with the non-inverting input end INP of the dc-recovery operational amplifier 32 via the resistor R2, and at the same time, the non-inverting input end INP of the dc-recovery operational amplifier 32 is grounded via the capacitor C2, and the resistor R2 and the capacitor C2 form the second filter unit 35. The inverting input terminal INN of the dc restoring op-amp 32 is connected to the output terminal out1 of the transimpedance amplifier stage via a resistor R1, and the inverting input terminal INN of the dc restoring op-amp 32 is grounded via a capacitor C1, where the resistor R1 and the capacitor C1 form the first filter unit 34. The output end of the dc restoring op-amp 32 is connected to the gate of the NMOS MN0, the source of the NMOS MN0 is grounded, the drain is connected to the input end IN of the transimpedance amplifier stage, and the NMOS MN0 forms the dc path unit 33.
The level-raising unit 2 includes a tail current source Itail and a capacitor C3, where the tail current source Itail and the capacitor C3 are connected in parallel, one end of the tail current source Itail is connected to the ground, the other end is connected to the source of the NMOS transistor MN1 of the transimpedance amplifier stage 1, and at the same time, the end is also connected to the source of the NMOS transistor MN2 of the pseudo transimpedance amplifier stage 31. After the tail current Itail is added, the loop gain of the transimpedance amplifier stage 1 can be reduced, and the capacitor C3 can play a role of high-frequency alternating current short circuit, so that the loop gain of the transimpedance amplifier stage 1 is improved.
As shown in fig. 4, the dc restoring op-amp 32 includes a PMOS transistor MP7, an NMOS transistor MN7, a PMOS transistor MP8, an NMOS transistor MN8, a PMOS transistor MP9, a resistor Rc, a capacitor Cc, a tail current source Itail2, and a tail current source Itail3, wherein a gate of the NMOS transistor MN7 is connected to an inverting input terminal of the dc restoring op-amp 32, a source is grounded via the tail current source Itail2, a drain is connected to a drain of the PMOS transistor MP7, and a drain of the NMOS transistor MN7 is also connected to a gate of the PMOS transistor MP7, and a source of the PMOS transistor MP7 is connected to the power supply VDD.
The grid electrode of the NMOS tube MN8 is connected with the non-inverting input end INP of the DC recovery operational amplifier 32, the source electrode is grounded through a tail current source Itail2, the drain electrode is connected with the drain electrode of the PMOS tube MP8 on one hand, and the drain electrode is connected with the output end out2 of the DC recovery operational amplifier 32 through a resistor Rc and a capacitor Cc in sequence on the other hand; the grid electrode of the PMOS tube MP8 is connected with the grid electrode of the PMOS tube MP7, and the source electrode of the PMOS tube MP8 is connected with the power supply VDD.
The grid electrode of the PMOS tube MP9 is connected with the drain electrode of the PMOS tube MP8, the source electrode of the PMOS tube MP9 is connected with the power supply VDD, the drain electrode of the PMOS tube MP9 is grounded through the tail current source Itail3 on one hand, and on the other hand, the drain electrode of the PMOS tube MP9 is connected with the output end out2 of the direct current recovery operational amplifier 32.
The invention is used in the transimpedance amplification because the tail current introduced by the differential amplification stage causes mismatch between the tail current and the DC level of the transimpedance amplification stage 1The tail current source Itail is also introduced in stage 1 to increase its output dc level. The output DC level of the transimpedance amplifier stage 1 is determined by the PMOS tube MP1, the NMOS tube MN1 and the power supply VDD, and after the tail current source Itail is introduced, the output DC level of the transimpedance amplifier stage is determined by the tail current source Itail, the PMOS tube MP1 and the power supply VDD. When the input current Iin of the transimpedance amplifier stage 1 is 0 or less, the output dc level Vout1 of the transimpedance amplifier stage 1 is increased by Vtail based on the original value due to the introduction of the tail current Itail, i.e., vout1 = VGS MN1 +V tail Matching the V2 dc level.
However, if the tail current source Itail is introduced singly, when the input current Iin of the transimpedance amplifier stage 1 increases, the output dc level thereof decreases due to the increase of the input current Iin, eventually resulting in a dc level mismatch. Thus introducing a direct current recovery loop 3 at the same time as introducing the tail current source Itail. The PMOS transistor MP2, the NMOS transistor MN2, and the resistor Rdummy in the dc recovery loop 3 form a pseudo-transimpedance amplifier stage 31, and the output dc level Vdummy thereof provides a reference level. The input current Iin of the transimpedance amplifier stage 1 is zero or close to zero, the output dc level Vout of the transimpedance amplifier stage 1 and the output dc level Vdummy of the pseudo transimpedance amplifier stage 31 are equal, and the MN0 pipe is closed (i.e., disconnected). When the input current Iin of the input end IN of the transimpedance amplifier stage 1 increases, the output direct current level of the transimpedance amplifier stage 1 decreases, the IN-phase input end voltage of the direct current recovery operational amplifier 32 is larger than the reverse-phase input end voltage, the output end voltage of the direct current recovery operational amplifier 32 increases, the NMOS tube MN0 is started, the direct current part of the input current Iin of the input end IN of the transimpedance amplifier stage 1 is led into the ground potential, and therefore the output direct current level of the transimpedance amplifier stage 1 is recovered, and matching is achieved again between the output direct current level Vout1 of the transimpedance amplifier stage 1 and the input direct current level V2 of the differential amplifier stage. If the current changes again at this time, the output voltage of the dc-dc restoration op-amp 32 also changes, so that the voltage and current of the NMOS transistor MN0 are converted, the current flowing through MN0 increases or decreases, the output dc level of the transimpedance amplifier stage is forced to restore to a level similar to Vdummy, and the output dc level Vout1 of the transimpedance amplifier stage and the input dc level V2 of the differential amplifier stage are re-matched, thereby improving the stability of the whole circuit.
The foregoing embodiments of the present invention are not intended to limit the technical scope of the present invention, and therefore, any minor modifications, equivalent variations and modifications made to the above embodiments according to the technical principles of the present invention still fall within the scope of the technical proposal of the present invention.
Claims (3)
1. A circuit for increasing the output dc level of a transimpedance amplifier stage in a TIA, characterized by: the device comprises a transimpedance amplifying stage, a differential amplifying stage, a level lifting unit and a direct current recovery loop; the input end of the transimpedance amplifying stage is used for inputting a photocurrent signal, and the output end of the transimpedance amplifying stage is directly connected with the input end of the differential amplifying stage;
the DC recovery loop comprises a pseudo-transimpedance amplifier stage, a first filter unit, a second filter unit, a DC recovery operational amplifier and a DC passage unit, wherein the transimpedance amplifier stage and the pseudo-transimpedance amplifier stage are connected in parallel between a power supply VDD and a level lifting unit, the output end of the transimpedance amplifier stage is connected with the inverting input end of the DC recovery operational amplifier through the first filter circuit, the output end of the pseudo-transimpedance amplifier stage is connected with the non-inverting input end of the DC recovery operational amplifier through the second filter unit, the output end of the DC recovery operational amplifier is connected with the DC passage unit, and the DC passage unit is also connected with the input end of the transimpedance amplifier stage;
the level lifting unit comprises a tail current source Itail and a capacitor C3, wherein the tail current source Itail and the capacitor C3 are connected in parallel, one end of the tail current source Itail is connected with a transimpedance amplifier stage and a pseudo transimpedance amplifier stage, and the other end of the tail current source Itail is grounded;
the pseudo-transimpedance amplifier stage comprises a PMOS tube MP2, an NMOS tube MN2 and a resistor Rdummy, wherein the source electrode of the PMOS tube MP2 is connected with a power supply VDD, the grid electrode is connected with one end of the resistor Rdummy, and the drain electrode is connected with the other end of the resistor Rdummy; the grid electrode of the NMOS tube MN2 is connected with one end of the grid electrode of the resistor Rdummy connected PMOS tube MP2, the drain electrode of the NMOS tube MN2 is connected with one end of the drain electrode of the resistor Rdummy connected PMOS tube MP2, the source electrode of the NMOS tube MN2 is connected with the level lifting unit, the resistor Rdummy is connected with the drain electrode of the PMOS tube MP2, and one end of the drain electrode of the NMOS tube MN2 is used as the output end of the pseudo-transimpedance amplifier stage to be connected to the second filter unit;
the direct current path unit comprises an NMOS tube MN0, wherein the grid electrode of the NMOS tube MN0 is connected with the output end of the direct current recovery operational amplifier, the drain electrode of the NMOS tube MN0 is connected with the input end of the transimpedance amplifier stage, and the source electrode of the NMOS tube MN0 is grounded;
the direct current recovery operational amplifier comprises a PMOS tube MP7, an NMOS tube MN7, a PMOS tube MP8, an NMOS tube MN8, a PMOS tube MP9, a resistor Rc, a capacitor Cc, a tail current source Itail2 and a tail current source Itail3, wherein the grid electrode of the NMOS tube MN7 is connected with the inverting input end of the direct current recovery operational amplifier, the source electrode is grounded through the tail current source Itail2, the drain electrode is connected with the drain electrode of the PMOS tube MP7 on one hand, the drain electrode of the NMOS tube MN7 is also connected with the grid electrode of the PMOS tube MP7, and the source electrode of the PMOS tube MP7 is connected with a power supply VDD;
the grid electrode of the NMOS tube MN8 is connected with the non-inverting input end INP of the direct current recovery operational amplifier, the source electrode is grounded through the tail current source Itail2, the drain electrode is connected with the drain electrode of the PMOS tube MP8 on one hand, and the drain electrode is connected with the output end of the direct current recovery operational amplifier through the resistor Rc and the capacitor Cc on the other hand in sequence; the grid electrode of the PMOS tube MP8 is connected with the grid electrode of the PMOS tube MP7, and the source electrode of the PMOS tube MP8 is connected with the power supply VDD;
the grid electrode of the PMOS tube MP9 is connected with the drain electrode of the PMOS tube MP8, the source electrode of the PMOS tube MP9 is connected with the power supply VDD, the drain electrode of the PMOS tube MP9 is grounded through the tail current source Itail3 on one hand, and on the other hand, the drain electrode of the PMOS tube MP9 is connected with the output end of the direct current recovery operational amplifier.
2. A circuit for increasing the dc level of a transimpedance amplifier stage output in a TIA according to claim 1, wherein: the transimpedance amplifier stage comprises a PMOS tube MP1, an NMOS tube MN1 and a variable resistor RF, wherein the grid electrode of the PMOS tube MP1 is connected with the input end IN of the transimpedance amplifier stage, the source electrode is connected with a power supply VDD, and the drain electrode is connected with the output end of the transimpedance amplifier stage; the grid electrode of the NMOS tube MN1 is connected with the input end of the transimpedance amplifier stage, the source electrode is connected with the level lifting unit, and the drain electrode is connected with the output end of the transimpedance amplifier stage; one end of the variable resistor RF is connected with the input end of the transimpedance amplifier stage, and the other end of the variable resistor RF is connected with the output end of the transimpedance amplifier stage.
3. A circuit for increasing the dc level of the output of a transimpedance amplifier stage in a TIA according to claim 2, wherein: the first filter circuit comprises a resistor R1 and a capacitor C1, one end of the resistor R1 is connected with the output end of the transimpedance amplifier stage, the other end of the resistor R1 is grounded through the capacitor C1, and meanwhile, one end of the resistor R1 connected with the capacitor C1 is also connected with the inverting input end of the direct current recovery operational amplifier; the second filtering unit comprises a resistor R2 and a capacitor C2, one end of the resistor R2 is connected with the output end of the pseudo-transimpedance amplifier stage, the other end of the resistor R2 is grounded through the capacitor C2, and meanwhile, one end of the resistor R2 connected with the capacitor C2 is also connected with the non-inverting input end of the direct current recovery operational amplifier.
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| JP2013115562A (en) * | 2011-11-28 | 2013-06-10 | Sumitomo Electric Ind Ltd | Transimpedance amplifier |
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| CN108508950A (en) | 2018-09-07 |
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