CN108493307A - A kind of packed LED chip and preparation method thereof - Google Patents
A kind of packed LED chip and preparation method thereof Download PDFInfo
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- CN108493307A CN108493307A CN201810417428.4A CN201810417428A CN108493307A CN 108493307 A CN108493307 A CN 108493307A CN 201810417428 A CN201810417428 A CN 201810417428A CN 108493307 A CN108493307 A CN 108493307A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000010931 gold Substances 0.000 claims abstract description 51
- 229910052737 gold Inorganic materials 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 28
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 448
- 239000004065 semiconductor Substances 0.000 claims description 100
- 239000000758 substrate Substances 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 26
- 239000000956 alloy Substances 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 25
- 229910052751 metal Inorganic materials 0.000 abstract description 25
- 230000005012 migration Effects 0.000 abstract description 16
- 238000013508 migration Methods 0.000 abstract description 16
- 230000007062 hydrolysis Effects 0.000 description 11
- 238000006460 hydrolysis reaction Methods 0.000 description 11
- 229910002601 GaN Inorganic materials 0.000 description 8
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002310 reflectometry Methods 0.000 description 6
- 239000000084 colloidal system Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 238000013467 fragmentation Methods 0.000 description 4
- 238000006062 fragmentation reaction Methods 0.000 description 4
- 210000004209 hair Anatomy 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 2
- 230000032683 aging Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000011514 reflex Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000003301 hydrolyzing effect Effects 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
Abstract
The invention discloses a kind of packed LED chips and preparation method thereof.Wherein, the production method of packed LED chip, including：One light emitting structure is provided, electrode is formed on the light emitting structure, deposits a laminated layer gold in the electrode surface, the alloy-layer is made of Au and Si.The present invention reduces the metal migration in electrode, is effectively increased the reliability of packed LED chip by forming a laminated layer gold on the surface of electrode.
Description
Technical field
The present invention relates to LED technology fields more particularly to a kind of packed LED chip and preparation method thereof.
Background technology
LED (Light Emitting Diode, light emitting diode) be it is a kind of using Carrier recombination when release energy shape
At luminous semiconductor devices, LED chip is with power consumption is low, coloration is pure, long lifespan, small, the response time is fast, energy conservation and environmental protection
Equal many advantages.
Then the existing packed LED chip Cr layers of bottom as electrode forms Al layers, Ti layers, Cr layers, Ti on Cr layers
Layer etc., eventually forms Al layers.But existing packed LED chip applied to display equipment when, due to by use environment with encapsulation
The electrode of the influence of body leakproofness, packed LED chip is easy heated, hydrolytic dissociation and migrates, to shorten LED chip
Service life.
Invention content
Technical problem to be solved by the present invention lies in provide a kind of packed LED chip and preparation method thereof, by electricity
The surface of pole forms a laminated layer gold, reduces the metal migration in electrode, is effectively increased the reliability of packed LED chip.
In order to solve the above technical problem, the present invention provides a kind of packed LED chip production methods, including：
One light emitting structure is provided,
Electrode is formed on the light emitting structure,
A laminated layer gold is deposited in the electrode surface, the alloy-layer is made of Au and Si.
As the improvement of said program, the content of Au is not less than 80% in the alloy-layer.
As the improvement of said program, the electrode includes Cr layers, Al layers, Ti layers and Pt layers successively.
As the improvement of said program, Cr layers of thickness is 10-30 angstroms, and Al layers of thickness is 1000-1500 angstroms, Ti layers
Thickness is 500-1000 angstroms, and Pt layers of thickness is 500-1000 angstroms.
As the improvement of said program, the light emitting structure includes in production method：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer.
As the improvement of said program, the production method of the electrode includes：
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
The electrode is deposited on the exposed region and the second semiconductor layer, the electrode on the first semiconductor layer is
First electrode, it is second electrode, first electrode and the alloy-layer in first electrode to be located at the electrode on the second semiconductor layer
The first alloy electrode is formed, second electrode and the alloy-layer in second electrode form the second alloy electrode.
As the improvement of said program, after forming exposed region, formed before electrode, it is further comprising the steps of：
Transparency conducting layer is formed on second semiconductor layer；
The transparency conducting layer is etched, formed through the transparency conducting layer and extends to the second semiconductor layer table
First hole in face, the second semiconductor layer is exposed.
It is further comprising the steps of after forming alloy-layer as the improvement of said program：
A layer insulating is deposited in alloyed layer, and the insulating layer is etched to form hole, by the alloy
Layer exposes.
Correspondingly, the present invention also provides a kind of packed LED chips, including light emitting structure and the electricity on light emitting structure
Pole, the electrode include Cr layers, Al layers, Ti layers, Pt layers and alloy-layer successively.
As the improvement of said program, the alloy-layer is made of AuSi.
Implement the present invention, has the advantages that：
1, the present invention provides a kind of production methods of packed LED chip, including：A light emitting structure is provided, in the hair
Electrode is formed on photo structure, deposits a laminated layer gold in the electrode surface, the alloy-layer is made of Au and Si.The present invention is logical
It crosses and adulterates Si in Au, during vapor deposition, Si can interrupt the grain size of Au, reduce the grain size of Au, to keep Au more equal
It is deposited evenly on the electrode.In addition, the Si in alloy-layer, which plays metal in blocking Au and electrode, carries out thermal diffusion, to slow down Au
Hydrolysis, migration occurs with the metal in electrode.Further, hydrolysis, migration occur for the Au in the metal and alloy-layer in electrode
Afterwards, the Si in alloy-layer is exposed, exposed Si hairs oxidation, to form silicon oxide film on the surface of electrode
Layer, further slows down the metal in electrode and continues to migrate, be effectively increased the reliability of LED chip.The present invention by
The surface of electrode forms a laminated layer gold, reduces the metal migration in electrode, is effectively increased the reliability of packed LED chip.
Description of the drawings
Fig. 1 is packed LED chip production method flow diagram of the present invention；
Fig. 2 is the structural schematic diagram of packed LED chip of the present invention.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, the present invention is made into one below in conjunction with attached drawing
Step ground detailed description.
Referring to Fig. 1, Fig. 1 is packed LED chip production method flow diagram of the present invention, a kind of formal dress provided by the invention
LED chip production method, includes the following steps：
S1：One substrate is provided；
The material of substrate can be sapphire, silicon carbide or silicon, or other semi-conducting materials, in the present embodiment
Substrate is preferably Sapphire Substrate.
S2：Form epitaxial layer；
Specifically, forming epitaxial layer in the substrate surface, the epitaxial layer includes being sequentially arranged in the substrate surface
First semiconductor layer, active layer and the second semiconductor layer.
Specifically, the first semiconductor layer provided by the embodiments of the present application and the second semiconductor layer are gallium nitride-based semiconductor
Layer, active layer are gallium nitride base active layer；In addition, the first semiconductor layer provided by the embodiments of the present application, the second semiconductor layer and
The material of active layer can also be other materials, be not particularly limited to this application.
Wherein, the first semiconductor layer can be n type semiconductor layer, then the second semiconductor layer is p type semiconductor layer；Alternatively,
First semiconductor layer is p type semiconductor layer, and the second semiconductor layer is n type semiconductor layer, for the first semiconductor layer and second
The conduction type of semiconductor layer needs to be designed according to practical application, is not particularly limited to this application.
It should be noted that in order to improve the yield of subsequent etching technics, the thickness of the epitaxial layer is 4-10 μm.When
The thickness of epitaxial layer is less than 4 μm, and the brightness of LED chip can reduce, and in subsequent etching, LED chip is susceptible to the feelings of sliver
Condition.But the thickness of epitaxial layer is more than 10 μm, and the brightness of LED chip can reduce, and increase difficulty and the time of etching.
It should be noted that in the other embodiment of the application, caching is equipped between the substrate and the epitaxial layer
Rush layer (not shown).
S3：The epitaxial layer is performed etching, exposed region is formed；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer.
Specifically, using photoresist or SiO2As mask, and use inductively coupled plasma etching technique or reaction
Ion etching etching technics performs etching the epitaxial layer, through second semiconductor layer and active layer and extends to described
First semiconductor layer exposes first semiconductor layer, to form exposed region.Due to photoresist and SiO2Have
High etching ratio improves the precision of etching convenient for etching to form required etching pattern.In the other embodiment of the application
In, the substance of other high etching selection ratios can also be used as mask.
In order to improve the light extraction efficiency of chip, the side light extraction efficiency of epitaxial layer is improved, the shape of the exposed region is
Inverted trapezoidal.In the other embodiment of the application, the shape of the exposed region can also be polygon.
S4：Form electrode；
Deposit the electrode on the exposed region and the second semiconductor layer, the electrode includes Cr layers successively, Al layers,
Ti layers and Pt layers.In the other embodiment of the application, electrode can also include other metal layers, and the sequence between metal layer
It can be interchanged.
Specifically, using electron beam evaporation plating, hot evaporation or magnetron sputtering technique respectively in the exposed region and the second half
The electrode is deposited in conductor layer.Wherein, it is first electrode to be located at the electrode on the first semiconductor layer, is located at the second semiconductor layer
On electrode be second electrode.
It should be noted that the present invention uses Cr layers to be used as bottom, since Cr has good conductive property, and Cr gold
Good Ohmic contact can be carried out with epitaxial p type gallium nitride by belonging to, therefore can be effectively reduced contact resistance；Secondly Cr metals with
Epitaxial p type gallium nitride adhesion strength is preferable, and avoidable alloy-layer falls off.Then, Al layers, Ti layers and Pt are formed on Cr layers successively
Layer.Wherein, Al layers of the reflectivity is compared with Cr floor heights, to improve the light extraction efficiency of chip.Further, due to Ti and Pt
Stability it is preferable, therefore Ti layers and Pt layers are formed on Al layers, the Al that can be effectively prevent in Al layers occurs dissolving, moves
Move, on alter.Due to during LED chip packaging and routing, encapsulating used colloid and technique, air cannot be prevent completely
Middle steam enters and colloid need to pass through high-temperature baking so that dissolving, migration occur for the Al in Al layers.Ti layers in the present invention and
Pt layers can prevent corrosion of the steam to Al layers.
Cr layers of the thickness is 10-30 angstroms, and Al layers of thickness is 1000-1500 angstroms, and Ti layers of thickness is 500-1000
Angstrom, Pt layers of thickness is 500-1000 angstroms.
Preferably, Cr layers of the thickness is 15-20 angstroms, and Al layers of thickness is 1200-1400 angstroms, and Ti layers of thickness is
650-850 angstroms, Pt layers of thickness is 650-850 angstroms.
Since Cr layers are used as bottom adhesion layer, thickness cannot be too thick, otherwise can influence the luminous suction of LED chip
It receives, i.e. Al layers does not have reflex.Cr layer thickness has preferable reflectivity at 10-30 angstroms, adhesion strength when being less than 10 angstroms
Poor and control difficulty is big.Wherein, when Al layers of the thickness is less than 1000 angstroms, Al layers of reflectivity cannot preferably be played
Can, chip brightness is relatively low；When Al layers of the thickness is more than 2000 angstroms, because Al metals itself are relatively active easy to migrate, Al layers
Difficulty is protected to increase.When Pt layers of thickness is respectively less than 500 angstroms, Pt layer thickness is too thin can not to play the role of Al layers of protection, work as Pt
When the thickness of layer is all higher than 1000 angstroms, cost of manufacture is excessively high.
S5：Form alloy-layer；
A laminated layer gold is deposited in the first electrode and second electrode surface, the alloy-layer is made of Au and Si.
Specifically, using electron beam evaporation plating, hot evaporation or magnetron sputtering technique on the Pt layers deposit alloy layer.Its
In, first electrode and alloy-layer in first electrode form the first alloy electrode, second electrode and in second electrode
Alloy-layer form the second alloy electrode.
Preferably, the thickness of the alloy-layer is more than 5000 angstroms.
It should be noted that the hardness of Au and Si is preferable, to the active force of electrode when can effectively resist routing, to protect
Electrode is protected, prevents fragmentation and falls off.Due to when routing, needing to electrode into strike, therefore electrode can be generated
One active force, so that electrode is easy to fall off and fragmentation.
When being powered, hydrolysis, migration can occur electrode for the metal in electrode, the present invention by the surface of electrode formed by
Alloy-layer made of Au and Si can effectively slow down the metal in electrode and hydrolysis, migration occurs.Specifically, the present invention by
Si is adulterated in Au, during vapor deposition, Si can interrupt the grain size of Au, reduce the grain size of Au, to make Au more uniformly
Vapor deposition is on the electrode.
In addition, the Si in alloy-layer, which plays metal in blocking Au and electrode, carries out thermal diffusion, to slow down in Au and electrode
Metal occur hydrolysis, migration.
Further, after hydrolysis, migration occur for the Au in the metal and alloy-layer in electrode, the Si in alloy-layer is exposed
Out, exposed Si hairs oxidation further slows down in electrode to form silicon oxide film layer on the surface of electrode
Metal continues to migrate, and is effectively increased the reliability of LED chip.
Preferably, the content of Au is no less than 80% in alloy-layer, when the content of Si is more than 20%, can increase LED chip
Voltage, have an effect on subsequent routing.
It should be noted that in order to improve the brightness of chip, make the homogeneous current distribution of chip, formed exposed region it
Afterwards, it is formed before first electrode, it is further comprising the steps of：
Transparency conducting layer is formed on second semiconductor layer；
The transparency conducting layer is etched, formed through the transparency conducting layer and extends to the second semiconductor layer table
First hole in face, and one layer of electrode is deposited in first hole, form second electrode.
It should be noted that in order to protect chip, prevent chip from leaking electricity, after forming anti-alloy-layer, further includes
Following steps：
A layer insulating is deposited in alloyed layer, and the insulating layer is etched to form hole, by the alloy
Layer exposes.
Preferably, the material of the transparency conducting layer is tin indium oxide.The insulating protective layer is by SiO2、Si3N4、Al2O3、
TiO2And Ta2O3One or more of be made.
Include light emitting structure and the electricity on light emitting structure the present invention also provides a kind of packed LED chip referring to Fig. 2
Pole 30, the electrode 30 include Cr layers 31, Al layers 32, Ti layers 33, Pt layers 34 and alloy-layer 35 successively.Wherein, alloy-layer 35 by
AuSi is made.
Specifically, the light emitting structure includes substrate 10 and the epitaxial layer 20 positioned at 10 surface of substrate.
Wherein, the material of substrate 10 can be sapphire, silicon carbide or silicon, or other semi-conducting materials, this reality
It is preferably Sapphire Substrate 10 to apply the substrate 10 in example.
The epitaxial layer 20 includes the first semiconductor layer 21, the active layer 22 and second for being sequentially arranged in 10 surface of the substrate
Semiconductor layer 23.
Specifically, 21 and second semiconductor layer 23 of the first semiconductor layer provided by the embodiments of the present application is gallium nitride base half
Conductor layer, active layer 22 are gallium nitride base active layer 22；In addition, the first semiconductor layer 21, second provided by the embodiments of the present application
The material of semiconductor layer 23 and active layer 22 can also be other materials, be not particularly limited to this application.
Wherein, the first semiconductor layer 21 can be n type semiconductor layer, then the second semiconductor layer 23 is p type semiconductor layer；Or
Person, the first semiconductor layer 21 is p type semiconductor layer, and the second semiconductor layer 23 is n type semiconductor layer, for the first semiconductor layer
21 and second semiconductor layer 23 conduction type, need to be designed according to practical application, this application be not particularly limited.
It should be noted that in order to improve the yield of subsequent etching technics, the thickness of the epitaxial layer 20 is 4-10 μm.
When the thickness of epitaxial layer 20 is less than 4 μm, the brightness of LED chip can reduce, and in subsequent etching, LED chip is susceptible to sliver
The case where.But the thickness of epitaxial layer 20 is more than 10 μm, and the brightness of LED chip can reduce, and increase difficulty and the time of etching.
It should be noted that in the other embodiment of the application, it is equipped between the substrate 10 and the epitaxial layer 20
Caching rushes layer (not shown).
Specifically, the electrode 30 on the first semiconductor layer 21 is the first alloy electrode, it is located at the second semiconductor layer 23
On electrode be the second alloy electrode.
It should be noted that the present invention uses Cr layers 31 to be used as bottom, since Cr has good conductive property, and Cr
Metal can carry out good Ohmic contact with epitaxial p type gallium nitride, therefore can be effectively reduced contact resistance；Secondly Cr metals
Preferable with epitaxial p type gallium nitride adhesion strength, avoidable alloy-layer falls off.Then, formed on Cr layers 31 successively Al layers 32, Ti layers
33 and Pt layers 34.Wherein, the reflectivity of the Al layers 32 is high compared with Cr layers 31, to improve the light extraction efficiency of chip.Further
Ground forms Ti layers 33 and Pt layers 34 on Al layers 32, can effectively prevent Al layers since the stability of Ti and Pt are preferable
Al in 32 occur dissolving, migration, on alter.Due to during LED chip packaging and routing, encapsulating used colloid and work
Skill, cannot prevent completely in air that steam enters and colloid need to pass through high-temperature baking so that the Al generations in Al layers 32 dissolve,
Migration.Ti layers 33 and Pt layers 34 in the present invention can prevent corrosion of the steam to Al layers 32.
The thickness of the Cr layers 31 is 10-30 angstroms, and the thickness of Al layers 32 is 1000-1500 angstroms, and the thickness of Ti layers 33 is
500-1000 angstroms, the thickness of Pt layers 34 is 500-1000 angstroms.
Preferably, the thickness of the Cr layers 31 is 15-20 angstroms, and the thickness of Al layers 32 is 1200-1400 angstroms, the thickness of Ti layers 33
Degree is 650-850 angstroms, and the thickness of Pt layers 34 is 650-850 angstroms.
Since Cr layers 31 are used as bottom adhesion layer, thickness cannot be too thick, otherwise can influence the luminous suction of LED chip
It receives, i.e. Al layers 32 do not have reflex.31 thickness of Cr layers corresponds to reflectivity (450nm wavelength) as shown in Fig. 2, 31 thickness of Cr layers
There is preferable reflectivity at 10-30 angstroms, adhesion strength is poor when being less than 10 angstroms and control difficulty is big.Wherein, when Al layers described
When 32 thickness is less than 1000 angstroms, the reflecting properties of Al layers 32 cannot be preferably played, chip brightness is relatively low；When the Al layers 32
Thickness when being more than 2000 angstroms, because Al metals itself are relatively active easy to migrate, the protection difficulty increase of Al layers 32.When the thickness of Pt layers 34
When degree is respectively less than 500 angstroms, 34 thickness of Pt layers is too thin can not to be played the role of protecting Al layers 32, when the thickness of Pt layers 34 is all higher than 1000
Angstrom when, cost of manufacture is excessively high.
It should be noted that the hardness of the Au Si in alloy-layer 34 is preferable, to the work of electrode when can effectively resist routing
Firmly, to guard electrode, prevent fragmentation and fall off.Due to when routing, needing to electrode into strike, therefore meeting
One active force is generated to electrode, so that electrode is easy to fall off and fragmentation.
When being powered, hydrolysis, migration can occur electrode for the metal in electrode, the present invention by the surface of electrode formed by
Alloy-layer made of AuSi can effectively slow down the metal in electrode and hydrolysis, migration occurs.In addition, the AuSi in alloy-layer can
Thermal diffusion is carried out with metal in blocking electrode, hydrolysis, migration occurs to slow down the metal in electrode.
Further, after hydrolysis, migration occur for the metal in electrode, the AuSi in alloy-layer is exposed, and is exposed
The AuSi hair oxidations come further slow down the metal in electrode and continue to move to form oxide film layer on the surface of electrode
It moves, is effectively increased the reliability of LED chip.
It should be noted that in order to improve the brightness of chip, make the homogeneous current distribution of chip, the first semiconductor layer 21 with
Further include transparency conducting layer between electrode 30.
In order to protect alloy-layer 35, prevent chip from short circuit and electric leakage occurs, the surface of the alloy-layer 35 is equipped with insulating layer
40 and through insulating layer 40 hole 41.
With specific embodiment, the present invention is further explained below
Embodiment 1
A kind of packed LED chip production method, including：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
Electrode is respectively formed on the exposed region and on the second semiconductor layer, the electrode includes Cr layers, Al successively
Layer, Ti layers and Pt layers；Wherein, Cr layers of the thickness is 10 angstroms, and Al layers of thickness is 1000 angstroms, and Ti layers of thickness is 500 angstroms,
Pt layers of thickness is 500 angstroms；
A laminated layer gold is deposited in the electrode surface, the alloy-layer is made of Au and Si, the content of Au in alloy-layer
It is 80%.
Embodiment 2
A kind of packed LED chip production method, including：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
Electrode is respectively formed on the exposed region and on the second semiconductor layer, the electrode includes Cr layers, Al successively
Layer, Ti layers and Pt layers；Wherein, Cr layers of the thickness is 15 angstroms, and Al layers of thickness is 1100 angstroms, and Ti layers of thickness is 600 angstroms,
Pt layers of thickness is 600 angstroms；
A laminated layer gold is deposited in the electrode surface, the alloy-layer is made of Au and Si, the content of Au in alloy-layer
It is 85%.
Embodiment 3
A kind of packed LED chip production method, including：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
Electrode is respectively formed on the exposed region and on the second semiconductor layer, the electrode includes Cr layers, Al successively
Layer, Ti layers and Pt layers；Wherein, Cr layers of the thickness is 20 angstroms, and Al layers of thickness is 1200 angstroms, and Ti layers of thickness is 700 angstroms,
Pt layers of thickness is 700 angstroms；
A laminated layer gold is deposited in the electrode surface, the alloy-layer is made of Au and Si, the content of Au in alloy-layer
It is 90%.
Embodiment 4
A kind of packed LED chip production method, including：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
Electrode is respectively formed on the exposed region and on the second semiconductor layer, the electrode includes Cr layers, Al successively
Layer, Ti layers and Pt layers；Wherein, Cr layers of the thickness is 25 angstroms, and Al layers of thickness is 1300 angstroms, and Ti layers of thickness is 800 angstroms,
Pt layers of thickness is 800 angstroms；
A laminated layer gold is deposited in the electrode surface, the alloy-layer is made of Au and Si, the content of Au in alloy-layer
It is 95%.
Embodiment 5
A kind of packed LED chip production method, including：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
Electrode is respectively formed on the exposed region and on the second semiconductor layer, the electrode includes Cr layers, Al successively
Layer, Ti layers and Pt layers；Wherein, Cr layers of the thickness is 30 angstroms, and Al layers of thickness is 1400 angstroms, and Ti layers of thickness is 900 angstroms,
Pt layers of thickness is 900 angstroms；
A laminated layer gold is deposited in the electrode surface, the alloy-layer is made of Au and Si, the content of Au in alloy-layer
It is 95%.
Embodiment 6
A kind of packed LED chip production method, including：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
Electrode is respectively formed on the exposed region and on the second semiconductor layer, the electrode includes Cr layers, Al successively
Layer, Ti layers and Pt layers；Wherein, Cr layers of the thickness is 30 angstroms, and Al layers of thickness is 1500 angstroms, and Ti layers of thickness is 1000
Angstrom, Pt layers of thickness is 1000 angstroms；
A laminated layer gold is deposited in the electrode surface, the alloy-layer is made of Au and Si, the content of Au in alloy-layer
It is 98%.
Comparative example 1
A kind of packed LED chip production method, including：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
Electrode is respectively formed on the exposed region and on the second semiconductor layer, the electrode includes the first Cr successively
Layer, the first Al layers, the 2nd Cr layers, the first Ti layers and the 2nd Al layers；Wherein, the described first Cr layers thickness be 20 angstroms, the first Al
The thickness of layer is 1200 angstroms, and the 2nd Cr layer of thickness is 200 angstroms, and the first Ti layers of thickness is 700 angstroms, and the 2nd Al layers of thickness is
18000 angstroms.
Comparative example 2
A kind of packed LED chip production method, including：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes being sequentially arranged in the first the half of the substrate surface to lead
Body layer, active layer and the second semiconductor layer；
The epitaxial layer is performed etching, forms exposed region, the exposed region through second semiconductor layer and
Active layer simultaneously extends to first semiconductor layer；
Electrode is respectively formed on the exposed region and on the second semiconductor layer, the electrode includes Cr layers, Al successively
Layer, Ti layers and Pt layers；Wherein, Cr layers of the thickness is 30 angstroms, and Al layers of thickness is 1500 angstroms, and Ti layers of thickness is 1000
Angstrom, Pt layers of thickness is 1000 angstroms.
Be fabricated to the chip of same size according to the method for above-described embodiment 1-6 and comparative example 1-2, and to chip into
Row photoelectric properties and burn-in test, burn-in test refers to that chip is placed in ageing oven to light 1000 hours, as a result as follows：
It can be seen that the chip made using production method of the present invention and existing making side from above-mentioned test result
The chip that method is made is compared, and the chip brightness of 1-6 of the embodiment of the present invention is high, and voltage is low, yields is high, power down is few.This
Outside, after aging in 1000 hours, in the case where long-time is powered, comparative example 1-2 electrodes occur hydrolysis, move chip
It moves, therefore voltage is got higher, brightness becomes smaller, and voltage and brightness remain unchanged the chip of embodiment 1-6 after weathering
It is above disclosed to be only a preferred embodiment of the present invention, the power of the present invention cannot be limited with this certainly
Sharp range, therefore equivalent changes made in accordance with the claims of the present invention, are still within the scope of the present invention.
Claims (10)
1. a kind of packed LED chip production method, which is characterized in that including：
One light emitting structure is provided,
Electrode is formed on the light emitting structure,
A laminated layer gold is deposited in the electrode surface, the alloy-layer is made of Au and Si.
2. packed LED chip production method according to claim 1, which is characterized in that the content of Au in the alloy-layer
Not less than 80%.
3. packed LED chip production method according to claim 1 or 2, which is characterized in that the electrode includes Cr successively
Layer, Al layers, Ti layers and Pt layers.
4. packed LED chip production method according to claim 3, which is characterized in that Cr layers of thickness is 10-30 angstroms,
Al layers of thickness is 1000-1500 angstroms, and Ti layers of thickness is 500-1000 angstroms, and Pt layers of thickness is 500-1000 angstroms.
5. packed LED chip production method according to claim 1, which is characterized in that the light emitting structure is in making side
Method includes：
One substrate is provided；
Epitaxial layer is formed in the substrate surface, the epitaxial layer includes the first semiconductor for being sequentially arranged in the substrate surface
Layer, active layer and the second semiconductor layer.
6. packed LED chip production method according to claim 5, which is characterized in that the production method packet of the electrode
It includes：
The epitaxial layer is performed etching, forms exposed region, the exposed region is through second semiconductor layer and active
Layer simultaneously extends to first semiconductor layer；
The electrode is deposited on the exposed region and the second semiconductor layer, it is first to be located at the electrode on the first semiconductor layer
Electrode, it is second electrode, first electrode and the alloy-layer composition in first electrode to be located at the electrode on the second semiconductor layer
First alloy electrode, second electrode and the alloy-layer in second electrode form the second alloy electrode.
7. packed LED chip production method according to claim 6, which is characterized in that after forming exposed region, shape
It is further comprising the steps of before electrode：
Transparency conducting layer is formed on second semiconductor layer；
The transparency conducting layer is etched, formed through the transparency conducting layer and extends to the second semiconductor layer surface
First hole exposes the second semiconductor layer.
8. packed LED chip production method according to claim 7, which is characterized in that after forming alloy-layer, also wrap
Include following steps：
A layer insulating is deposited in alloyed layer, and the insulating layer is etched to form hole, the alloy-layer is naked
Expose.
9. a kind of packed LED chip, including light emitting structure and the electrode on light emitting structure, the electrode includes Cr successively
Layer, Al layers, Ti layers, Pt layers and alloy-layer.
10. packed LED chip according to claim 9, which is characterized in that the alloy-layer is made of AuSi.
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|---|---|---|---|---|
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