CN108490705B

CN108490705B - Array substrate, liquid crystal display panel and display device

Info

Publication number: CN108490705B
Application number: CN201810328914.9A
Authority: CN
Inventors: 曹兆铿; 秦丹丹
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2018-04-13
Filing date: 2018-04-13
Publication date: 2021-08-27
Anticipated expiration: 2038-04-13
Also published as: CN108490705A

Abstract

The invention provides an array substrate, a liquid crystal display panel and a display device, wherein the array substrate comprises a plurality of sub-pixel groups, each sub-pixel group comprises a first sub-pixel and a second sub-pixel which are adjacently arranged and arranged along a row direction, a first area of the first sub-pixel and a second area of the second sub-pixel are adjacently arranged and arranged along the row direction, a second area of the first sub-pixel and a first area of the second sub-pixel are adjacently arranged and arranged along the row direction, the number of strip electrodes in the first area is larger than that of the strip electrodes in the second area, and each sub-pixel utilizes the surplus space of the adjacent sub-pixel to perform opening area compensation so as to enable a part of areas of the sub-pixels to be provided with next strip electrodes, so that the space utilization rate of each sub-pixel is improved, and the penetration rate of a liquid crystal display panel and the display device is increased as much as possible.

Description

Array substrate, liquid crystal display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a liquid crystal display panel and a display device.

Background

The lcd panel is generally composed of a color filter Substrate (CF Substrate), a thin film transistor array Substrate (TFT array Substrate), and a liquid crystal layer (liquid crystal layer) disposed between the two substrates, and the liquid crystal display panel operates by applying a driving voltage to the two glass substrates to control the rotation of liquid crystal molecules of the liquid crystal layer, so as to refract light from the backlight module to generate a picture. Liquid crystal display panels can be classified into the following types according to the alignment of liquid crystals: TN (twisted nematic) mode, VA (vertical alignment) mode, IPS (in-plane switching) mode, FFS (fringe field switching) mode, and the like.

Currently, IPS and FFS modes are the mainstream modes of LCD panels, and the pixel structures of the IPS and FFS mode LCDs are as follows: a pixel electrode and a common electrode are formed on the same substrate. In the IPS mode LCD, the common electrode and the pixel electrode are formed in a comb-tooth shape and formed on the same insulating film. The FFS mode is a display mode in which an IPS mode is improved, in which a pixel electrode is formed to be opposed to a common electrode with an insulating film interposed therebetween. The FFS mode LCD has a structure in which a plurality of slits are formed in a pixel electrode, for example, and controls the alignment of liquid crystal molecules by an electric field (fringe field) formed between an edge (fringe) of the pixel electrode and a common electrode, thereby having characteristics of a wide viewing angle and high transmittance, compared to the IPS mode LCD. In order to increase the transmittance, the number of the strip-shaped electrodes is increased as much as possible, but as the resolution of the display screen increases, the area of each pixel opening area becomes smaller and smaller, and in consideration of the exposure limit, only a limited number of strip-shaped electrodes can be placed in a pixel with a fixed size, so that how to increase the transmittance in the pixel opening area with a limited area becomes an urgent problem to be solved.

Disclosure of Invention

The invention provides an array substrate, a liquid crystal display panel and a display device, which can improve the penetration rate of the array substrate, the liquid crystal display panel and the display device and improve the display effect.

In a first aspect, the present invention provides an array substrate, including: a substrate base plate; the gate lines and the data lines are sequentially arranged on the substrate, the gate lines extend along a row direction and are arranged along a column direction, the data lines extend along the column direction and are arranged along the row direction, the gate lines and the data lines are mutually crossed to define a plurality of sub-pixels, each sub-pixel comprises a first area and a second area which are arranged along the column direction, and the width of the first area along the row direction is greater than that of the second area along the row direction; the first electrode comprises a plurality of strip electrodes arranged in parallel; the partial electrodes of the first electrodes in the first region comprise M strip-shaped electrodes, the partial electrodes of the first electrodes in the second region comprise N strip-shaped electrodes, wherein M is greater than N, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 1; the plurality of sub-pixels comprise a plurality of sub-pixel groups, each sub-pixel group comprises a first sub-pixel and a second sub-pixel which are adjacently arranged and arranged along a row direction, a first area of the first sub-pixel is adjacently arranged and arranged along the row direction with a second area of the second sub-pixel, and the second area of the first sub-pixel is adjacently arranged and arranged along the row direction with the first area of the second sub-pixel; the data lines comprise first data lines and are positioned between the first sub-pixels and the second sub-pixels, the parts of the first data lines, corresponding to each sub-pixel, comprise first branch lines, second branch lines and connecting lines positioned between the first branch lines and the second branch lines, the first branch lines are parallel to the second branch lines, and the inclination of straight lines where the connecting lines are positioned relative to the column direction is larger than that of the straight lines where the first branch lines are positioned relative to the column direction.

In a second aspect, the liquid crystal display panel provided by the invention includes a color film substrate and an array substrate which are correspondingly arranged, and the array substrate adopts the above array substrate.

In a third aspect, the present invention provides a display device, including the above liquid crystal display panel.

The array substrate, the liquid crystal display panel and the display device provided by the embodiment of the invention comprise a plurality of sub-pixels, each sub-pixel comprises a first area and a second area which are arranged along a column direction, a part of electrodes of the first electrodes in the first area comprises M strip-shaped electrodes, a part of electrodes of the first electrodes in the second area comprises N strip-shaped electrodes, wherein M is greater than N, M is an integer which is greater than or equal to 2, and N is an integer which is greater than or equal to 1; the plurality of sub-pixels comprise a plurality of sub-pixel groups, each sub-pixel group comprises a first sub-pixel and a second sub-pixel which are adjacently arranged and arranged along a row direction, a first area of the first sub-pixel and a second area of the second sub-pixel are adjacently arranged and arranged along the row direction, and a second area of the first sub-pixel and a first area of the second sub-pixel are adjacently arranged and arranged along the row direction, so that each sub-pixel can use the spare space of the adjacent sub-pixels to enable a part of areas of the sub-pixels to be provided with lower strip-shaped electrodes, the space utilization rate of each sub-pixel is improved, and the penetration rate of a display panel can be increased as much as possible.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

FIG. 2 is a schematic view of a pixel structure on the array substrate shown in FIG. 1;

FIG. 3 is a cross-sectional view taken along line A1-A2 of FIG. 2;

fig. 4 is a schematic view of a pixel structure of another array substrate according to an embodiment of the invention;

fig. 5 is a schematic view of a pixel structure of another array substrate according to an embodiment of the invention;

FIG. 6 is a sectional view taken along line B1-B2 in FIG. 5;

fig. 7 is a schematic view of a pixel structure of another array substrate according to an embodiment of the invention;

fig. 8 is a schematic view of a pixel structure of another array substrate according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described through embodiments with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention relates to an array substrate, a liquid crystal display panel and a display device which are composed of the array substrate. The grid electrode of the thin film transistor is connected with the grid line of the array substrate and is connected to the grid drive circuit through the grid line, the source electrode of the thin film transistor is connected with the data line and is connected to the data drive circuit through the data line, the drain electrode of the thin film transistor is connected to the pixel electrode, and voltage is loaded to the pixel electrode through the data line, so that a horizontal electric field is formed between the pixel electrode and the common electrode, and image display of the liquid crystal display panel and the display device is further achieved.

Referring to fig. 1, 2 and 3, fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, fig. 2 is a schematic structural diagram of a pixel on the array substrate shown in fig. 1, and fig. 3 is a cross-sectional view taken along a direction a1-a2 in fig. 2. First, the embodiment of the present invention provides an array substrate 10, including a substrate 101, a first electrode 14 formed on the substrate 101, a plurality of data lines 11 and a plurality of gate lines 12, where the plurality of data lines 11 extend along a column direction and are arranged along a row direction, the plurality of gate lines 12 extend along a row direction and are arranged along a column direction, the plurality of data lines 11 and the plurality of gate lines 12 are crossed to define a plurality of sub-pixels P arranged in an array, so as to form a pixel array, and each sub-pixel P in the pixel array at least includes a switching element 13.

Each of the switching elements 13 may be, for example, a thin film transistor including a gate electrode, a semiconductor channel overlapping with the gate electrode, a gate insulating layer disposed between the gate electrode and the semiconductor channel, and a source electrode and a drain electrode electrically connected to both sides of the semiconductor channel, respectively. The gates of the switching elements 13 in the sub-pixels P in the same row are connected to the same gate line 12, and the sources of the switching elements 13 in the sub-pixels P in the same column are connected to the same data line 11. In the present embodiment, the first electrodes 14 are pixel electrodes, one first electrode 14 is disposed in each sub-pixel P, and each first electrode 14 is electrically connected to the drain of the switching element T. In the present embodiment, the gate of the switching element 13 and the gate line 12 may be selectively formed in the same film; the source and drain of the switching element 13 and the data line 11 may be formed by the same film layer. However, the invention is not limited thereto, and in other embodiments, the film relationship between the gate and the gate line and/or the film relationship between the source and the drain and the data line may be designed according to actual requirements. The material of the first electrode can be, for example, a transparent conductive material such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, and the like.

Wherein, each sub-pixel P includes a first region PH1 and a second region PH2, the first region PH1 and the second region PH2 communicate with each other to form an opening region of each sub-pixel P, wherein a width of the first region PH1 in a row direction is greater than a width of the second region PH2 in the row direction.

The plurality of sub-pixels P arranged in an array includes a first sub-pixel P1 and a second sub-pixel P2, a first sub-pixel P1 and a second sub-pixel P2 disposed adjacent thereto and arranged in a row direction form a sub-pixel group, and the plurality of sub-pixel groups are repeatedly arranged to form a pixel array. The first region PH1 of the first subpixel P1 is adjacent to the second region PH2 of the second subpixel P2 and is arranged in a row direction, and the second region PH2 of the first subpixel P1 is adjacent to the first region PH1 of the second subpixel P2 and is arranged in a row direction.

Specifically, in each sub-pixel group, the data line 11 includes a first data line 111 and a second data line 112, the first data line 111 is located between the first sub-pixel P1 and the second sub-pixel P2, the second data line 112 is located on two sides of each sub-pixel group, that is, each sub-pixel group includes one first data line 111 and two second data lines 112, the two second data lines 112 are respectively located on a side of the first sub-pixel P1 away from the second sub-pixel P2, and a side of the second sub-pixel P2 away from the first sub-pixel P1. The first data line 111 includes a first branch line 111a, a second branch line 111b, and a connection line 111c between the first branch line 111a and the second branch line 111b, wherein the first branch line 111a is located between a first region PH1 of the first subpixel P1 and a second region PH2 of the second subpixel P2, the second branch line 111b is located between a second region PH2 of the first subpixel P1 and a first region PH1 of the second subpixel P2, the first branch line 111a is arranged in parallel with the second branch line 111b, an angle θ 1 between a line on which the connection line 111c is located and a row direction is smaller than an angle θ 2 between a line on which the first branch line 111a is located and a row direction, or an inclination of the connection line 111c with respect to a column direction is greater than an inclination of the first branch line 111a and the second branch line 111b with respect to a column direction, and may be: the first branch line 111a and the second branch line 111b extend in the column direction, and only the connection line 111c has a certain inclination with respect to the column direction. In this way, compared to the prior art, it is possible to compensate the partial opening area close to the first branch line 111a in the second sub-pixel P2 for the first sub-pixel P1 adjacent thereto, and simultaneously compensate the partial opening area close to the second branch line 111b in the first sub-pixel P1 for the second sub-pixel P2 adjacent thereto, thereby forming the first and second regions PH1 and PH2 of the first sub-pixel P1 and the first and second regions PH1 and PH2 of the second sub-pixel P2.

In each sub-pixel P, the first electrode 14 includes a plurality of strip electrodes arranged in parallel, the strip electrodes may be formed by, for example, arranging closed slits on the first electrode 14, the ends of the plurality of strip electrodes are connected to each other and connected to the drain of the same corresponding switching element 13, the strip electrodes are arranged in parallel with the first branch line 111a and the second branch line 111b of the first data line 111, and the first branch line 111a and the second branch line 111b of the first data line 111 are arranged in parallel with each other and the second data line 112. As shown in fig. 2, in the embodiment of the invention, the partial electrodes of the first electrode 14 located in the first region PH1 include M stripe electrodes, and the partial electrodes of the first electrode 14 located in the second region PH2 include N stripe electrodes, where M > N, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 1. For example, in the present embodiment, in each sub-pixel P, each first electrode 14 includes two first strip electrodes 141 and one second strip electrode 142, where the two first strip electrodes 141 extend from one end of the first region PH1 away from the second region PH2 to one end of the second region PH2 away from the first region PH 1; the second stripe electrodes 142 include a main electrode 14a and a connection electrode 142b, the main electrode 14a is connected to the adjacent first stripe electrodes 141 through the connection electrode 142b, and in particular, is connected to the first stripe electrodes 141 near a boundary between the first region PH1 and the second region PH2, such that there are three stripe electrodes (two first stripe electrodes 141 and one second stripe electrode 142, respectively) in the first region PH1 of each sub-pixel P, and there are only two first stripe electrodes 141 in the second region PH2 of each sub-pixel P. Of course, fig. 2 only exemplifies the implementation of the embodiment of the present invention by taking three strip-shaped electrodes in each sub-pixel as an example, and the present invention is not limited thereto, and the number of the electrodes in each sub-pixel may be as long as the following settings are satisfied: the partial electrodes of the first electrode 14 in the first region PH1 include M stripe electrodes, and the partial electrodes of the first electrode 14 in the second region PH2 include N stripe electrodes, where M > N, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 1.

With the improvement of the definition requirement of the display device, the PPI (pixel per inch) of the liquid crystal display panel is higher and higher, which results in that the area of the opening area of each sub-pixel is smaller and smaller, and considering the exposure limit in the manufacturing process of the array substrate, a sub-pixel with a fixed size can only place a limited number of strip electrodes, and the area of the opening area of the sub-pixel is smaller, which results in that the number of strips of the pixel electrodes that can be accommodated in each sub-pixel is limited, but in order to meet the requirements of the display device on low power consumption, high contrast and high brightness, the penetration rate of the liquid crystal display panel must be improved, and the reduction of the number of strip electrodes on the array substrate inevitably results in the reduction of the penetration rate of the liquid crystal display panel. In the embodiment of the invention, under the condition that the total area of the opening area of each sub-pixel is approximately unchanged, the extending direction and the structure of the data line between two adjacent sub-pixels are adjusted, so that the two adjacent sub-pixels form the mutual compensation relationship of the opening areas, a part of area of each sub-pixel can be provided with a larger number of strip electrodes, and the penetration rate of the strip electrodes is improved. Especially, under the limitation of exposure limit, when N strip electrodes are placed in each sub-pixel, the space is more spare and there is not enough space for placing N +1 strip electrodes, the method provided by the embodiment of the invention enables each sub-pixel to use the spare space of the adjacent sub-pixel to enable the next N +1 strip electrodes to be placed in a partial area of the sub-pixel, the space utilization rate of each sub-pixel is improved, and the penetration rate of the display panel can be increased as much as possible, wherein N is an integer greater than or equal to 1.

For example, due to the limitation of exposure limit in the manufacturing process, when the width of each sub-pixel opening area is about 25um, two strip-shaped electrodes are suitable to be placed, when the width of each sub-pixel opening area is about 31um, three strip-shaped electrodes are suitable to be placed, when the width of each sub-pixel opening area is between 25-31um, because the exposure limit is exceeded, only two strip-shaped electrodes can be placed in each sub-pixel at most, so that the light efficiency is not optimal, and a certain transmittance is lost. In the present embodiment, it is set that: the width of each sub-pixel group along the row direction may be 56um, for example, by a mutual compensation design between two adjacent sub-pixels, the width of the first region PH1 along the row direction of each sub-pixel is 31um, three strip electrodes are disposed in the first region PH1, the width of the second region PH2 along the row direction of each sub-pixel is 25um, and two strip electrodes are disposed in the second region PH2, that is: let M =3 and N = 2. The method can enable each sub-pixel to use the spare space of the adjacent sub-pixel to enable the lower N +1 strip-shaped electrodes to be placed in a partial area of the sub-pixel, the space utilization rate of each sub-pixel is improved, and the penetration rate of the display panel can be increased as much as possible, wherein N is an integer larger than or equal to 1.

Further, in the present embodiment, the main electrode 14a of the second stripe electrode 142 is parallel to the first stripe electrode 141, and the connection electrode 142b is parallel to the connection line 111c of the first data line 111.

Further, in this embodiment, the connection line 111c of the first data line 111 is located in the middle of each sub-pixel group, and the center point of the connection line 111c of the first data line 111 coincides with the center point of each sub-pixel group, so that the opening areas of the first sub-pixel P1 and the second sub-pixel P2 are equal, and the display areas of the two sub-pixels are equal, thereby improving the display uniformity of the liquid crystal display panel.

In this embodiment, the first electrode 14 is a pixel electrode, the array substrate 10 further includes a second electrode 15, and the second electrode 15 is, for example, a whole surface type and is provided with a common voltage signal by an external driving unit, that is, in this embodiment, the second electrode 15 is a common electrode and forms a potential difference between the pixel electrode and the common electrode according to a signal from a data line. As for the film structure of the array substrate 10, specifically, for example, it may be: providing a substrate 101, forming a first metal layer on the substrate 101, and patterning the first metal layer to form a gate line and a gate of a switching element; forming a gate insulating layer 102 to cover the gate line and the first metal layer where the gate electrode is located, and then forming an active layer on the gate insulating layer to be partially overlapped with the gate electrode; forming a second metal layer, imaging the second metal layer to form a data line and a source electrode and a drain electrode of the switching element, wherein the source electrode and the drain electrode of the switching element are respectively in electric contact with two ends of the active layer, and a channel of the switching element is formed between the source electrode and the drain electrode; forming a planarization layer 103 covering the second metal layer where the data line, the source electrode and the drain electrode are located, and simultaneously playing roles of planarization and insulation; forming a common electrode; forming an insulating layer 104 covering the common electrode; a pixel electrode layer is formed, and patterned to form the first electrode 14, and the common electrode and the first electrode 14 may be formed of a transparent conductive material, such as a metal oxide transparent material, for example, ITO. In this embodiment, the switch element is an amorphous silicon thin film transistor, but of course, the switch element may also be a low temperature polysilicon thin film transistor or a metal oxide thin film transistor, which is not limited in this embodiment of the present invention.

Fig. 4 is a schematic view of a pixel structure of another array substrate according to an embodiment of the present invention, and the structure of the array substrate provided in this embodiment is similar to that of the array substrate provided in fig. 1 to 3: each sub-pixel group comprises a first sub-pixel P1 and a second sub-pixel P2 which is arranged adjacent to the first sub-pixel P1 and arranged along a row direction, a first region PH1 of the first sub-pixel P1 is arranged adjacent to a second region PH2 of the second sub-pixel P2 and arranged along the row direction, a second region PH2 of the first sub-pixel P1 is arranged adjacent to a first region PH1 of the second sub-pixel P2 and arranged along the row direction, a part of the first electrode 14 located in the first region PH1 comprises M strip-shaped electrodes, a part of the first electrode 14 located in the second region PH2 comprises N strip-shaped electrodes, wherein M > N, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 1. The first data line 111 is positioned between the first subpixel P1 and the second subpixel P2, and the second data line 112 is positioned at both sides of each subpixel group. The first data line 111 includes a first branch line 111a, a second branch line 111b, and a connection line 111c located between the first branch line 111a and the second branch line 111b, the first branch line 111a and the second branch line 111b are parallel to each other, and an inclination of the connection line 111c with respect to the column direction is greater than an inclination of the first branch line 111a and the second branch line 111b with respect to the column direction.

Further, in this embodiment, each strip electrode includes a main electrode 14a and a terminal electrode 14f located at the end of each main electrode 14a, where the main electrode 14a is parallel to the first branch 111a of the first data line 111, and the terminal electrode 14f is parallel to the connection line 111c of the first data line 111, or an included angle θ 1 between a straight line where the connection line 111c is located and the row direction is equal to an included angle β 1 between a straight line where each terminal electrode 14f is located and the row direction, so that the light transmittance of the liquid crystal display panel where the array substrate is located can be further improved. For example, it can be set as: the included angle between the straight line where the connecting line 111c is located and the row direction is 35-45 degrees, the included angle between the straight line where each end electrode 14f is located and the row direction is 35-45 degrees, and the end electrodes 14f are parallel to the connecting line 111c of the first data line 111. The end referred to herein may be an end of each strip electrode far from the switching element, and may also refer to two ends of each strip electrode near the upper and lower gate lines, which is not limited by the comparison in the embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating a pixel structure of another array substrate according to an embodiment of the present invention, and fig. 6 is a cross-sectional view taken along a direction B1-B2 in fig. 5, in which the structure of the array substrate provided by this embodiment is similar to that of the array substrate provided in fig. 1-3: each sub-pixel group includes a first sub-pixel P1 and a second sub-pixel P2 disposed adjacent thereto and arranged in a row direction, a first region PH1 of the first sub-pixel P1 is disposed adjacent to a second region PH2 of the second sub-pixel P2 and arranged in the row direction, a second region PH2 of the first sub-pixel P1 is disposed adjacent to a first region PH1 of the second sub-pixel P2 and arranged in the row direction, the first electrode 14 is a stripe electrode formed by a slit, and a part of the first electrode 14 located in the first region PH1 includes M stripe electrodes, and a part of the first electrode 14 located in the second region PH2 includes N stripe electrodes, where M > N, M is an integer equal to or greater than 2, and N is an integer equal to or greater than 1. The first data line 111 is positioned between the first subpixel P1 and the second subpixel P2, and the second data line 112 is positioned at both sides of each subpixel group. The first data line 111 includes a first branch line 111a, a second branch line 111b, and a connection line 111c located between the first branch line 111a and the second branch line 111b, the first branch line 111a and the second branch line 111b are parallel to each other, and an inclination of the connection line 111c with respect to the column direction is greater than an inclination of the first branch line 111a and the second branch line 111b with respect to the column direction. The difference is that in the present embodiment, the first electrode 14 is a common electrode, and a common voltage signal is provided thereto through an external driving unit, for example, the first electrode may be connected to the external driving unit through a common signal line, or may extend to the non-display area of the array substrate and be connected to the external driving unit.

Further, in the present embodiment, the first electrode 14 further includes a shielding electrode 143 covering the data line 11. The shielding electrode 143 is electrically connected to each of the strip electrodes, and can shield an electric field generated by the current signal in the data line 11, for example, in a liquid crystal display panel including the array substrate, the influence of the current signal in the data line 11 on liquid crystal molecules can be shielded, and the display effect of the liquid crystal display panel can be improved.

The array substrate further includes a plurality of second electrodes 15, in this embodiment, the second electrodes 15 are pixel electrodes, and the pixel electrode of each sub-pixel is connected to the drain of the corresponding switching element. The film structure of the array substrate may specifically be, for example: providing a substrate 101, forming a first metal layer on the substrate 101, and patterning the first metal layer to form a gate line and a gate of a switching element; forming a gate insulating layer 102 to cover the gate line and the first metal layer where the gate electrode is located, and then forming an active layer on the gate insulating layer to be partially overlapped with the gate electrode; forming a second metal layer, imaging the second metal layer to form a data line and a source electrode and a drain electrode of the switching element, wherein the source electrode and the drain electrode of the switching element are respectively in electric contact with two ends of the active layer, and a channel of the switching element is formed between the source electrode and the drain electrode; forming a planarization layer 103 covering the second metal layer where the data line, the source electrode and the drain electrode are located, and simultaneously playing roles of planarization and insulation; forming a pixel electrode, wherein in each sub-pixel, the pixel electrode can be a strip electrode or a planar electrode; forming an insulating layer 104 covering the pixel electrode; and forming a common electrode layer, and patterning the common electrode layer to form a common electrode, wherein in each sub-pixel, the common electrode comprises a plurality of strip-shaped electrodes and a shielding electrode, and the shielding electrode is a part of the common electrode. The pixel electrode and the common electrode may be formed of a transparent conductive material, such as a metal oxide transparent material, e.g., ITO. In this embodiment, the switch element is an amorphous silicon thin film transistor, but of course, the switch element may also be a low temperature polysilicon thin film transistor or a metal oxide thin film transistor, which is not limited in this embodiment of the present invention.

In this embodiment, it may be set that: in each sub-pixel P, the strip electrodes of each first electrode 14 include a first strip electrode and a second strip electrode, wherein the first strip electrode extends from one end of the first region PH1 far away from the second region PH2 to one end of the second region PH2 far away from the first region PH 1; the second stripe electrodes include main electrodes and link electrodes, and the main electrodes are connected to the first stripe electrodes adjacent thereto through the link electrodes, and in particular, are connected to the first stripe electrodes near a boundary between the first region PH1 and the second region PH2, so that the number of stripe electrodes in the first region PH1 of each sub-pixel is greater than the number of stripe electrodes in the second region PH2 of each sub-pixel. The surplus space of each sub-pixel can be utilized to enable the lower N +1 strip-shaped electrodes to be placed in partial areas of the sub-pixels, the space utilization rate of each sub-pixel is improved, and the penetration rate of the display panel can be increased as much as possible.

Further, in this embodiment, it may be further configured to: each strip electrode comprises a main electrode and a terminal electrode located at the tail end of each main electrode, wherein the main electrode is arranged in parallel with the first branch line 111a of the first data line 111, the terminal electrode is arranged in parallel with the connecting line 111c of the first data line 111, or an included angle between a straight line where the connecting line 111c is located and a row direction is equal to an included angle between a straight line where each terminal electrode is located and a row direction, and the light transmittance of the display panel where the array substrate is located can be further improved. For example, it can be set as: the included angle between the straight line where the connecting line 111c is located and the row direction is 35-45 degrees, the included angle between the straight line where each end electrode is located and the row direction is 35-45 degrees, and the end electrodes are parallel to the connecting line 111c of the first data line 111. The end referred to herein may be an end of each strip electrode far from the light-emitting element, and may also refer to two ends of each strip electrode near the upper and lower gate lines, which is not limited by the comparison in the embodiment of the present invention.

Fig. 7 is a schematic view of a pixel structure of another array substrate according to an embodiment of the present invention, and the structure of the array substrate provided in this embodiment is similar to the structure of the array substrate provided in fig. 5 and 6: the first electrode 14 is a common electrode, and the first electrode 14 further includes a shielding electrode 143 covering the data line 11. The shield electrode 143 is electrically connected to each of the strip electrodes.

In the present embodiment, in each sub-pixel P, the strip-shaped electrodes of each first electrode 14 include a first strip-shaped electrode 141 and a second strip-shaped electrode 142, wherein the first strip-shaped electrode 141 extends from one end of the first region PH1, which is far away from the second region PH2, to one end of the second region PH2, which is far away from the first region PH 1; the second strip-shaped electrode 142 is connected to the shielding electrode 143 between the two sub-pixels, the shielding electrode 143 between the two sub-pixels covers the first data line 111 and extends along the extending direction of the first data line 111, and specifically, the portion of the shielding electrode 143 between the two sub-pixels, which corresponds to the connection line 111c of the first data line 111, can further improve the transmittance of the display panel where the array substrate is located.

Further, in this embodiment, it may be further configured to: each strip electrode comprises a main electrode and a terminal electrode located at the tail end of each main electrode, wherein the main electrode is arranged in parallel with the first branch line 111a of the first data line 111, the terminal electrode is arranged in parallel with the connecting line 111c of the first data line 111, or an included angle between a straight line where the connecting line 111c is located and a row direction is equal to an included angle between a straight line where each terminal electrode is located and a row direction, and the light transmittance of the display panel where the array substrate is located can be further improved.

Fig. 8 is a schematic view of a pixel structure of another array substrate according to an embodiment of the present invention, where the structure of the array substrate provided in this embodiment is similar to that of the array substrate shown in fig. 4. Further, in the present embodiment, the pixel array includes a gate line 12 extending along a row direction, a first data line 111 extending along a column direction, a second data line 112, and a plurality of sub-pixel groups, each sub-pixel group includes a first sub-pixel P1 and a second sub-pixel P2 disposed adjacent to the first sub-pixel P1 and arranged along the row direction, a part of the first electrode 14 located in the first region PH1 includes M strip electrodes, and a part of the first electrode 14 located in the second region PH2 includes N strip electrodes, where M > N, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 1. The first data line 111 includes a first branch line 111a, a second branch line 111b, and a connection line 111c located between the first branch line 111a and the second branch line 111b, the first branch line 111a, the second branch line 111b, and the second data line 112 are parallel to each other and are disposed obliquely with respect to the row direction, or an included angle between the extension directions of the first branch line 111a, the second branch line 111b, the second data line 112, and the gate line 12 is not equal to 0 ° nor equal to 90 °, an inclination of the connection line 111c with respect to the column direction is greater than an inclination of the first branch line 111a, the second branch line 111b with respect to the column direction, and the plurality of strip electrodes of the first electrode 14 are parallel to each other and are parallel to the extension direction of the second data line.

Further, the plurality of sub-pixel groups include a first sub-pixel group P10 and a second sub-pixel group P20 that are adjacently disposed along a column direction, the second data lines 112 are respectively located at two sides of the first sub-pixel group P10 and the second sub-pixel group P20, the first sub-pixel P1 in the first sub-pixel group P10 and the first sub-pixel P1 in the second sub-pixel group P20 are connected to the same second data line 112 located at the left side thereof, and the second sub-pixel P2 in the first sub-pixel group P10 and the second sub-pixel P2 in the second sub-pixel group P20 are connected to the same second data line 112 located at the right side thereof. The second data line 112 is a broken line extending in a column direction as a whole, wherein a portion of the second data line 112 corresponding to the first sub-pixel group P10 and a portion thereof corresponding to the second sub-pixel group P20 are symmetrically disposed with respect to the gate line 12, or are symmetrically disposed with respect to a row direction, such that an extending direction of the first electrode 14 in the first sub-pixel group P10 and an extending direction of the first electrode 14 in the second sub-pixel group P20 are symmetrically disposed with respect to the gate line 12, and a portion of the first data line 111 corresponding to the first sub-pixel group P10 and a portion thereof corresponding to the second sub-pixel group P20 are also symmetrically disposed with respect to the gate line 12, thereby forming a pseudo-dual-domain structure, which can further increase the transmittance of the array substrate.

The invention also provides a liquid crystal display panel, which comprises an array substrate, a color film substrate and a liquid crystal molecular layer clamped between the array substrate and the color film substrate which are oppositely arranged.

The present invention also provides a display device, including the above liquid crystal display panel and a housing, wherein the housing forms an accommodating space for accommodating the display panel, and the housing may be rigid or flexible, which is not limited in this respect. It should be understood that the display device provided in the embodiment of the present invention may be other display devices with a display function, such as a computer, a television, a vehicle-mounted display device, and the present invention is not limited thereto.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, comprising:

a substrate base plate;

the gate lines and the data lines are sequentially arranged on the substrate, the gate lines extend along a row direction and are arranged along a column direction, the data lines extend along the column direction and are arranged along the row direction, the gate lines and the data lines are mutually crossed to define a plurality of sub-pixels, each sub-pixel comprises a first area and a second area which are arranged along the column direction, and the width of the first area along the row direction is greater than that of the second area along the row direction;

the first electrode comprises a plurality of strip electrodes arranged in parallel;

the partial electrodes of the first electrodes in the first region comprise M strip-shaped electrodes, the partial electrodes of the first electrodes in the second region comprise N strip-shaped electrodes, wherein M is greater than N, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 1;

the plurality of sub-pixels comprise a plurality of sub-pixel groups, each sub-pixel group comprises a first sub-pixel and a second sub-pixel which are adjacently arranged and arranged along a row direction, a first area of the first sub-pixel is adjacently arranged and arranged along the row direction with a second area of the second sub-pixel, and the second area of the first sub-pixel is adjacently arranged and arranged along the row direction with the first area of the second sub-pixel;

the data line comprises a first data line and a second data line, the first data line is located between a first sub-pixel and a second sub-pixel, the part of the first data line corresponding to each sub-pixel comprises a first branch line, a second branch line and a connecting line located between the first branch line and the second branch line, the first branch line is parallel to the second branch line, the inclination of a straight line where the connecting line is located relative to a column direction is larger than that of the straight line where the first branch line is located relative to the column direction, and the included angle between the connecting line and the grid line is 35-45 degrees;

in each sub-pixel, the strip-shaped electrodes comprise a first strip-shaped electrode and a second strip-shaped electrode, the first strip-shaped electrode extends from one end of the first area, which is far away from the second area, to one end of the second area, which is far away from the first area, and the second strip-shaped electrode is located in the first area;

the second strip-shaped electrode comprises a main electrode and a connecting electrode, the main electrode is connected to the first strip-shaped electrode through the connecting electrode and is close to the boundary of the first area and the second area, the main electrode is parallel to the first strip-shaped electrode, and the connecting electrode is parallel to the connecting line of the first data line.

2. The array substrate of claim 1, wherein the first electrode is a pixel electrode, and the array substrate further comprises a common electrode between the pixel electrode and the substrate.

3. The array substrate of claim 1, wherein the first electrode is a common electrode, the array substrate further comprising a pixel electrode, the pixel electrode being located between the common electrode and the substrate.

4. The array substrate of claim 3, wherein the common electrode further comprises a shielding electrode covering the data line.

5. The array substrate of claim 1, wherein a center point of the connection line of the first data line coincides with a center point of each sub-pixel group, and the open areas of the first sub-pixel and the second sub-pixel are equal.

6. The array substrate of claim 1, wherein the width of the first region along the row direction is 31um, and the width of the second region along the row direction is 25um, wherein M =3 and N = 2.

7. The array substrate of claim 1, wherein the data lines further comprise at least two second data lines disposed in parallel and respectively located at two sides of each sub-pixel group, the first branch lines of the first data lines are disposed in parallel with the second data lines, and the stripe electrodes are disposed in parallel with the first branch lines.

8. The array substrate of claim 7, wherein in each sub-pixel, the strip-shaped electrode comprises a main electrode and a terminal electrode at an end of the main electrode, the main electrode is disposed in parallel with the first branch line of the first data line, and the terminal electrode is disposed in parallel with the connection line of the first data line.

9. The array substrate of claim 7, wherein the second data line is disposed obliquely with respect to the gate line;

the plurality of sub-pixel groups comprise a first sub-pixel group and a second sub-pixel group which are adjacently arranged along a column direction, and the part of the second data line corresponding to the first sub-pixel group and the part of the second data line corresponding to the second sub-pixel group are symmetrically arranged relative to the grid line.

10. A liquid crystal display panel comprising the array substrate according to any one of claims 1 to 9.

11. A display device comprising the liquid crystal display panel according to claim 10.