CN108418589B - Dynamic coding and decoding method for single-layer nonvolatile memory - Google Patents

Dynamic coding and decoding method for single-layer nonvolatile memory Download PDF

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CN108418589B
CN108418589B CN201810179013.8A CN201810179013A CN108418589B CN 108418589 B CN108418589 B CN 108418589B CN 201810179013 A CN201810179013 A CN 201810179013A CN 108418589 B CN108418589 B CN 108418589B
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冯丹
童薇
徐洁
李春艳
魏学亮
李帅
张扬
冯雅植
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Huazhong University of Science and Technology
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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Abstract

The invention discloses a dynamic coding and decoding method of a single-layer nonvolatile memory, belonging to the technical field of data coding and decoding. Firstly, compressing the written cache line data; and calculating the space saved by compression, dynamically selecting the coding mode with the best coding effect on the single-layer nonvolatile memory according to the size of the saved space, coding the data by using the space saved by compression, and finally writing the coded data into the single-layer nonvolatile memory array. Meanwhile, the invention also realizes a decoding method corresponding to the dynamic coding mode. The method reduces the writing of the single-layer nonvolatile memory under the extremely small space overhead, thereby reducing the writing energy consumption of the single-layer nonvolatile memory and prolonging the service life, and thus solving the problem that the space overhead is increased for reducing the writing energy consumption of the memory in the prior coding and decoding technology.

Description

Dynamic coding and decoding method for single-layer nonvolatile memory
Technical Field
The invention belongs to the technical field of data coding and decoding, and particularly relates to a dynamic coding and decoding method of a single-layer nonvolatile memory.
Background
Compared with the conventional DRAM technology, the novel Non-Volatile Memory (NVM), such as a Phase Change Memory (PCM) memristor (RRAM), has the advantages of data Non-volatility, high integration and low read latency, and is expected to replace the conventional DRAM to be used as the Memory of the next generation computer system. PCM uses phase change materials such as Ge2Sb2Te2The change in crystalline and amorphous states of (GST) stores logic values 0 and 1. When GST is in the crystalline state, the PCM cell is in a state of low resistance value, at which time the PCM stores a logic value 1. When GST is in the amorphous state, the PCM cell is in a state of high resistance value, at which time the PCM stores a logic value 0. When a current pulse of short duration (about 40ns) but high amplitude is applied to the PCM cell, the PCM cell is momentarily heated to 600 degrees celsius and after the material cools, the PCM cell is in a high resistance (logic 0) state; when a pulse of longer duration and lower intensity is applied to a PCM cell, the PCM cell will be in a low resistance (logic value 1) state. During repeated heating, the PCM material may be damaged when writing 106To 109Next time, the PCM cell will fall into a 0 or 1 state and cannot change. The write power consumption of PCM per cell is about 20pJ, which is 2 times that of DRAM. RRAM has similar characteristics to PCM, and the abrasion frequency of the RRAM device is 1010And its write power consumption is several times that of DRAM.
Both PCM and RRAM suffer from high write power consumption, limited write times or lifetime. How to reduce the writing energy consumption of the novel nonvolatile memory and simultaneously improve the service life of the novel nonvolatile memory is a very critical problem.
Existing approaches propose to reduce bit flips (i.e., write from 0 to 1, write from 1 to 0) for writing NVM by way of data encoding. One of the methods proposed at the earliest is called Flip-N-Write. The core idea of this method is to assign a flag bit of one bit to every N bits of data. The initial value of the flag bit is 0. If the bit flip required for writing the N bits of data and the 1 bit of flag bit exceeds (N +1)/2, the N bits of data are inverted bit by bit while the flag bit is set to 1, and then writing is performed. Flip-N-Write reduces bit flips while at the same timeThe flag bits it introduces also cause a 1/N capacity overhead. The effect of the reduction of Flip-N-Write bit flips is limited by the overhead of the flag bit. When N equals 16, the flag bit results in a capacity overhead of 1/16, while Flip-N-Write can reduce bit flips by 14.6%. When N is equal to 2, the capacity overhead by the flag bit is 50%, but Flip-N-Write can reduce bit flips by 25%. Still other approaches are to arrange the data of the cache lines in a matrix called N rows and M columns and then use Flip-N-Write for both rows and columns. There is also a rule for the number of times of writing of hot data, and Flip-N-Write is applied to reduce the writing of hot data, but these methods bring a lot of extra space. In addition, the FlipMin coding scheme is based on coset coding: adding k bits of redundant bits while mapping the data to a data set comprising 2kSet of elements, before each write, from these 2kThe encoding method also incurs a large amount of space overhead when selecting a write with the least bit flipping from the set of elements.
At present, no coding mode aiming at a single-layer nonvolatile memory exists, which can reduce the write energy consumption of the nonvolatile memory, prolong the service life and not increase excessive space overhead.
Disclosure of Invention
The invention provides a dynamic coding and decoding method of a single-layer nonvolatile memory, aiming at combining data compression and data coding, dynamically selecting a proper coding mode according to the compression rate, and simultaneously using the space saved by compression as a flag bit of coding to reduce the writing of the single-layer nonvolatile memory under the extremely small space overhead, thereby reducing the writing energy consumption of the single-layer nonvolatile memory and prolonging the service life, and thus solving the problem that the space overhead is increased for reducing the writing energy consumption of the memory in the prior coding and decoding technology.
In order to achieve the above object, the present invention provides a dynamic encoding and decoding method for a single-layer nonvolatile memory, the method including an encoding method and a decoding method:
the encoding method includes the steps of:
(1) compressing the written cache line data;
(2) if the cache line data can not be compressed, directly sending the cache line data to the write controller, and ending; otherwise, entering the step (3);
(3) if the space S saved after the cache line is compressed is more than or equal to (T-N × P)/2, a FlipMin coding mode is selected to code the compressed data, otherwise, a Flip-N-Write coding mode is selected to code the compressed data, wherein T represents the digit number of the cache line and is preset 512, N represents the word number of each cache line and is preset 8, P represents the digit number of prefix bits and is preset 3;
(4) the encoded data is written into the non-volatile memory array.
Further, the step (1) specifically includes:
(11) grouping the cache line data by taking a word as a unit, and presetting the size of the word to be 64; and compressing each word respectively;
(12) setting a compression flag bit to record whether cache line data can be compressed or not, recording the cache line data as compressible data and recording 1 if a word in the cache line can be compressed, otherwise recording the cache line data as incompressible data and recording 0, and presetting the size of the compression flag bit as 1 bit;
(13) and setting prefix bits for each word in the cache line capable of being compressed to record compression information, wherein the size of the prefix bits is preset to be 3 bits.
Further, the recording information of the compressed word in the step (13) includes: the size of the compressed word and the pattern of the compressed word.
Further, the compression algorithm is preferably an FPC compression algorithm.
Further, after the data in the step (1) is compressed, the compressed flag bit, the prefix bit and the encoded data are continuously stored from high bit to low bit.
Further, if the cache line data cannot be compressed in the step (2), the compressed flag bit and the cache line data are stored continuously from the high bit to the low bit and then sent to the write controller.
Further, the space saved after the cache line compression in the step (3) is performed
Figure BDA0001588189980000041
Wherein, CiThe number of bits of the ith compressed word.
Further, in the step (3):
if 1 is less than or equal to S < (T-N × P)/3, selecting a Flip-N-Write coding mode to code the compressed data, allocating a flag bit to each M bits of data bits,
Figure BDA0001588189980000042
if (T-N × P)/3 is less than or equal to S < (T-N × P)/2, the Flip-N-Write coding mode is selected to code the compressed data, and a flag bit is allocated to each 2-bit data bit.
Further, the step (4) is specifically to determine whether there is old data stored in a unit that is the same as new data to be written before writing data, if so, the unit does not need to perform a write operation, otherwise, the unit performs the write operation.
Further, the decoding method specifically includes:
s1, reading the compressed flag bit and the compressed cache line data from the nonvolatile memory unit;
s2, judging whether the cache line is compressed and encoded according to the compression flag bit;
s3, if the cache line is not compressed, the read cache line data does not need to be decompressed or decoded; if the cache line is compressed, reading prefix bits in the cache line, and determining the space saved by compression according to the prefix bits, thereby determining the encoding method adopted by the cache line data and decoding the cache line data by adopting a corresponding decoding method.
Generally, compared with the prior art, the technical scheme of the invention has the following technical characteristics and beneficial effects:
(1) the invention combines data compression and data coding, uses the space saved by compression as coding, can improve the service life of the single-layer nonvolatile memory under the extremely small space overhead (0.2 percent), and simultaneously reduces the energy consumption of the single-layer nonvolatile memory;
(2) the invention dynamically selects a coding mode with the best effect according to the space saved by compression, fully utilizes the space saved by compression to select the coding mode with the best effect, and furthest prolongs the service life of the single-layer nonvolatile memory and reduces the energy consumption;
(3) the invention adopts a read-to-write mode, can avoid redundant writing and can reduce the writing energy consumption.
Drawings
FIG. 1 is a flow chart of an implementation of the encoding method of the present invention;
FIG. 2 illustrates the arrangement of cache lines after data compression according to the present invention;
FIG. 3 is a schematic diagram of the data decoding of the present invention;
fig. 4 is a schematic diagram of the FlipMin encoding.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The invention is further described in the following examples in conjunction with the following figures:
in this embodiment, the write to the memory by the upper level cache system is in units of cache lines, and the typical cache line size is 64 bytes (64B), so the patent assumes that the cache line size is 64B. The size of the word in the patent is 64 bits (64b), the compression method can adopt any other compression method, and the embodiment of the patent takes an FPC compression algorithm as an example.
As shown in fig. 1, the encoding method according to the embodiment of the present invention includes:
for each write request, it is first determined whether compression is possible. If the compression can not be carried out, the data is directly sent to a write controller and finally written into the storage array, and meanwhile, the compression flag position is set to be 0.
If the data can be compressed, firstly compressing the cache line data of the write request, then calculating the compressed data bit number and the space bit number saved by compression, and setting the compression flag position to be 1. Assuming that the number of space bits saved by compression is S and the number of data bits after compression is D, the data after compression is encoded according to the following rules:
if S <163, encoding the compressed data bits using Flip-N-Write while assigning a flag bit for each D/S bit;
if 163< > S <244, encoding the compressed data bits using Flip-N-Write while assigning a flag bit of one bit to each 2-bit data bit;
if 244 < S, then the data bits after compression are encoded using FlipMin.
The encoded data bits are sent to a write controller and ultimately written to the memory array.
As shown in fig. 2, for a cache line that can be compressed, the compression flag bit is 1, and each word uses 3-bit prefix bits to identify the type of compression. And the prefix bits are deposited consecutively starting from the upper bits of this cache line. The compressed words are stored consecutively starting with the prefix bit, and for an incompressible cache line, the compressed flag bit is 0, and no prefix bit is used for each word.
As shown in fig. 3, the decoding method includes:
firstly, judging whether the data of the cache line is compressed according to the compression flag bit, if the compression flag bit is 0, the cache line is not compressed, and the cache line does not need to be cached and decoded. If the compression flag bit is 1, it indicates that the cache line is compressible and needs to be decoded.
The method of decoding corresponds to the method of encoding. The prefix bits of the first 24 bits are read first, and the size of the compressed data bits and the space saved by compression can be calculated according to the prefix bits. And (3) judging the encoding mode adopted by the cache line data according to the size of the compressed data bits and the space saved by compression, and then decoding the data bits by using a corresponding decoding method Flip-N-Write decoding or FlipMin decoding. Each compressed word is obtained from the prefix bits after decoding. And finally, decompressing each word by using FPC decompression to obtain the data of each word and the whole cache line.
Other techniques presented in the examples are presented:
the data Compression technique, the Frequency Pattern Compression (FPC) in this embodiment, can compress the data to reduce the number of bits that need to be written. It uses three bits of prefix bits to identify the regularity of the data, thereby reducing the space required for data storage. The FPC compresses in units of 64-bit words, and can compress 7 different data patterns. As shown in table 1.
TABLE 1
Figure BDA0001588189980000071
The first mode is 64-bit all 0 data, which may be represented by a 3-bit prefix bit. In the first mode, all 0's of 64 bits are compressed into 3-bit prefix bits. In the second mode, the upper 56 bits of a word are 0 and the lower 8 bits are variable, which is represented by prefix bits 001. The data after compression is prefix bits plus variable lower 8 bits, so the total number of data bits is 11 bits. In addition to these two alternatives there are also 5 different compressible data patterns. The space that the FPC can save varies for different data patterns.
The Flip-N-Write coding and decoding technology comprises the following steps:
the Flip-N-Write encoding process specifically comprises the following steps:
initializing a flag bit to be written to 0, wherein the bit number and the bit number of an old flag bit are both N bits, combining the Nth K bit data in the N × K bit cache line data to be written with the Nth old flag bit to form K +1 bit data, counting the number of 0, if the number of 0 is more than (K +1)/2, setting the Nth position of the flag to be written to 0, otherwise, setting the Nth position of the flag to be written to 1, and sequentially executing the above processes on all cache line data and each flag bit to be written.
The Flip-N-Write decoding process specifically comprises:
reading out old buffer line data N × K bit and old flag bit N bit, where the Nth K bit data of the buffer line corresponds to the Nth flag bit, if the flag bit is 0, the corresponding K bit data does not execute any operation, otherwise, the data of K bit is executed with negation operation, and the above processes are executed for all data in turn.
FlipMin encoding and decoding technology:
as shown in fig. 4, the FlipMin encoding process specifically includes:
firstly, any one generating matrix G of RM (1, 3) codes is found, and a left inverse matrix G # of G is solved. Using all possible information bits, binary 0000-1111, respectively, the Coset is obtained by multiplying the generation matrix by the information bits0And (coset number 0) sets correspond to all code words. All code words are set to C0，C1，…C15. For any information bit d to be written, firstly multiplying d by G # to obtain Coset (i.e. Coset) corresponding to ddCoset No. d). This element is then xored with the codeword that has been written to obtain the transmission element. This transmission element is associated with Coset0And carrying out XOR on all the code words corresponding to the set to obtain the set of the transmission elements. And finding an element with the least number of 1 in the set as a Coset leader, and then carrying out XOR on the data written by the Cosetleader to obtain a vector to be written after encoding.
Further, the FlipMin decoding process specifically includes:
and multiplying the encoded vector by the generated matrix to obtain an element which is a required element, thereby realizing decoding.
It will be appreciated by those skilled in the art that the foregoing is only a preferred embodiment of the invention, and is not intended to limit the invention, such that various modifications, equivalents and improvements may be made without departing from the spirit and scope of the invention.

Claims (6)

1. A dynamic coding and decoding method of a single-layer nonvolatile memory comprises a coding method and a decoding method, and is characterized in that the coding method comprises the following steps:
(1) compressing the written cache line data; the step (1) specifically comprises:
(11) grouping the cache line data by taking a word as a unit; and compressing each word respectively;
(12) setting a compression flag bit to record whether cache line data can be compressed or not, recording the cache line data as compressible if a word in the cache line can be compressed, and recording the cache line data as incompressible if the cache line data cannot be compressed;
(13) setting prefix bit record compression information for each word in the cache line capable of being compressed;
after the cache line data is compressed, continuously storing the compressed flag bit, the prefix bit and the encoded data from high bit to low bit;
(2) if the cache line data can not be compressed, directly sending the cache line data to the write controller, and ending; otherwise, entering the step (3);
(3) if the space S saved after the cache line is compressed is more than or equal to (T-N × P)/2, a FlipMin coding mode is selected to code the compressed data, otherwise, a Flip-N-Write coding mode is selected to code the compressed data, wherein T represents the bit number of the cache line, N represents the word number of each cache line, P represents the bit number of prefix bits, and the space saved after the cache line is compressed in the step (3)
Figure FDA0002491954960000011
Wherein, CiThe number of bits of the ith compressed word;
in the step (3):
if 1 is less than or equal to S<(T-N × P)/3, selecting a Flip-N-Write encoding mode to encode the compressed data, allocating a flag bit to each M bits of data bits,
Figure FDA0002491954960000012
if (T-N × P)/3 is not more than S < (T-N × P)/2, selecting a Flip-N-Write coding mode to code the compressed data, and distributing a flag bit to each 2-bit data bit;
(4) the encoded data is written into the non-volatile memory array.
2. The dynamic coding/decoding method for single-layer nonvolatile memory as claimed in claim 1, wherein the step (13) of recording the compressed word information comprises: the size of the compressed word and the pattern of the compressed word.
3. The dynamic codec method of claim 1, wherein the compression algorithm is FPC.
4. The dynamic encoding and decoding method of a single-layer nonvolatile memory as claimed in claim 1, wherein in step (2), if the cache line data cannot be compressed, the compressed flag bit and the cache line data are stored continuously from high bit to low bit and then sent to the write controller.
5. The dynamic encoding and decoding method of a single-layer nonvolatile memory according to claim 1, wherein the step (4) is specifically to determine whether there is old data stored in a cell before writing data, and the new data to be written are the same, if there is old data, the cell does not need to perform a write operation, otherwise, the cell performs a write operation.
6. The dynamic coding and decoding method of a single-layer nonvolatile memory according to claim 1, wherein the decoding method specifically comprises:
s1, reading the compressed flag bit and the compressed cache line data from the nonvolatile memory unit;
s2, judging whether the cache line is compressed and encoded according to the compression flag bit;
s3, if the cache line is not compressed, the read cache line data does not need to be decompressed or decoded; if the cache line is compressed, reading prefix bits in the cache line, and determining the space saved by compression according to the prefix bits, thereby determining the encoding method adopted by the cache line data and decoding the cache line data by adopting a corresponding decoding method.
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