CN108415866B

CN108415866B - Intelligent platform management controller

Info

Publication number: CN108415866B
Application number: CN201810162302.7A
Authority: CN
Inventors: 赵孝雪
Original assignee: Shenzhen Forward Industrial Co Ltd
Current assignee: Shenzhen Forward Industrial Co Ltd
Priority date: 2018-02-27
Filing date: 2018-02-27
Publication date: 2020-01-17
Anticipated expiration: 2038-02-27
Also published as: CN108415866A

Abstract

The invention provides an intelligent platform management controller, which is applied to a standard ATCA architecture platform, and is electrically connected with a single-board power supply unit, a sensor unit and a Payload unit; this intelligent platform management controller includes: a protocol processing unit and a logic expansion interface unit; the protocol processing unit is electrically connected with the logic expansion interface unit through an FSMC bus and a PS timing sequence bus; the protocol processing unit is electrically connected with the Payload unit through a UART BUS, and the logic expansion interface unit is electrically connected with the Payload unit through a Local BUS BUS; the protocol processing unit and the logic expansion interface unit are both electrically connected with the single board power supply unit; the protocol processing unit is electrically connected with the sensor unit; and the detection end of the single board power supply unit is connected with the A/D module of the protocol processing unit.

Description

Intelligent platform management controller

Technical Field

The invention belongs to the technical field of data communication, and particularly relates to an intelligent platform management controller.

Background

The advanced Telecom Computing platform is a new generation Industrial Computer architecture based on the CPCI standard organized by the PCI Industrial Computer manufacturers' Group, provides a new standardized platform for the application fields of converged communication, data networks, Computer servers and the like, and has the characteristics of modular structure, strong compatibility, high expansibility and the like. The ATCA defines a series of unified specifications, including a core specification PICMG 3.x of a machine frame structure, power management, heat dissipation management, backboard interconnection and system management, and 5 auxiliary specifications of point-to-point communication are formulated at the same time. The system Management comprises a frame Management unit (Shelf Management Controller, ShMC) and an Intelligent Platform Management Controller (IPMC) unit on each single board, power module, fan plug-in frame assembly and other components, and exchanges equipment information, sensor/event state and the like of each single board/component through Intelligent Platform Management Interface (IPMI) communication, and corresponding instructions are issued in time, so that a strong function is provided for overall system Management, and the safety, stability and robustness of system operation are greatly improved. The mainstream intelligent platform management controller chip or scheme in the market at present has the problems of high cost, poor reliability and weak compatibility.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides an intelligent platform management controller.

Specifically, the embodiment of the present invention provides an intelligent platform management controller, which is applied to a standard ATCA architecture platform, and the intelligent platform management controller is electrically connected to a single board power supply unit, a sensor unit, and a Payload unit; this intelligent platform management controller includes: a protocol processing unit and a logic expansion interface unit;

the protocol processing unit is electrically connected with the logic expansion interface unit through an FSMC bus and a PS timing sequence bus; the protocol processing unit is electrically connected with the Payload unit through a UART BUS, and the logic expansion interface unit is electrically connected with the Payload unit through a Local BUS BUS; the protocol processing unit and the logic expansion interface unit are both electrically connected with the single board power supply unit; the protocol processing unit is electrically connected with the sensor unit; and the detection end of the single board power supply unit is connected with the A/D module of the protocol processing unit.

As a further improvement of the above technical solution, the protocol processing unit is an ARM processor.

As a further improvement of the above technical solution, the logic expansion interface unit is an FPGA.

As a further improvement of the above technical solution, the logic expansion interface unit is further electrically connected to the ATCA backplane through a dual IPMB bus.

As a further improvement of the above technical solution, the ATCA backplane is divided into 3 functional areas, and the first functional area is used for power supply and IPMB bus communication; the second functional area is used for a base optical interface, a fabric optical interface and a synchronous clock; the third functional area is used for factory self-definition and function expansion of the RTM board; the logic expansion interface unit is electrically connected with the first functional area of the ATCA backplane through a Zone1 power connector.

As a further improvement of the above technical solution, the protocol processing unit includes: the system comprises a main program circulation module, an IPMC standard protocol module, a sensor acquisition and threshold judgment module, a power management control module, a power state acquisition module, a logic expansion unit upgrading module, an FSMC main control module, an interrupt processing module and a Flash control module.

As a further improvement of the above technical solution, the logic expansion interface unit includes: I2C master/slave controller module, I/O expansion logic module, power management control module, FSMC controller module, Local BUS controller module, register access coordination module, interrupt application module and BUS expansion module.

As a further improvement of the above technical solution, the sensor unit includes: a temperature sensor.

As a further improvement of the above technical solution, the intelligent platform management controller further includes: and the storage unit is electrically connected with the protocol processing unit.

As a further improvement of the technical scheme, the storage unit is a Flash memory.

Compared with the prior art, the technical scheme provided by the invention at least has the following beneficial effects: the intelligent platform management controller realizes standard IPMC through cooperative work of the protocol processing unit and the logic expansion interface unit, has the advantages of low cost, high reliability, good compatibility, flexible expansion capability and the like, greatly overcomes the defects of the existing special IC, adopts modular design, has flexible transportability, can effectively shorten the development period of the ATCA single board, and is very convenient for on-line upgrading and later maintenance.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1 is a block diagram of a system management bus connection defined by the ATCA standard;

FIG. 2 is a system block diagram of an intelligent platform management controller according to an embodiment of the present invention;

FIG. 3 is a logical functional block diagram of the protocol processing unit of FIG. 2;

fig. 4 is a logic function block diagram of the logic expansion interface unit in fig. 2.

Description of the main element symbols:

in the figure: 201-logical expansion interface unit; 202-a protocol processing unit; 203-a sensor unit; 204-a single board power supply unit; 205-Payload unit; 206-ATCA backplane; 2010-register array; 2011-I2C master/slave module; 2012-I/O expansion logic module; 2013-power management control module; 2014-FSMC controller module; 2015-Local BUS controller module; 2016-register access coordination module; 2017-interrupt application module; 2018-bus extension module; 2021-main program loop module; 2022-IPMC standard protocol module; 2023-sensor collection and threshold judgment module; 2024-power management control module; 2025-power state acquisition module; 2026-logic expansion unit upgrade module; 2027-an interrupt handling module; 2028-Flash control module; 2029 — FSMC controller module.

Detailed Description

Various embodiments of the present disclosure will be described more fully hereinafter. The present disclosure is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit the scope of the disclosure to the specific embodiments disclosed herein, but rather, the disclosure is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the disclosure.

Hereinafter, the term "includes" or "may include" used in various embodiments of the present disclosure indicates the presence of the disclosed functions, operations, or elements, and does not limit the addition of one or more functions, operations, or elements. Furthermore, as used in various embodiments of the present disclosure, the terms "comprising," "having," and their derivatives, are intended to be only representative of the particular features, integers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to one or more other features, integers, steps, operations, elements, components, or combinations of the foregoing.

Expressions (such as "first", "second", and the like) used in various embodiments of the present disclosure may modify various constituent elements in the various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user equipment and the second user equipment indicate different user equipments, although both are user equipments. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present disclosure.

It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.

The terminology used in the various embodiments of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the present disclosure. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present disclosure belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in various embodiments of the present disclosure.

As shown in fig. 1, the rack system defined by the ATCA standard includes 2 redundant machine frame management boards, several fan insertion frames, several power modules, and several single boards. ShMC is integrated on the machine frame management board and connected with IPMC on each single board, fan plug-in frame and power module through IPMB bus, so as to realize machine frame system management.

Example 1

As shown in fig. 2, an embodiment of the present invention provides an intelligent platform management controller, which is applied to a standard ATCA architecture platform, and the intelligent platform management controller includes: a protocol processing unit 202 and a logic expansion interface unit 201; the intelligent platform management controller is electrically connected with the single board power supply unit 204, the sensor unit 203 and the Payload unit 205. A protocol processing unit 202, a logic expansion interface unit 201, a sensor unit 203, a board power supply unit 204, and a Payload unit 205 are integrated on the main control board service board inserted on the ATCA backplane.

The protocol processing unit 202 is electrically connected with the logic expansion interface unit 201 through an FSMC bus and a PS timing sequence bus; the protocol processing unit 202 is electrically connected with the Payload unit 205 through a UART BUS, and the logic expansion interface unit 201 is electrically connected with the Payload unit 205 through a Local BUS BUS; the protocol processing unit 202 and the logic expansion interface unit 201 are both electrically connected to the board power supply unit 204; the protocol processing unit 202 is electrically connected with the sensor unit 203; the detection end of the board power supply unit 204 is connected to the a/D module of the protocol processing unit 202.

In this embodiment, the protocol processing unit 202 is an ARM processor; the logic expansion interface unit 201 is an FPGA.

The logic expansion interface unit 201 is also electrically connected to the ATCA backplane 206 via the dual IPMB bus. By adopting the double IPMB bus, the system can work in a master mode and a slave mode; therefore, the system can be respectively communicated with 2 machine frame management boards with redundant functions to complete the management control of the single board.

Specifically, the ATCA backplane 206 is divided into 3 functional areas, and the first functional area is used for power supply and IPMB bus communication; the second functional area is used for a base optical interface, a fabric optical interface and a synchronous clock; the third functional area is used for factory self-definition and RTM (Release To Manufacturing) board function expansion; the logic expansion interface unit 201 is electrically connected to the first functional area of the ATCA backplane 206 via dual IPMB buses (IPMB _ A and IPMB _ B).

The logic expansion interface unit 201 realizes 2-lane standard IPMB buses (IPMB _ A and IPMB _ B), is connected to the ATCA backboard 206 through a power connector of Zone1, and realizes communication with ShMC units integrated on a subrack management board; the LocalBUS slave controller can be accessed by the CPU of the Payload unit 205 to acquire all IPMC related information stored in the internal register; meanwhile, the control of the board power supply unit 204 may be performed according to the instruction of the protocol processing unit 202 and by combining with the power-on timing requirement of the board.

The protocol processing unit 202 implements the standard IPMI protocol; the FSMC bus is communicated with the logic expansion interface unit 201, receives or transmits communication data with the ShMC, transmits factory information, sensor/event information, power control/state information and the like of the board card to the logic expansion interface unit 201, and acquires an instruction or data issued by the ShMC from the logic expansion interface unit 201; the management and control of the single board power supply unit 204 are realized according to the ShMC instruction, the single board plugging state, the hot-plugging switch closing state and the like in combination with the single board power-on/power-off sequence requirements; acquiring sensor information in real time, comparing and judging the information with a set threshold group, analyzing whether the heat dissipation state of the board card is normal, reporting ShMC application state skip if necessary, and executing corresponding operation according to an ShMC instruction; and simulating a PS loading time sequence to realize the online upgrading function of the logic expansion interface unit 201.

The sensor unit 203 mainly includes a temperature sensor. The temperature sensors are distributed near the main heating source of the single board to measure the working temperature of the single board in real time. The sensor provides a high temperature alarm function, informs the protocol processing unit 202 in an interrupt mode, ensures that the protocol processing unit 202 can find abnormality in the shortest time, and reports the abnormality to the machine frame management board so that the machine frame management board can perform corresponding protection measures.

A single board power supply unit 204, which mainly provides power supply for all the service chips of a single chip, and performs corresponding power on/off actions by combining with the power on/off sequence requirements of the single board under the control of the protocol processing unit 202 and the logic expansion interface unit 201; meanwhile, the current sampling sensor is provided, so that the output current and the power consumption are recorded in real time and are acquired by the protocol processing unit 202 in real time.

The CPU of Payload unit 205 communicates with protocol processing unit 202 through a UART interface, mainly implementing the online upgrade function of protocol processing unit 202; the Local BUS BUS is connected with the logic expansion interface unit 201, so that an internal register array can be accessed, the state information of the IPMC unit can be acquired, and the working state of the board card can be conveniently monitored on site or remotely by a user and the operation and maintenance can be carried out.

The intelligent platform management controller further comprises: the memory unit is electrically connected to the protocol processing unit 202. The storage unit is a Flash memory.

As shown in fig. 3, the protocol processing unit 202 includes: a main program loop module 2021, an IPMC standard protocol module 2022, a sensor acquisition and threshold value judgment module 2023, a power management control module 2024, a power state acquisition module 2025, a logic expansion unit upgrade module 2026, an interrupt processing module 2027, a Flash control module 2028, and an FSMC controller module 2029.

The main program loop module 2021 implements processing of power-on state jump (M0-M4 state jump) events based on the ATCA standard, including address validation, up/down current control, sending of sensor events, and reporting of state transition events.

The IPMC standard protocol module 2022 implements functions of ATCA standard-based power supply control, sensor/event acquisition and judgment processing, board state event acquisition, board safety connection control, and the like. By realizing the E-key (electronic keying) function, the interconnection safety of the board cards in the rack is ensured. The Fabric interface supported by ATCA has many types, including xaui, 10GBASE-KR, 40GBASE-KR4, PCIe and the like, and the E-KEY function is to inform the interface type of the shmc board, so as to ensure that the board card is allowed to be powered on to work under the condition that the type of the board card is consistent with that of the opposite terminal interface. This is not a problem.

The sensor acquisition and threshold value judgment module 2023 realizes acquisition of all onboard sensor information, compares and judges the onboard sensor information with an upper limit alarm threshold value set by a factory, confirms whether the heat dissipation state of the board card is normal or not, reports the onboard sensor information to the ShMC in time under abnormal conditions, and takes necessary protective measures.

The power management control module 2024 controls the power-on/power-off of the board card according to the ShMC instruction, the plugging/unplugging state of the board card, the closing state of the hot-plug switch, and the power-on/power-off timing sequence requirements of Payload.

The power state acquisition module 2025 acquires the voltage and current output by the single-board power supply unit 204 through the high-precision ADC, compares and judges the voltage and current with the set upper and lower limit thresholds, determines whether the power supply is normal, and reports the voltage and current to the ShMC in time under abnormal conditions, and takes necessary protective measures.

The logic expansion unit upgrading module 2026 is responsible for simulating a PS loading time sequence through a GPIO pin, and sending an upgrading program in a storage unit such as a Flash memory to the logic expansion interface unit 201, thereby implementing online upgrading of the logic expansion interface unit 201.

The interrupt processing module 2027 receives the interrupt request signal sent by the logical expansion interface unit 201, determines the type of the interrupt event by querying the interrupt information table, and responds accordingly.

The Flash control module 2028 is responsible for read-write control of external storage units such as Flash memories, and the storage units mainly store factory information of board cards and store work logs of the board cards; and storing the logic expansion and interface unit upgrading program.

The FSMC controller module 2029 is in the master mode, and implements communication between the protocol processing unit 202 and the logical expansion interface unit 201.

As shown in fig. 4, the logical expansion interface unit 201 includes: register array 2010, I2C master/slave controller module 2011, I/O extension logic module 2012, power management control module 2013, FSMC controller module 2014, Local BUS controller module 2015, register access coordination module 2016, interrupt application module 2017, and BUS extension module 2018.

The I2C master/slave module 2011 adopts an IP core, follows the complete I2C specification, adopts an IPMB bus protocol, receives an instruction from the ShMC and stores the instruction in the register array 2010, sends an interrupt request to notify the protocol processing unit 202, and performs corresponding operations according to the instruction after the protocol processing unit 202 reads the instruction; on the other hand, the data packet sent from the protocol processing unit 202 is read from the register array 2010, reframed according to the IPMB protocol requirement, and sent to the ShMC.

The I/O extension logic module 2012 is configured to logically turn on a lamp, and output a lamp indicating Hot Swap (Hot Swap), OOS (out of service), and the like defined by the panel ATCA according to a corresponding control value in the register array 2010, and a user-defined extension function lamp. And simultaneously, independent reset of all circuits, logic signal expansion of an RTM board and the like are realized.

The power management control module 2013 outputs a power control signal according to the power-on/power-off control information sent by the protocol processing unit 202, and synchronously controls the board card to be powered on and powered off.

The FSMC controller 2014 is in slave mode, and implements communication between the protocol processing unit 202 and the logical expansion interface unit 201.

The Local BUS controller module 2015 is in a slave mode, and realizes communication between the CPU of the Payload unit 205 and the logic expansion interface unit 201, so that the CPU can access information stored in the register array 2010, and a user can conveniently monitor the working state of the board card on site or remotely.

The register access coordination module 2016 is configured to coordinate the FSMC control module 2014 and the Local BUS controller module 2015 to access the register array 2010, and allocate BUS access permission according to a register access state, so as to avoid register access conflict.

The interrupt application module 2017 generates an interrupt according to the related event information, notifies the protocol processing unit 202 to access the interrupt information table to confirm the interrupt information, accesses the related register array 2010 according to the interrupt information, and performs corresponding processing and feedback.

The bus extension module 2018 realizes functions such as richer management, control and extension according to functions and extended buses required to be added by the Payload unit 205.

The online upgrade process of the protocol processing unit 202 specifically includes the following steps: the CPU sends an upgrading instruction through a UART interface to inform the ARM of needing upgrading; the ARM confirms that the working state of the single board is normal, and informs the FPGA to lock a control signal of a single board power system through the FSMC, so that the Payload is ensured to supply power normally, and the current service is ensured not to be interrupted; the FPGA sends an ARM upgrading control signal to enable the ARM to enter an online upgrading mode; the CPU transmits the upgrading program to Flash inside the ARM through the UART; after the ARM is upgraded, an upgrade completion state identification signal is sent to the FPGA, the FPGA sends a reset instruction to the ARM after receiving the state signal to control the ARM to restart, a new system is loaded, and online upgrade is completed.

The online upgrade process of the logic expansion interface unit 201 specifically includes the following steps: the CPU sends an upgrading instruction through a UART interface to inform the FPGA of needing upgrading; the ARM confirms that the working state of the single board is normal, locks a control signal of a power supply system of the single board, ensures that the power supply of Payload is normal, and ensures that the current service is not interrupted; the CPU sends an FPGA upgrading program through the UART, and the ARM receives the FPGA upgrading program and stores the FPGA upgrading program in the external Flash; the ARM simulates a PS loading time sequence with the GPIO and transmits an FPGA upgrading program sequence in the Flash to the FPGA; and after the FPGA finishes upgrading, returning to a DONE mark for finishing upgrading, and after receiving the mark, the ARM sends a reset instruction to control to restart the FPGA, and loads a new program to finish online upgrading.

The intelligent platform management controller completes management control based on the ATCA board card and the module, has strong redundancy robustness, adopts modular design, has high transportability, and effectively improves the period of design and development.

Those skilled in the art will appreciate that the figures are merely schematic representations of one preferred implementation scenario and that the blocks or flow diagrams in the figures are not necessarily required to practice the present invention.

Those skilled in the art will appreciate that the modules in the device in the implementation scenario may be distributed in the device in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules.

The above-mentioned invention numbers are merely for description and do not represent the merits of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.

Claims

1. An intelligent platform management controller is applied to a standard ATCA architecture platform and is characterized in that the intelligent platform management controller is electrically connected with a single-board power supply unit, a sensor unit and a Payload unit; this intelligent platform management controller includes: a protocol processing unit and a logic expansion interface unit;

2. The intelligent platform management controller according to claim 1, wherein the protocol processing unit is an ARM processor.

3. The intelligent platform management controller according to claim 1, wherein the logic expansion interface unit is an FPGA.

4. The SMRC of claim 1 wherein the logic expansion interface unit is further electrically connected to the ATCA backplane via a dual IPMB bus.

5. The intelligent platform management controller according to claim 4, wherein the ATCA backplane is divided into 3 functional zones, the first functional zone is used for power supply and IPMB bus communication; the second functional area is used for a base optical interface, a fabric optical interface and a synchronous clock; the third functional area is used for factory self-definition and function expansion of the RTM board; the logic expansion interface unit is electrically connected with the first functional area of the ATCA backplane through a Zone1 power connector.

6. The intelligent platform management controller according to claim 1, wherein the protocol processing unit comprises: the system comprises a main program circulation module, an IPMC standard protocol module, a sensor acquisition and threshold judgment module, a power management control module, a power state acquisition module, a logic expansion unit upgrading module, an FSMC main control module, an interrupt processing module and a Flash control module.

7. The intelligent platform management controller according to claim 1, wherein the logical expansion interface unit comprises: I2C master/slave controller module, I/O expansion logic module, power management control module, FSMC controller module, LocalBUS controller module, register access coordination module, interrupt application module and bus expansion module.

8. The intelligent platform management controller according to claim 1, wherein the sensor unit comprises: a temperature sensor.

9. The intelligent platform management controller according to claim 1, further comprising: and the storage unit is electrically connected with the protocol processing unit.

10. The intelligent platform management controller according to claim 9, wherein the storage unit is a Flash memory.