CN108398590A - A kind of voltage peak detection circuit of numeral output - Google Patents
A kind of voltage peak detection circuit of numeral output Download PDFInfo
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- CN108398590A CN108398590A CN201710552423.8A CN201710552423A CN108398590A CN 108398590 A CN108398590 A CN 108398590A CN 201710552423 A CN201710552423 A CN 201710552423A CN 108398590 A CN108398590 A CN 108398590A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/255—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with counting of pulses during a period of time proportional to voltage or current, delivered by a pulse generator with fixed frequency
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Abstract
The invention discloses a kind of voltage peak detection circuits of numeral output, the circuit realizes that the voltage peak of numeral output detects using what voltage follower, zero passage voltage comparator, A/D converter, register, binary numeral comparator and three inputs one exported with circuits such as doors, it avoids in traditional scheme and first obtains peak value with the voltage peak detection circuit of simulation, then the voltage peak of simulation is obtained into numeral output by A/D conversion circuits.Compared with prior art, the circuit is simple and reliable, it is suitble to low-and high-frequency measured signal voltage peak to the conversion of number, fast response time, measures conversion precision is high, and peak detection voltage dynamic range is big, and minimum can survey the voltage of μ V magnitudes, and number is facultative small suitable for the main logics circuits such as TTL, COMS, dynamic power loss by force.
Description
Technical field
The present invention relates to a kind of electric circuit constructions, and electricity is detected more specifically to a kind of voltage peak of numeral output
Road.
Background technology
Peak detector is widely used in nuclear radiation detection, geology, automatic growth control, oscillator and RF power
In the feedback protection system of amplifier.Peak detector has simulation output and numeral output peak detector, in noise or does
It disturbs and tracks small-signal under environment, this requires peak detector to have accuracy of detection high, strong antijamming capability and easily controllable
And the features such as signal processing, the peak detector of simulation output cannot meet design requirement due to the limitation of theory structure,
The general peak detector for using numeral output.The peak detection circuit of Contemporary Digital output is due to using first simulated peak
The principle of detection number conversion again, there is that Peak detection accuracy is not high, sample frequency is too low, poor anti jamming capability, Power Capacity
The defects of dividing non-linear ambassador's distorted signals and difficult system debug.
The voltage signal peak value measurement circuit of numeral output is the core of signal data acquisition in basic electric quantity test instrument
Circuit, traditionally voltage signal peak to number conversion is mainly first with the voltage peak detection circuit acquisition Voltage Peak of simulation
Value, then voltage peak is obtained into numeral output by A/D conversion circuits.And the voltage peak detection circuit simulated mainly has two
Kind, one is the peak value measurement circuit of voltage-type, another kind is the peak value measurement circuit of transconductance type.The peak value measurement electricity of voltage-type
Road principle is simple, but integral nonlinearity is big, and passband is small, and dynamic range is also small (general to require to the difference in response of small amplitude signal
Signal is more than 200mV), it is less than satisfactory to the effect for handling fast signal.Although the peak value measurement circuit performance of transconductance type is excellent
In voltage-type, but there is also difficulties in circuit design.Due to the use of trsanscondutance amplifier, there is an integral in loop gain
The factor is related with capacitance C, in order to improve the linear properties of circuit, needs capacitance C as big as possible, and increasing capacitance C can reduce
The passband and Slew Rate of circuit.The voltage peak that such two kinds of circuits detect has hysteresis quality, when peak value is by low level to height
Level change, this level change that subsequent conditioning circuit detects thinks that peak value arrives, while starting and being exported to peak detection circuit
Peak value carries out A/D conversions, and apparent transformed error, the reliability of circuit is brought to depend not only on integrating circuit stability, and
Depending on the waveform of detected signal, false triggering is easily caused to some slow pickup electrodes of variation, seriously affects measurement result.
Invention content
It is an object of the present invention to provide a kind of voltage peak detection circuits of numeral output, it is therefore an objective to overcome existing numeral output
The small signal simulation voltage peak that is primarily present of voltage peak detection circuit is high to D conversion accuracy, conversion speed mistake
The defects of low, poor anti jamming capability and difficult capacitance integral non-linear ambassador distorted signals and system debug.
The solution that the present invention solves its technical problem is：A kind of voltage peak detection circuit of numeral output, including：
Voltage follower, A/D converter, register, zero passage voltage comparator, binary numeral comparator, three input one output with
Door, the in-phase input end of the voltage follower are connect with measured signal, and the output end of the voltage follower is anti-with itself
The in-phase input end connection of phase input terminal, the input end of analog signal of the A/D converter, the zero passage voltage comparator, institute
State the N bit binary numbers signal output end of A/D converter according to the positions N two of binary system power and position sequence and the register into
One N bit binary number of digital input end processed and the binary numeral comparator compares input terminal parallel connection, described
The N bit binary numbers output end of register is according to another of binary system power and position sequence and the binary numeral comparator
N bit binary numbers compare input terminal parallel connection, the clock end of system work clock and the A/D converter and with door the
One input terminal connects, and the output end of the zero passage voltage comparator is connect with described with the second input terminal of door, the zero passage electricity
The inverting input of pressure comparator is connected to ground, and the output end of the binary numeral comparator is inputted with the third with door
End connection, described to be connect with the output end of door with the control terminal of the register, the binary numeral comparator is for comparing
One working pulse value of the N bit binary numbers of the A/D converter digital signal output end output and upper one when arriving
The size of the value of the N bit binary numbers of register deposit when a working pulse, when the zero passage voltage comparator exports
When high level, when the value of A/D converter digital signal output end output is more than the value of the presently described register deposit
When, the binary numeral comparator output terminal exports high level, when a working pulse arrives, is exported with gate output terminal high
Level, the A/D that the register is stored in by the high level control exported with door when a working pulse arrives are converted
The N bit binary numbers of device digital signal output end output, when the value of A/D converter digital signal output end output is less than
Or equal to the presently described register deposit value when, the binary numeral comparator output terminal exports low level, with door
Output end exports low level, and the register is kept depositing when a upper working pulse by the low level control exported with door
Data it is constant, the binary numeral comparator system work clock effect under be constantly compared, the register is posted
Deposit and export be measured signal before next working pulse arrives maximum N bit binary numbers value, i.e. register
The peak value of output tracking measured signal exports low level when the zero passage voltage comparator exports low level with gate output terminal,
The register is kept the data of deposit constant by the low level control with door output, i.e. the voltage peak of the numeral output
Detection circuit only tracks the measured signal more than or equal to zero, and the gain of the voltage follower is 1, for measured signal
Isolation.
The beneficial effects of the invention are as follows：The circuit is using voltage follower, zero passage voltage comparator, A/D converter, deposit
One output of device, binary numeral comparator and three inputs realizes that the voltage peak of numeral output detects with circuits such as doors, avoids
Peak value first is obtained with the voltage peak detection circuit of simulation in traditional scheme, then the voltage peak of simulation converted by A/D
Circuit obtains numeral output.Compared with prior art, the circuit is simple and reliable, is suitble to low-and high-frequency measured signal voltage peak to number
The conversion of word, fast response time, measures conversion precision is high, and peak detection voltage dynamic range is big, and minimum can survey μ V magnitudes
Voltage, number is facultative, and to be suitable for the main logics circuit such as TTL, COMS, dynamic power loss by force small.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described.Obviously, described attached drawing is a part of the embodiment of the present invention, rather than is all implemented
Example, those skilled in the art without creative efforts, can also be obtained according to these attached drawings other designs
Scheme and attached drawing.
Fig. 1 is the circuit diagram of voltage peak detection circuit of the present invention.
Specific implementation mode
The technique effect of the design of the present invention, concrete structure and generation is carried out below with reference to embodiment and attached drawing clear
Chu is fully described by, to be completely understood by the purpose of the present invention, feature and effect.Obviously, described embodiment is this hair
Bright a part of the embodiment, rather than whole embodiments, based on the embodiment of the present invention, those skilled in the art are not being paid
The other embodiment obtained under the premise of creative work, belongs to the scope of protection of the invention.In addition, be previously mentioned in text
All connection relations, not single finger element directly connects, and referring to can be according to specific implementation situation, by adding or reducing connection
Element, to form more preferably circuit structure.Each technical characteristic in the invention, under the premise of not conflicting conflict
It can be with combination of interactions.
Embodiment 1, with reference to figure 1, a kind of voltage peak detection circuit of numeral output, including：Operational amplifier A1It constitutes
Voltage follower, A/D converter, register, zero passage voltage comparator a2, the binary numeral being made of voltage comparator A2
Comparator, three inputs, one output with door, the in-phase input end of the voltage follower a1 and measured signal UiConnection, the electricity
Press inverting input of the output end with itself of follower a1, the input end of analog signal IN of the A/D converter+, the mistake
The in-phase input end of no-voltage comparator a2, the N bit binary number signal output ends D of the A/D converterOUTAccording to binary system
One N of the N bit binary number input terminal D and the binary numeral comparator of power and position sequence and the register
Binary digit compares input terminal A parallel connections, and the N bit binary number output end Q of the register are high according to binary system power and position
Low sequence input terminal B compared with another N bit binary number of the binary numeral comparator is connected in parallel, system work
Clock is connect with the clock end CLK of the A/D converter and with the first input end X of door, the zero passage voltage comparator a2's
Output end is connect with described with the second input terminal Y of door, and the inverting input of the zero passage voltage comparator a2 is connected to ground, institute
State the output terminals A of binary numeral comparator>B is connect with described with the third input terminal Z of door, the output end W with door with
The control terminal CP connections of the register, the binary numeral comparator is for comparing an A/ when working pulse arrives
D converter digital signal output ends DOUTThe value of the N bit binary numbers of output and the register in a upper working pulse
The size of the value of the N bit binary numbers of deposit, when the zero passage voltage comparator a2 exports high level, when the A/D turns
Parallel operation digital signal output end DOUTWhen the value of output is more than the value of the presently described register deposit, the binary numeral
Comparator output terminal A>B exports high level, and when a working pulse arrives, high level, the deposit are exported with gate output terminal W
The A/D converter digital signal that device is stored in by the high level control with door output when a working pulse arrives exports
Hold DOUTThe N bit binary numbers of output, as the A/D converter digital signal output end DOUTThe value of output is less than or equal to institute
When stating the value of presently described register deposit, the binary numeral comparator output terminal A>B exports low level, with gate output terminal
W exports low level, and the register is kept posting when a upper working pulse by the low level control register exported with door
The data deposited are constant, and the binary numeral comparator is constantly compared under the effect of system work clock, the register
Deposit and export be measured signal before next working pulse arrives maximum N bit binary numbers value OOUT, that is, post
The peak value of the output tracking measured signal of storage.It is defeated with gate output terminal W when the zero passage voltage comparator a2 exports low level
Go out low level, the register is kept the data of deposit constant by the low level control exported with door, i.e. the numeral output
Voltage peak detection circuit only track the measured signal Ui more than or equal to zero, in addition, the gain of voltage follower a1 is 1,
Buffer action is played to measured signal Ui, improves the conversion accuracy of circuit.
The principle of the present invention is further described：Under original state, the voltage peak detection circuit of numeral output is to be
It works under the action of system work clock, when there is no working pulse, i.e., before detection circuit is started to work, is answered by register
Position end R carries out reset control to register, and register deposit at this time is N bit binary numbers 0, since working pulse state is
Low level " 0 ", this signal are added to the input terminal X with door, so being low level " 0 ", this low electricity with gate output terminal W output
Flat " 0 " is added on the control terminal CP of register, and register is locked at this time, and what register kept deposit is N bits
Word 0, the Q outputs of register output end are N bit binary numbers 0.
Under working condition, as measured signal UiWhen=0V, the output end through voltage follower a1 is added to the mould of A/D converter
Quasi- signal input part IN+, since system work clock is connected on the clock end CLK of A/D converter, in system work clock
Under the action of working pulse, the digital signal output end D of A/D converter at this timeOUTParallel output N bit binary numbers 0, this N
Binary digit 0 according to binary system power and position sequence be concurrently output to the N bit binary number input terminal D and two of register into
One N bit binary number of digital comparator processed compares input terminal A, at this time the positions output end Q parallel outputs N two of register into
Another N bit binary number of system number to binary numeral comparator compares input terminal B, due to the original state of register
It is N bit binary numbers 0, that is, the comparison input terminal B for being added to binary numeral comparator is N bit binary numbers 0, it is clear that is added to
The comparison end A of binary numeral comparator holds the data on B identical compared with, the comparison mode bit " A of binary numeral comparator
>B " exports low level " 0 ", exports low level with gate output terminal W, this low level " 0 " warp is added to the control of register with door
Hold on CP, register is locked at this time, and the content of register deposit remains unchanged, the Q outputs of register output end be the positions N two into
System number 0.
Work as Ui>When 0V, the digital signal output end D of A/D converterOUTThe N bit binary numbers for being greater than zero of output,
This N bit binary number according to binary system power and position sequence be concurrently output to register N bit binary number input terminal D and
One N bit binary number of binary numeral comparator compares input terminal A, and be added to binary numeral comparator another
It is N bit binary numbers 0 that N bit binary numbers, which compare input terminal B, it is clear that is input to the comparison input of binary numeral comparator
The data of end A are more than the data for the comparison input terminal B for being input to binary numeral comparator, the comparison of binary numeral comparator
Mode bit " A>B " output high level " 1 ", and Ui>0V, zero passage voltage comparator a2 export high level " 1 ", when the system is operating clock
Working pulse when being high level " 1 ", be high level " 1 " with gate output terminal W output, this high level " 1 " is added to register
On control terminal CP, the digital signal output end D of A/D converterOUTThe data of output are written into register, similarly in working pulse
Under the action of, detection circuit ceaselessly compares the digital signal output end D of A/D converterOUTThe N bit binary numbers of output (add
N bit binary numbers to binary numeral comparator compare input terminal A) positions N binary system with the output end Q output of register
Digital (the N bit binary numbers for being added to binary numeral comparator compare input terminal B), the data for such as comparing input terminal A are more than
Compare the data of input terminal B, then the digital signal output end D of A/D converterOUTThe data of output replace register legacy data,
The data for such as comparing input terminal A are less than the data for comparing input terminal B, then register legacy data remains unchanged, i.e., register is defeated
The N bit binary numbers of outlet Q outputs are exactly measured signal U before subsequent work pulse arrivesiNumeral output peak signal
OOUT。
The circuit has certain anti-interference ability, works as Ui<When 0V, zero passage voltage comparator a2 output low levels " 0 ", with
Gate output terminal W exports low level, this low level " 0 " warp is added to door on the control terminal CP of register, at this time register quilt
Locked, register registered data is constant, to prevent circuit by negative level signal interference, in addition, the increasing of voltage follower a1
Benefit is 1, to measured signal UiBuffer action is played, the conversion accuracy of circuit is improved.
The selection of A/D converter digit, depending on measurement accuracy requirement, A/D converter digit is higher for this, and voltage peak is surveyed
Amount is higher, can take eight, ten, 12, the A/D converter of sixteen bit here；According to selected A/D converter digit
Determine the digit of register and binary numeral comparator, i.e. A/D converter digit and register and binary numeral comparator
Digit be identical, be N.
The circuit uses operational amplifier A1Voltage follower a1, the voltage comparator A of composition2The zero passage voltage ratio of composition
Realize that number is defeated with circuits such as doors compared with what device a2, A/D converter, register, binary numeral comparator and three inputs one exported
The voltage peak detection gone out avoids in traditional scheme and first obtains peak value with the voltage peak detection circuit of simulation, then will simulation
Voltage peak pass through A/D conversion circuits obtain numeral output.Compared with prior art, circuit is simple and reliable, is suitble to low-and high-frequency
Measured signal voltage peak is to the conversion of number, and fast response time, measures conversion precision is high, and peak detection voltage dynamic model
Big, the minimum voltage that can survey μ V magnitudes is enclosed, number is facultative to be suitable for by force the main logics circuits such as TTL, COMS, dynamic power loss
It is small.
The better embodiment of the present invention is illustrated above, but the invention is not limited to the implementation
Example, those skilled in the art can also make various equivalent modifications or be replaced under the premise of without prejudice to spirit of that invention
It changes, these equivalent modifications or replacement are all contained in the application claim limited range.
Claims (1)
1. a kind of voltage peak detection circuit of numeral output, which is characterized in that including：Voltage follower, is posted A/D converter
Storage, zero passage voltage comparator, binary numeral comparator, three input one output with door, the same phase of the voltage follower
Input terminal is connect with measured signal, the output end of the voltage follower and itself inverting input, the A/D converter
The in-phase input end connection of input end of analog signal, the zero passage voltage comparator, the N bits of the A/D converter
N bit binary number input terminal and the binary system of the word signal output end according to binary system power and position sequence with the register
One N bit binary number of digital comparator compares input terminal parallel connection, the N bit binary numbers output of the register
According to binary system power and position sequence, input terminal is simultaneously compared with another N bit binary number of the binary numeral comparator at end
Row connection, system work clock are connect with the clock end of the A/D converter and with the first input end of door, the zero passage voltage
The output end of comparator is connect with described with the second input terminal of door, and inverting input and the ground of the zero passage voltage comparator connect
Connect, the output end of the binary numeral comparator is connect with described with the third input terminal of door, the output end with door with
The control terminal of the register connects, and the binary numeral comparator is for comparing an A/D when working pulse arrives
The value of the N bit binary numbers of converter digital signal output end output and the register deposit in a upper working pulse
N bit binary numbers value size, when the zero passage voltage comparator export high level when, when the A/D converter number
When the value of word signal output end output is more than the value of the presently described register deposit, the binary numeral comparator output
Output high level in end exports high level, the register is by described defeated with door when a working pulse arrives with gate output terminal
The high level control gone out is stored in the positions N two of an A/D converter digital signal output end output when working pulse arrives
Binary digits, when the value of A/D converter digital signal output end output is posted less than or equal to the presently described register
When the value deposited, the binary numeral comparator output terminal exports low level, and low level, the register are exported with gate output terminal
Kept the data deposited when a upper working pulse constant by the low level control with door output, the binary numeral ratio
It is constantly compared under the effect of system work clock compared with device, the register is deposited and what is exported is that next working pulse arrives
The value of the maximum N bit binary numbers of measured signal before coming, the i.e. peak value of the output tracking measured signal of register, when described
When zero passage voltage comparator exports low level, low level is exported with gate output terminal, the register is by described low with door output
Level control keeps the data of deposit constant, i.e., the voltage peak detection circuit of the numeral output is only tracked more than or equal to zero
The gain of measured signal, the voltage follower is 1, for the isolation to measured signal.
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Cited By (2)
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| CN114584113A (en) * | 2022-04-15 | 2022-06-03 | 苏州大学 | Inverse integral peak detection system, method and apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113608111A (en) * | 2021-06-10 | 2021-11-05 | 苏州瀚宸科技有限公司 | System for accurately detecting input signal amplitude |
| CN113608111B (en) * | 2021-06-10 | 2022-05-03 | 苏州瀚宸科技有限公司 | System for accurately detecting input signal amplitude |
| CN114584113A (en) * | 2022-04-15 | 2022-06-03 | 苏州大学 | Inverse integral peak detection system, method and apparatus |
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