CN108389555A - Driving circuit and display device - Google Patents
Driving circuit and display device Download PDFInfo
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- CN108389555A CN108389555A CN201810118119.7A CN201810118119A CN108389555A CN 108389555 A CN108389555 A CN 108389555A CN 201810118119 A CN201810118119 A CN 201810118119A CN 108389555 A CN108389555 A CN 108389555A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
This application discloses a kind of driving circuit, driving circuit includes：First group of drive element of the grid and second group of drive element of the grid；Sequential control circuit, for generating clock signal and control signal；Level shift circuit, the voltage range for adjusting clock signal with controlling signal, which is characterized in that level shift circuit is connected with sequential control circuit further includes with signal, driving circuit is controlled with the clock signal for receiving sequential control circuit generation：Switching circuit, switching circuit is connected with level shift circuit to receive the clock signal after adjusting voltage range and control signal, switching circuit is connected with first group of gate driving circuit and second group of gate driving circuit respectively, switching circuit is used to alternately provide clock signal to first group of drive element of the grid and second group of drive element of the grid according to control signal so that first group of drive element of the grid or second group of drive element of the grid generate gate drive signal according to clock signal.
Description
Technical field
The present invention relates to display technology fields, more particularly, to a kind of driving circuit and display device.
Background technology
Liquid crystal display device generally comprises liquid crystal display panel and backlight module, and display panel includes the array being oppositely arranged
Substrate and colored filter substrate are provided with the pel array for including multiple pixel units, each picture in array substrate therein
Plain unit is limited and is formed by grid line and data line intersection.A thin film transistor (TFT) is set in each pixel unit, is located at same
The grid of thin film transistor (TFT) in capable pixel unit is connected by same grid line with gate driving circuit, gate driving electricity
Road selects each row pixel unit in pel array by a plurality of grid line line by line；Film in the pixel unit of same row
The source electrode of transistor or drain electrode are connected by same data line with source electrode drive circuit, and source electrode drive circuit passes through a plurality of data
Line applies gray scale voltage to each row pixel unit, to make display panel that image be presented.In the prior art, display device passes through
Horizontal-interlace technique makes the odd-numbered line of grid line staggeredly be charged with even number line to achieve the purpose that realize saving panel power consumption.
Fig. 1 shows interlacing scan circuit diagram in the prior art.As shown in Figure 1, the circuit includes sequence circuit 10, delays
Rush circuit 20, the first level shift circuit 31, second electrical level shift circuit 32, first grid driving circuit 41 and second grid
Driving circuit 42.Sequence circuit 10 for generating control signal, clock signal and enabling signal respectively, and by these three signals
Two-way is divided to be input in buffer circuits 20, buffer circuit 20 controls signal, clock signal and startup letter for temporarily storing
Number, the first level shift circuit 31 expands three kinds of signals for receiving first via control signal, clock signal and enabling signal
Voltage range, and is generated respectively according to control signal, clock signal and enabling signal control signal L, clock signal L with
And enabling signal L；Second electrical level shift circuit 32 expands for receiving the second tunnel control signal, clock signal and enabling signal
The voltage range of three kinds of signals, and is generated respectively according to control signal, clock signal and enabling signal control signal R,
Clock signal R and enabling signal R；First grid driving circuit 41 and second grid driving circuit 42 receive control signal respectively
L, clock signal L, enabling signal L and control signal R, clock signal R and enabling signal R and corresponding gate driving letter is generated
Number, gate drive signal is alternately exported to reach the conducting and shutdown of control parity rows grid line.Due to additionally increasing buffering
Circuit 20 and level shift circuit occupy printed circuit plate suqare, while also increasing design cost.
Invention content
In view of this, the present invention for the above problem in the presence of the prior art provide a kind of liquid crystal display panel and
Liquid crystal display device.
According to an aspect of the present invention, a kind of driving circuit is provided, including：First group of drive element of the grid and second group
Drive element of the grid；Sequential control circuit, for generating clock signal and control signal；Level shift circuit, for adjusting
State the voltage range of clock signal and the control signal, which is characterized in that the level shift circuit and the timing control
Circuit is connected further includes with signal, the driving circuit is controlled to receive the clock signal that the sequential control circuit generates：It cuts
Change circuit, the switching circuit be connected with the level shift circuit with receive the clock signal after adjusting voltage range with
The control signal, the switching circuit respectively with first group of gate driving circuit and second group of gate driving circuit
It is connected, the switching circuit is used for according to the control signal alternately to first group of drive element of the grid and described second
Group drive element of the grid provides the clock signal so that first group of drive element of the grid or second group of gate driving
Unit generates gate drive signal according to the clock signal.
Preferably, the control signal includes alternately effective first control signal and second control signal, when described the
When one control signal is effective, the clock signal is provided to first group of drive element of the grid by the switching circuit, works as institute
State second control signal it is effective when, the clock signal is provided to second group of drive element of the grid by the switching circuit.
Preferably, the switching circuit includes：First handover module, first handover module and first group of grid
Driving unit is connected, and when the first control signal is effective, the first handover module conducting is to put forward the clock signal
It is supplied to first group of drive element of the grid；Second handover module, second handover module and second group of gate driving
Unit is connected, and when the second control signal is effective, the second handover module conducting is the clock signal to be provided to
Second group of drive element of the grid.
Preferably, first handover module includes multiple the first transistors and first resistor, the multiple first crystal
The control terminal of pipe is connected with the first end of the first resistor, the second end of the first resistor and the level shift circuit phase
Even, the control terminal of the multiple the first transistor receives the first control signal by the first resistor, and the multiple the
First path terminal of one transistor is connected with the level shift circuit, the first path terminal difference of the multiple the first transistor
Receive the corresponding clock signal, the alternate path end of the multiple the first transistor and first group of drive element of the grid
It is connected, to provide the clock signal to first group of drive element of the grid.
Preferably, first handover module further includes second transistor and third transistor, second, third described crystal
The control terminal of pipe is connected with the first end of the first resistor, and the control terminal of second, third transistor passes through described first
Resistance receives the first control signal, the first path terminal of the second transistor and the third transistor respectively with it is described
Level shift circuit is connected, and the first path terminal of the second transistor and the third transistor receives first control respectively
The alternate path end of signal processed and the second control signal, the second transistor and the third transistor and described first
Group drive element of the grid is connected, to provide the first control signal and second control to first group of drive element of the grid
Signal processed.
Preferably, second handover module includes multiple 4th transistors and second resistance, the multiple 4th crystal
The control terminal of pipe is connected with the first end of the second resistance, the second end of the second resistance and the level shift circuit phase
Even, the control terminal of the multiple 4th transistor receives the second control signal by the second resistance, and the multiple the
First path terminal of four transistors is connected with the level shift circuit respectively, the first path terminal of the multiple 4th transistor
Receive the corresponding clock signal, the alternate path end of the multiple 4th transistor and second group of drive element of the grid
It is connected, to provide the clock signal to second group of drive element of the grid.
Preferably, second handover module further includes the 5th transistor and the 6th transistor, the five, the 6th crystal
The control terminal of pipe is connected with the first end of the second resistance, and the control terminal of the five, the 6th transistor passes through described second
Resistance receives the second control signal, the first path terminal of the 5th transistor and the 6th transistor respectively with it is described
Level shift circuit is connected, and the first path terminal of the 5th transistor and the 6th transistor receives first control respectively
Signal processed and the second control signal, the alternate path end and described second of the 5th transistor and the 6th transistor
Group drive element of the grid is connected, to provide the first control signal and second control to second group of drive element of the grid
Signal processed.
Preferably, first group of drive element of the grid forms bilateral with second group of drive element of the grid and integrates grid
Driving structure.
Preferably, the transistor in the switching circuit is N-channel thin film transistor (TFT).
According to another aspect of the present invention, a kind of display device is provided, including：Display panel, the display panel packet
Include be set to its non-display area such as above-mentioned driving circuit.
The embodiment of the present invention is directly inputted with clock signal to electricity by the control signal for generating sequential control circuit
Translational shifting circuit, by level shift circuit adjust control signal and clock signal voltage range, and will control signal and when
Clock signal alternately is input in first group of drive element of the grid and second group of drive element of the grid, to reduce buffer circuit with
Level shift circuit, achieved the purpose that save printed circuit board area, and then reached reduce design, production cost mesh
's.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below simple be situated between will be made to the attached drawing of embodiment
It continues, it should be apparent that, the attached drawing in description below only relates to some embodiments of the present invention rather than limitation of the present invention.
Fig. 1 shows interlacing scan circuit diagram in the prior art.
Fig. 2 shows the structural schematic diagrams of the display device of the embodiment of the present invention.
Fig. 3 shows the partial circuit schematic diagram in the display panel of the embodiment of the present invention.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
Attached drawing, clear, complete description is carried out to the technical solution of the embodiment of the present invention.Obvious described embodiment is the present invention
A part of the embodiment, instead of all the embodiments.Based on described the embodiment of the present invention, ordinary skill people
The every other embodiment that member is obtained under the premise of without creative work, shall fall within the protection scope of the present invention.
Fig. 2 shows the structural schematic diagrams of the display device of the embodiment of the present invention.
As shown in Fig. 2, the display device of the embodiment of the present invention includes：Display panel with for display panel provide backlight
And the backlight module (not shown) that is oppositely arranged with display panel.Display panel includes：Driving circuit with for receive it is multiple
To carry out the display area (pel array) 1600 that picture is shown, driving circuit includes gate drive signal：Sequential control circuit
1100, source electrode drive circuit 1200, level shift circuit 1300, switching circuit 1400 and gate driving circuit, wherein grid
Driving circuit includes first group of drive element of the grid 1510 and second group of drive element of the grid 1520, display area 1600 include：
Multiple pixel units 1610, a plurality of grid line 1620 and multiple data lines 1630, each pixel unit 1610 include a crystalline substance
Body pipe 1611 and a pixel electrode 1612.
Multiple pixel units 1610 are arranged in array, the grid of the transistor 1611 in each pixel unit 1610 with it is corresponding
Grid line 1620 be connected, source electrode and corresponding data line 1630 are connected, and drain electrode and the pixel in respective pixel unit 1610 are electric
Pole 1612 is connected.First group of drive element of the grid 1510 and second group of drive element of the grid 1520 are respectively connected to corresponding grid
Line 1620, source electrode drive circuit 1200 are connected to multiple data lines 1630, and sequential control circuit 1100 is electric with source drive respectively
Road 1200, level shift circuit 1300 be connected, switching circuit 1400 respectively with 1300, first groups of gate drivings of level shift circuit
Unit 1510 and second group of drive element of the grid 1520 are connected.
Sequential control circuit 1100 is used to provide clock signal, to level shift circuit 1300 to source electrode drive circuit 1200
Clock signal and control signal are provided, clock signal includes multiple clock signals and multiple enabling signal (Start
Vertical, STV), wherein enabling signal can be the open signal of a frame, and control signal includes alternately effective first control
Signal processed and second control signal.Source electrode drive circuit 1200 in pixel unit 1610 transistor 1611 be connected when
Apply gray scale voltage corresponding with display data on corresponding pixel electrode 1612.Level shift circuit 1300 is controlled for adjusting
The voltage range of signal processed and clock signal.Switching circuit 1400 is used for according to control signal alternately to first group of gate driving
Unit 1510 and second group of drive element of the grid 1520 provide clock signal so that first group of drive element of the grid 1510 or the second
Group drive element of the grid 1520 provides corresponding gate drive signal according to clock signal to corresponding grid line 1620, wherein
Gate drive signal is for scanning grid line, and first control signal and second control signal are alternately effectively so that the group of grid drives
Moving cell 1510 and the group of two drive element of the grid 1520 work alternatively, to realize interlacing scan, for example, first group of gate driving
Unit 1510 and second group of drive element of the grid 1520 are respectively used to by every grid line of odd number and the sequential scan of even number line
1620 so that the transistor 1611 of corresponding line is connected.In the present embodiment, group of drive element of the grid 1510 and group of two grid
The opposite left and right sides that pole driving unit 1520 is located at display panel display area 1600 forms the integrated grid drive of bilateral
Dynamic structure.Apply example some other, gate driving circuit can with sequential control circuit 1100, source electrode drive circuit 1200 with
And level shift circuit 1300 etc. is integrated on same circuit board.In some preferred embodiments, switching circuit 1400 can be put
It sets in display panel in unappropriated space (such as near detection unit cell test of some display panels), with
Avoid increasing the volume of display panel.
Fig. 3 shows the partial circuit schematic diagram in the display panel of the embodiment of the present invention.It should be noted that in this implementation
The transistor that refers to is N-type TFT in example, and control terminal is the grid of thin film transistor (TFT), and the first of each transistor
Path terminal and alternate path end can be interchanged (i.e. drain electrode and source electrode can be interchanged).But the present invention be practiced without limitation to this.
As shown in figure 3, sequential control circuit 1100 provides two path control signal, four road clocks to level shift circuit 1300
Signal and two-way enabling signal, wherein two path control signal includes：First control signal V1, second control signal V2, four tunnels
Clock signal includes：First clock signal clk 1, second clock signal CLK2, third clock signal clk 3, the 4th clock signal
CLK4, two-way enabling signal include：First enabling signal STV1, the second enabling signal STV2.Level shift circuit 1300 receives
First control signal V1, second control signal V2, the first clock signal clk 1, second clock signal CLK2, third clock signal
CLK3, the 4th clock signal clk 4, the first enabling signal STV1 and the second enabling signal STV2 are used for the electricity of above-mentioned signal
Pressure range is adjusted, including the voltage range for expanding signal, to reach the demand of gate driving circuit.
Switching circuit 1400 includes the first handover module 1410 and the second handover module 1420, wherein the first handover module
1410 include：Resistance R1 and transistor T1, T3, T5, T7, T9, T11, T13, T15.The first end of resistance R1 receives the first control
The grid of signal V1 processed, transistor T1, T3, T5, T7, T9, T11, T13, T15 are connected with the second end of resistance R1 to receive first
Signal V1 is controlled, the source electrode of transistor T1 is connected with level shift circuit 1300 to receive first control signal V1, transistor T3
Source electrode be connected with level shift circuit 1300 to receive second control signal V2, source electrode and the electricity of transistor T5, T7, T9, T11
Translational shifting circuit 1300 is connected to receive the first clock signal clk 1, second clock signal CLK2, third clock signal respectively
The source electrode of CLK3, the 4th clock signal clk 4, transistor T13, T15 is connected with level shift circuit 1300 to receive first respectively
Enabling signal STV1 and the second enabling signal STV2, the drain electrode of transistor T1 are connected with first group of drive element of the grid 1510 to carry
For first control signal V1, the drain electrode of transistor T3 is connected with first group of drive element of the grid 1510 to provide second control signal
V2, the drain electrode of transistor T5, T7, T9, T11 are connected with first group of drive element of the grid 1510 to provide the first clock signal respectively
CLK1, second clock signal CLK2, third clock signal clk 3, the 4th clock signal clk 4, the drain electrode of transistor T13, T15 with
First group of drive element of the grid 1510 is connected to provide the first enabling signal STV1 and the second enabling signal STV2 respectively, and first cuts
Mold changing block 1410 is used to that clock signal to be provided to first grid driving unit in conducting, and if only if first control signal V1
When effective, the conducting of the first handover module 1410.Second handover module 1420 includes：Resistance R2 and transistor T2, T4, T6, T8,
T10、T12、T14、T16.The first end of resistance R2 receives first control signal V1, transistor T2, T4, T6, T8, T10, T12,
The grid of T14, T16 are connected with the second end of resistance R2 to receive second control signal V2, and source electrode and the level of transistor T2 move
Position circuit 1300 is connected to receive first control signal V1, and being connected with level shift circuit 1300 for transistor T4 is received with source electrode
The source electrode of second control signal V2, transistor T6, T8, T10, T12 are connected with level shift circuit 1300 to receive first respectively
Clock signal clk 1, second clock signal CLK2, third clock signal clk 3, the 4th clock signal clk 4, transistor T14, T16
Source electrode be connected with level shift circuit 1300 to receive the first enabling signal STV1 and the second enabling signal STV2, crystal respectively
The drain electrode of pipe T2 is connected with second group of drive element of the grid 1520 to provide first control signal V1, the drain electrode of transistor T4 and the
Two groups of drive element of the grid 1520 are connected to provide second control signal V2, the drain electrode of transistor T6, T8, T10, T12 and second
Group drive element of the grid 1520 is connected to be believed with providing the first clock signal clk 1, second clock signal CLK2, third clock respectively
Number CLK3, the 4th clock signal clk 4, the drain electrode of transistor T14, T16 are connected with second group of drive element of the grid 1520 to distinguish
The first enabling signal STV1 and the second enabling signal STV2 are provided, the second handover module 1420 is used for clock signal in conducting
It is provided to second grid driving unit, when second control signal V2 is effective, the conducting of the second handover module, for example, the
One handover module 1410 is with the second handover module 1420 by being controlled respectively according to first control signal V1 and second control signal V2
The corresponding first group of drive element of the grid 1510 in 1600 left and right ends of display area processed and second group of drive element of the grid 1520.
First group of drive element of the grid 1510 is according to first control signal V1, second control signal V2, the first clock signal clk 1, second
Clock signal clk 2, third clock signal clk 3, the 4th clock signal clk 4, the first enabling signal STV1 and second start letter
Number STV2 exports gate drive signal, and second group of drive element of the grid 1520 is according to first control signal V1, second control signal
V2, the first clock signal clk 1, second clock signal CLK2, third clock signal clk 3, the 4th clock signal clk 4, first are opened
Dynamic signal STV1 and the second enabling signal STV2 export gate drive signal, wherein when first control signal V1 is effective, the
One group of drive element of the grid 1510 exports odd-numbered line gate drive signal, and when second control signal V2 is effective, second group of grid drives
Moving cell 1520 exports even number line gate drive signal, effective by making first control signal V1 and second control signal V2 replace
Method, it is ensured that first group of drive element of the grid 1510 and second group of drive element of the grid 1520 have always is in high resistant on one side
State, to reach 1600 interleaved purpose of display panel.
In the switching circuit 1400 of the embodiment of the present invention, high level signal is useful signal, can also utilize inverse
Useful signal is defined as low level signal, transistor T5, T7, T9, T11,13,15 can be named as the first transistor, transistor
T1 can be named as second transistor transistor, and transistor T3 can be named as third transistor, and transistor T6, T8, T10, T12 can be ordered
Entitled 4th transistor, transistor T2 can be named as the 5th transistor, and transistor T4 can be named as the 6th transistor, brilliant
The number of body pipe can be configured as needed, and the embodiment of the present invention is only illustrated with 16 transistors, however this hair
The parameter setting of bright embodiment is without being limited thereto, and those skilled in the art can carry out related setting according to actual needs.
The display device of the embodiment of the present invention is liquid crystal display device, and display panel is liquid crystal display panel, however this hair
Bright embodiment is without being limited thereto, and those skilled in the art can as needed carry out other kinds of display panel and display device
Correlation setting.Meanwhile the driving circuit in the embodiment of the present invention is set to the non-display area of liquid crystal display panel.
After the embodiment of the present invention by switching circuit by being placed in level shift circuit, sequence circuit and level are simplified
Circuit structure between shift circuit.
The embodiment of the present invention with switching circuit by, instead of the signal branch between sequence circuit and buffer circuit, being made
Control signal directly controls the break-make of transistor in switching circuit to control to odd-numbered line grid line or the progress of even number line grid line
Scanning, keeps interleaved process easier.
The embodiment of the present invention is directly inputted with clock signal to electricity by the control signal for generating sequential control circuit
Translational shifting circuit, by level shift circuit adjust control signal and clock signal voltage range, and will control signal and when
Clock signal alternately is input in first group of drive element of the grid and second group of drive element of the grid, to reduce buffer circuit with
Level shift circuit, achieved the purpose that save printed circuit board area, and then reached reduce design, production cost mesh
's.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
As described above according to the embodiment of the present invention, there is no all details of detailed descriptionthe for these embodiments, also not
Limit the specific embodiment that the invention is only described.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is in order to preferably explain the principle of the present invention and practical application, belonging to making
Technical field technical staff can utilize modification of the invention and on the basis of the present invention to use well.
Claims (10)
1. a kind of driving circuit, the driving circuit include：First group of drive element of the grid and second group of drive element of the grid；When
Sequence control circuit, for generating clock signal and control signal；Level shift circuit, for adjust the clock signal with it is described
Control the voltage range of signal, which is characterized in that the level shift circuit is connected with the sequential control circuit to receive
The clock signal and control signal of sequential control circuit generation are stated,
The driving circuit further includes：
Switching circuit, the switching circuit are connected with the level shift circuit to receive the clock after adjusting voltage range
Signal and the control signal,
The switching circuit is connected with first group of gate driving circuit and second group of gate driving circuit respectively,
The switching circuit is used for according to the control signal alternately to first group of drive element of the grid and described second
Group drive element of the grid provides the clock signal so that first group of drive element of the grid or second group of gate driving
Unit generates gate drive signal according to the clock signal.
2. driving circuit according to claim 1, which is characterized in that the control signal includes alternately effective first control
Signal processed and second control signal,
When the first control signal is effective, the clock signal is provided to first group of grid and driven by the switching circuit
Moving cell,
When the second control signal is effective, the clock signal is provided to second group of grid and driven by the switching circuit
Moving cell.
3. driving circuit according to claim 2, which is characterized in that the switching circuit includes：
First handover module, first handover module are connected with first group of drive element of the grid, when first control
When signal is effective, the first handover module conducting by the clock signal to be provided to first group of drive element of the grid；
Second handover module, second handover module are connected with second group of drive element of the grid, when second control
When signal is effective, the second handover module conducting by the clock signal to be provided to second group of drive element of the grid.
4. driving circuit according to claim 3, which is characterized in that first handover module includes multiple first crystals
Pipe and first resistor, the control terminal of the multiple the first transistor are connected with the first end of the first resistor, first electricity
The second end of resistance is connected with the level shift circuit, and the control terminal of the multiple the first transistor is connect by the first resistor
The first control signal is received, the first path terminal of the multiple the first transistor is connected with the level shift circuit, described
First path terminal of multiple the first transistors receives the corresponding clock signal respectively, and the second of the multiple the first transistor
Path terminal is connected with first group of drive element of the grid, is believed with providing the clock to first group of drive element of the grid
Number.
5. driving circuit according to claim 4, which is characterized in that first handover module further includes second transistor
And third transistor, the control terminal of second, third transistor are connected with the first end of the first resistor, described second,
The control terminal of third transistor receives the first control signal by the first resistor, the second transistor and described the
First path terminal of three transistors is connected with the level shift circuit respectively, the second transistor and the third transistor
The first path terminal receive the first control signal and the second control signal, the second transistor and described respectively
The alternate path end of three transistors is connected with first group of drive element of the grid, to be carried to first group of drive element of the grid
For the first control signal and the second control signal.
6. driving circuit according to claim 3, which is characterized in that second handover module includes multiple 4th crystal
Pipe and second resistance, the control terminal of the multiple 4th transistor are connected with the first end of the second resistance, second electricity
The second end of resistance is connected with the level shift circuit, and the control terminal of the multiple 4th transistor is connect by the second resistance
The second control signal is received, the first path terminal of the multiple 4th transistor is connected with the level shift circuit respectively,
The corresponding clock signal of the first path terminal reception of the multiple 4th transistor, the second of the multiple 4th transistor
Path terminal is connected with second group of drive element of the grid, is believed with providing the clock to second group of drive element of the grid
Number.
7. driving circuit according to claim 6, which is characterized in that second handover module further includes the 5th transistor
It is connected with the first end of the second resistance with the control terminal of the 6th transistor, the five, the 6th transistor, the described 5th,
The control terminal of 6th transistor receives the second control signal by the second resistance, the 5th transistor and described the
First path terminal of six transistors is connected with the level shift circuit respectively, the 5th transistor and the 6th transistor
The first path terminal receive the first control signal and the second control signal, the 5th transistor and described respectively
The alternate path end of six transistors is connected with second group of drive element of the grid, to be carried to second group of drive element of the grid
For the first control signal and the second control signal.
8. according to claim 1-7 any one of them driving circuits, which is characterized in that first group of drive element of the grid with
Second group of drive element of the grid forms bilateral and integrates gate drive configuration.
9. according to claim 4-7 any one of them driving circuits, which is characterized in that the transistor in the switching circuit is
N-channel thin film transistor (TFT).
10. a kind of display device, which is characterized in that including：
Display panel, the display panel include the driving circuit as described in claim 1-9 for being set to its non-display area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810118119.7A CN108389555B (en) | 2018-02-06 | 2018-02-06 | Drive circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810118119.7A CN108389555B (en) | 2018-02-06 | 2018-02-06 | Drive circuit and display device |
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| CN108389555A true CN108389555A (en) | 2018-08-10 |
| CN108389555B CN108389555B (en) | 2020-09-04 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN110136667A (en) * | 2019-05-06 | 2019-08-16 | 晶晨半导体(上海)股份有限公司 | A kind of driving circuit |
| CN110136667B (en) * | 2019-05-06 | 2021-06-04 | 晶晨半导体(上海)股份有限公司 | Driving circuit |
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| CN110619857A (en) * | 2019-08-27 | 2019-12-27 | 昆山龙腾光电股份有限公司 | Driving circuit and display device |
| CN110619857B (en) * | 2019-08-27 | 2021-10-29 | 昆山龙腾光电股份有限公司 | Driving circuit and display device |
| WO2022199189A1 (en) * | 2021-03-22 | 2022-09-29 | 重庆惠科金渝光电科技有限公司 | Gate drive module, method for generating gate control signal, and display apparatus |
| CN113066421A (en) * | 2021-03-31 | 2021-07-02 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN113299722A (en) * | 2021-05-31 | 2021-08-24 | 福州京东方显示技术有限公司 | Display panel |
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