CN108363894B - Circuit-level single event effect simulation platform - Google Patents
Circuit-level single event effect simulation platform Download PDFInfo
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Abstract
The invention provides a circuit-level single event effect simulation platform which can support a large-scale circuit with more than ten thousand gate levels to carry out single event effect simulation analysis. The circuit-level single event effect simulation platform comprises a circuit analysis module, a fault injection configuration module, an analysis mode module, a netlist processing module and a result analysis module, wherein the circuit analysis module extracts all sensitive nodes in a circuit and generates a circuit node list file; the fault injection configuration module combines the circuit node list file and the relevant parameters of the fault current source of the circuit to be injected input by a user, compiles a script to randomly select the circuit node and the fault injection time, and generates a fault injection file; compiling a script by the netlist processing module to obtain a result detection file, and generating an excitation file by combining an analysis mode and a fault injection file to be provided to a Fast-Spice simulator; and the result analysis module stores and extracts the simulation result and forms different result icons according to different analysis modes.
Description
Technical Field
The invention belongs to the field of space radiation effect, relates to a single event effect simulation platform, and is particularly suitable for relevant researchers to carry out single event effect simulation analysis on large-scale circuits above ten thousand gate levels.
Background
With the further development of aerospace industry and nuclear energy technology, electronic components with high reliability and high performance are urgently needed in both national defense modernization and national economic construction. The Single Event Effect (SEE) is a radiation effect in which a single energetic particle in the universe enters a sensitive region of a semiconductor device to flip the logic state of the device. This can lead to system dysfunction and, in severe cases, catastrophic failure. With the improvement of the process technology and the reduction of the transistor size, the single event effect becomes an important factor influencing the reliability problem related to the single event effect and also becomes one of the leading factors of the total soft error rate
In a single-particle experiment, the specific positions of particle injection cannot be determined, and the particles cannot be positioned, so that the circuit is in error; and the domestic experimental places capable of carrying out the single event effect are very limited and the cost is high.
Compared with the experiment, the simulation analysis can accurately position the high-energy particles which cause the circuit to generate errors, and has the advantages of high speed, low cost and the like; for example:
chinese patent document CN103577643A discloses a simulation method for single event upset effect of SRAM type FPGA. The method adopts a device-level simulation tool, the simulation speed is limited, and the circuit scale is very small.
Chinese patent document CN106997402A discloses a single event effect multi-bit flip circuit simulation method, which mainly adopts a scheme of injecting a transient pulse model into two nodes in a circuit.
At present, no simulation platform capable of injecting a plurality of fault current sources simultaneously for a large-scale circuit exists.
Disclosure of Invention
The invention provides a circuit-level single event effect simulation platform which can support a large-scale circuit with more than ten thousand gate levels to carry out single event effect simulation analysis.
The solution of this aspect is as follows:
the circuit level single event effect simulation platform comprises
The circuit analysis module is used for a user to select the type of the analyzed circuit and extract all sensitive nodes in the circuit according to the circuit netlist file provided by the user to generate a circuit node list file;
the fault injection configuration module is used for providing a fault current source template file, combining a circuit node list file and relevant parameters of a fault current source of a circuit to be injected by user input, compiling a script to randomly select a circuit node and fault injection time, and generating a fault injection file;
the analysis mode module is used for the user to select an analysis mode according to the requirement;
the netlist processing module is used for determining a result detection template file according to the analysis mode, correspondingly compiling a script to obtain a result detection file, and then generating an excitation file by combining the analysis mode and the fault injection file;
the Fast-Spice simulator takes the excitation file output by the netlist processing module as input for simulation;
and the result analysis module is used for storing and extracting the simulation result of the Fast-Spice simulator and forming different result icons according to different analysis modes.
Based on the above scheme, the invention further optimizes as follows:
the circuit analysis module specifically utilizes Hercules software to analyze and obtain the total area of the sensitive node region in the layout and the proportion of the sensitive node region in the whole layout.
The types of circuit analyzed as described above include SRAM circuits, CPU circuits, and the like.
The related parameters of the fault current source comprise fault injection quantity, an LET value, a current source distribution model, simulation times, simulator types and the like.
The analysis mode module provides three analysis modes: key path analysis, key signal sensitivity analysis and statistical analysis; the method comprises the steps that a critical path analysis is to perform static time sequence analysis on a circuit to obtain a path with the largest combinational logic delay in a synchronous logic circuit, fault current source injection is performed on the path, and the condition that the circuit function is wrong when the critical path is influenced by a single-event transient is analyzed; the key signal sensitivity analysis is to inject current sources corresponding to different LET values into the most sensitive positions of key signals in a scanning analysis mode aiming at the key signals in the circuit, and the LET threshold value of the circuit, which is caused by the key signals, is obtained through analysis; the statistical analysis is to randomly select circuit nodes according to the randomness of the single event effect, randomly select the occurrence time, inject a fault current source with the pulse width being random in a set range, and perform multiple simulation analysis and count the average value of circuit errors.
The fault injection configuration module uses Perl language and C-shell language to compile scripts to randomly select circuit nodes and fault injection time;
the circuit analysis module writes scripts to extract all nodes in the circuit by using Perl language and C-shell language according to the netlist file of the circuit;
the netlist processing module generates random numbers by Perl language, each random number corresponds to one row of the circuit node list file and also corresponds to the randomly selected circuit node of the row; meanwhile, the Perl script randomly generates the fault injection time, and calls a fault current source template file to form a fault injection file; the fault injection file conforms to SPICE grammar and can be directly called by a Fast-SPICE simulator;
the netlist processing module generates different excitation files by using a Perl script;
the Fast-Spice simulator utilizes Perl language and C-shell language to compile scripts according to the simulation times set in the excitation file to realize multiple times of simulation, saves the simulation result and deletes the intermediate file.
The Fast-Spice simulator can adopt Spectre XPS, Finesim and the like.
The different result icons comprise a turning section curve, a soft error rate, a statistical analysis table, a waveform diagram and the like; for calculating the turnover section and the soft error rate, the related parameters comprise the proportion of sensitive nodes in the layout, the number of faults and the total number of injected faults; the proportion of the sensitive nodes in the layout is obtained by the circuit analysis module according to the circuit layout analysis corresponding to the circuit type and is directly provided to the result analysis module.
The sensitive node is determined as the drain electrode of an NMOS tube in the circuit.
The invention has the following technical effects:
the single event effect simulation analysis method can perform single event effect simulation analysis on large-scale circuits above ten thousand gate levels, can inject a fault current source into random circuit nodes at any time, enables the peak value and the pulse width of the fault current source to be random within a certain range, and automatically analyzes a simulation result to replace a single event effect experiment.
The invention can accurately position which injected faults in the large-scale circuit cause the circuit to have errors; the cost is low, and the simulation speed is high; in addition, simulation analysis may perform fault injection for a particular node or signal, thereby analyzing the single particle sensitivity of this signal.
Drawings
FIG. 1 is a schematic diagram of a basic framework of a circuit-level single event effect simulation platform structure according to the present invention.
Fig. 2 is a detailed frame diagram of a circuit-level single event effect simulation platform structure.
FIG. 3 is a block diagram of random fault injection file generation.
FIG. 4 is a netlist processing module script flow diagram.
Detailed Description
Each module of the circuit-level single event effect simulation platform of the present invention is further described in detail below with reference to the accompanying drawings.
As shown in fig. 1 and 2, the circuit-level single-event-effect simulation platform includes a circuit analysis module, a fault injection configuration module, an analysis mode module, a netlist processing module, and a result analysis module.
And the circuit analysis module obtains the proportion of the node list file of the analyzed circuit to the drain region in the layout. Specifically, the method comprises the following steps: and the circuit analysis module extracts all nodes in the circuit by using the Perl script and the C-shell script according to the netlist file of the circuit and stores all the nodes in a circuit node list file. For different circuit forms, such as an SRAM circuit and a CPU circuit, scripts for extracting circuit nodes are different, but circuit node list files are formed, and each row in the circuit node list files corresponds to one circuit node; and meanwhile, analyzing by using Hercules software according to the circuit layout to obtain the proportion of the total area of the drain region in the version to the whole layout.
The fault injection configuration module configures parameters of a fault current source, and specifically: the fault injection configuration module specifies relevant parameters of injected faults, the fault injection quantity represents how many fault current sources are injected in each simulation, the LET value gives the LET value range needing simulation, the simulation times determine how many times of repeated simulation, the more the repeated simulation times are, the more accurate the obtained result is, but the longer the time is. According to the simulator owned by the user, the platform supports different simulators to simulate and process the simulation result.
The analysis mode module selects different analysis modes, and the netlist processing module forms different excitation files according to the different analysis modes. Specifically, the method comprises the following steps: the analysis mode module mainly comprises three analysis modes: (1) the method comprises the steps that firstly, a circuit is subjected to static time sequence analysis, a path with the largest combinational logic delay in a synchronous logic circuit is obtained, random fault current source injection is carried out aiming at the path, and the condition that the circuit function is wrong when the critical path is influenced by a single-event transient state is analyzed; (2) the key signal sensitivity analysis is to inject current sources corresponding to different LET values into the most sensitive positions of key signals in a scanning analysis mode aiming at the key signals in the circuit, and the LET threshold value of the circuit, which is caused by the key signals, is obtained through analysis; the method comprises the steps that a fault current source corresponding to injection time and different LET values is scanned simultaneously in scanning analysis, a simulation result is generated for each pair of injection time and LET value in a scanning range, and a Perl script is used for extracting all results into a file to obtain the injection time most sensitive to a key signal and the minimum LET value causing circuit errors; (3) the statistical analysis is to randomly select circuit nodes at all circuit nodes according to the randomness of the single event effect, randomly select the occurrence time, inject a fault current source with a pulse width random within a certain range, and perform multiple simulation analysis and count the average value of circuit errors.
The netlist processing module generates different excitation files by using a Perl script according to different analysis modes and different circuit types, and simultaneously writes a script by using the Perl language and the C-shell language to randomly select circuit nodes and add fault injection time to the excitation files. Specifically, the method comprises the following steps:
the method for injecting the fault current source into the random circuit node at any time and randomly setting the peak value and the pulse width of the fault current source within a certain range is shown in fig. 3. And generating random numbers by Perl language, wherein each random number corresponds to one row of the circuit node list file and also corresponds to the randomly selected circuit node of the row. Meanwhile, the Perl script randomly generates the fault injection time again, and calls a current source to form a fault current source file. The fault current source file conforms to SPICE grammar and can be directly called by a Fast-SPICE simulator, and random fault current sources can be injected into random circuit nodes at any time.
A flow diagram of the netlist processing module is shown in fig. 4. For the CPU circuit, whether the output instruction output after fault injection is correct or not is analyzed, and all instructions are traversed. For the SRAM circuit, the read-write operation is mainly repeatedly performed at different addresses. Taking the statistical analysis of the SRAM as an example, the platform adopts the read-write excitation of 'all 0 address write 0-all 1 address write 1-all 0 address read 0-all 1 address read 1-all 0 address write 1-all 1 address write 0-all 0 address read 1-all 1 address read 0' to carry out circulation, so that different addresses are ensured to alternately carry out read-write on different numerical values, and the storage node and the output Q are both turned over on the acting device. And meanwhile, generating a corresponding result detection file according to the read-write excitation, wherein the result display file conforms to SPICE grammar and can be directly called by a Fast-SPICE simulator, and directly generating a corresponding result file after the simulation is finished.
The Fast-Spice tool (Spectre XPS/Finesim, etc.) calls the stimulus file for simulation.
And the result analysis module stores and extracts the simulation result of the simulator and forms different analysis results according to different analysis modes. Specifically, the method comprises the following steps: in a result analysis module, a Perl script extracts a simulation result from a result file output by the simulator and compares the simulation result with an expected value, and if the simulation result does not accord with the expected value, the circuit is judged to be in error due to the fault current source. Counting the number of results which are inconsistent with the expectation, and calculating the turnover section, the soft error rate or outputting a statistical result table and a corresponding oscillogram according to a corresponding formula. For calculating the turnover section and the soft error rate, the related parameters include the proportion of sensitive nodes in the layout, the number of faults, the total number of injection faults and the like.
Claims (9)
1. A circuit-level single event effect simulation platform is characterized by comprising:
the circuit analysis module is used for a user to select the type of the analyzed circuit and extract all sensitive nodes in the circuit according to the circuit netlist file provided by the user to generate a circuit node list file;
the fault injection configuration module is used for providing a fault current source template file, combining a circuit node list file and relevant parameters of a fault current source of a circuit to be injected by user input, compiling a script to randomly select a circuit node and fault injection time, and generating a fault injection file;
the analysis mode module is used for the user to select an analysis mode according to the requirement;
the netlist processing module is used for determining a result detection template file according to the analysis mode, correspondingly compiling a script to obtain a result detection file, and then generating an excitation file by combining the analysis mode and the fault injection file;
the Fast-Spice simulator takes the excitation file output by the netlist processing module as input for simulation;
and the result analysis module is used for storing and extracting the simulation result of the Fast-Spice simulator and forming different result icons according to different analysis modes.
2. The circuit-level single event effect simulation platform of claim 1, wherein: the circuit analysis module analyzes the total area of the sensitive node region and the proportion of the sensitive node region to the whole layout by using Hercules software.
3. The circuit-level single event effect simulation platform of claim 1, wherein: the circuit types analyzed include SRAM circuits and CPU circuits.
4. The circuit-level single event effect simulation platform of claim 1, wherein: the related parameters of the fault current source comprise fault injection quantity, an LET value, a current source distribution model, simulation times and simulator types.
5. The circuit-level single event effect simulation platform of claim 1, wherein: the analysis mode module provides three analysis modes: key path analysis, key signal sensitivity analysis and statistical analysis; the method comprises the steps that a critical path analysis is to perform static time sequence analysis on a circuit to obtain a path with the largest combinational logic delay in a synchronous logic circuit, fault current source injection is performed on the path, and the condition that the circuit function is wrong when the critical path is influenced by a single-event transient is analyzed; the key signal sensitivity analysis is to inject current sources corresponding to different LET values into the most sensitive positions of key signals in a scanning analysis mode aiming at the key signals in the circuit, and the LET threshold value of the circuit, which is caused by the key signals, is obtained through analysis; the statistical analysis is to randomly select circuit nodes according to the randomness of the single event effect, randomly select the occurrence time, inject a fault current source with the pulse width being random in a set range, and perform multiple simulation analysis and count the average value of circuit errors.
6. The circuit-level single event effect simulation platform of claim 1, wherein:
the fault injection configuration module writes scripts by using Perl language and C-shell language to randomly select circuit nodes and fault injection time;
the circuit analysis module writes scripts to extract all nodes in the circuit by using Perl language and C-shell language according to the netlist file of the circuit;
the netlist processing module generates random numbers by Perl language, each random number corresponds to one row of the circuit node list file and also corresponds to the randomly selected circuit node of the row; meanwhile, the Perl script randomly generates the fault injection time, and calls a fault current source template file to form a fault injection file; the fault injection file conforms to SPICE grammar and can be directly called by a Fast-SPICE simulator;
the netlist processing module generates different excitation files by using a Perl script;
and the Fast-Spice simulator writes scripts by utilizing Perl language and C-shell language according to the simulation times set in the excitation file to realize multiple times of simulation and stores the simulation result to delete the intermediate file.
7. The circuit-level single event effect simulation platform of claim 1, wherein: the Fast-Spice simulator adopts spectrum XPS or Finesim.
8. The circuit-level single event effect simulation platform of claim 1, wherein: the different result icons comprise a turning section curve, a soft error rate, a statistical analysis table and a oscillogram; for calculating the turnover section and the soft error rate, the related parameters comprise the proportion of sensitive nodes in the layout, the number of faults and the total number of injected faults; the proportion of the sensitive nodes in the layout is obtained by the circuit analysis module according to the circuit layout analysis corresponding to the circuit type and is directly provided to the result analysis module.
9. The circuit-level single event effect simulation platform of claim 1, wherein: the sensitive node is the drain electrode of an NMOS tube in the circuit.
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