CN108347660B - Analog relay access device - Google Patents
Analog relay access device Download PDFInfo
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- CN108347660B CN108347660B CN201711487729.6A CN201711487729A CN108347660B CN 108347660 B CN108347660 B CN 108347660B CN 201711487729 A CN201711487729 A CN 201711487729A CN 108347660 B CN108347660 B CN 108347660B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/26—Devices for calling a subscriber
- H04M1/30—Devices which can set up and transmit only one digit at a time
- H04M1/50—Devices which can set up and transmit only one digit at a time by generating or selecting currents of predetermined frequencies or combinations of frequencies
- H04M1/505—Devices which can set up and transmit only one digit at a time by generating or selecting currents of predetermined frequencies or combinations of frequencies signals generated in digital form
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/0008—Selecting arrangements using relay selectors in the switching stages
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Telephonic Communication Services (AREA)
- Interface Circuits In Exchanges (AREA)
Abstract
The invention discloses an analog relay access device, and belongs to the technical field of telephone communication. The device comprises an analog relay interface voice module, a main control module and a logic processing module, wherein the analog relay interface voice module comprises an analog relay interface circuit unit, a caller identification and dual-tone multi-frequency forwarding unit and a coding and decoding unit, the caller identification and dual-tone multi-frequency forwarding unit is used for decoding dual-tone multi-frequency signals in analog four-wire signals into first digital signals and forwarding frequency shift keying signals in the first digital signals and the analog four-wire signals to the logic processing module, the logic processing module is used for sending the first digital signals and the frequency shift keying signals to the main control module, the main control module is used for determining a called user according to the first digital signals and sending the frequency shift keying signals to the called user, and the called user displays a calling number of the calling user according to the frequency shift keying signals.
Description
Technical Field
The invention relates to the technical field of telephone communication, in particular to an analog relay access device.
Background
In the program control exchange system, a small-sized local side communication exchange system (called local side for short) is realized after the telephone signal of the local side is accessed through an analog telephone interface device. The information interaction between the local side and the user at the local side needs to be completed by simulating the relay access device.
The present analog relay access device is generally used for accessing an analog signal processed by a calling end office, converting the analog signal into a digital signal after a series of processing such as sampling, compression and decompression, encoding and decoding, and then implementing processing and switching of the digital signal through a Pulse Code Modulation (PCM) switching center.
Through the analog relay access device, when a calling subscriber dials for the first time, a called subscriber can know the calling number of the calling subscriber, but when the calling subscriber needs to dial for the second time, the called subscriber cannot display the calling number of the calling subscriber, for example, when a subscriber A needs to dial for the second time, the called subscriber dials to a host B, and inputs a subscriber C needing to be called through keys, the host B cannot display the calling number of the subscriber C input by the subscriber A through the keys.
Disclosure of Invention
In order to solve the problem that an analog relay interface device in the prior art cannot detect and display calling number information, the embodiment of the invention provides an analog relay access device. The technical scheme is as follows:
the invention provides an analog relay access device, which comprises an analog relay interface voice module, a main control module and a logic processing module, wherein the analog relay interface voice module comprises an analog relay interface circuit unit, a caller identification and dual-tone multi-frequency forwarding unit and a coding and decoding unit,
the analog relay interface circuit unit is configured to convert an analog two-wire signal accessed to the analog relay interface voice module into an analog four-wire signal, the caller identification and dual-tone multi-frequency forwarding unit is configured to decode a dual-tone multi-frequency signal in the analog four-wire signal into a first digital signal and forward a frequency shift keying signal in the first digital signal and the analog four-wire signal to the logic processing module, and the logic processing module is configured to send the first digital signal and the frequency shift keying signal to the main control module;
the coding and decoding unit is used for converting the voice signal of the analog four-wire signal output by the analog relay interface circuit unit into a second digital signal and sending the second digital signal to the main control module through the logic processing module;
the main control module is used for determining a called user according to the first digital signal and sending the frequency shift keying signal to the called user, and the called user displays the calling number of the calling user according to the frequency shift keying signal.
Further, the analog relay interface circuit unit comprises a protection circuit, a power taking and balancing circuit, an 2/4 line conversion circuit and a subscriber line detection circuit,
the protection circuit is used for right the simulation second-line signal incoming end of simulation relay interface circuit unit carries out high-voltage isolation, it is used for intercepting to get electric and balanced circuit the feed power of simulation second-line signal, and will feed power with the power of simulation relay access device is earthed together, 2/4 line converting circuit be used for with simulation second-line signal converts to simulation four-wire signal, subscriber line detection circuitry is used for right under master control module's control simulation four-wire signal carries out ringing current detection, simulation pick-up and hang-up, polarity reversal detection, loopback test.
Further, the protection circuit is a diode protection circuit.
Further, the main control module includes an ethernet circuit for downloading a debugging program, performing ringing detection and reporting, and performing dual tone multi-frequency signal detection and reporting, and the ethernet circuit is a 10M/100M self-adaptive ethernet circuit composed of a PHY circuit of a physical layer of a 100M ethernet port and a transformer circuit.
Furthermore, the logic processing module comprises a Field Programmable Gate Array (FPGA) main chip, an external clock circuit and a configuration circuit, wherein the external clock circuit and a phase-locked circuit inside the FPGA main chip form a clock system, the clock system is used for providing a working clock for the main control module, and the FPGA main chip reads a program stored in the configuration circuit.
Furthermore, the main control module is also used for configuring and reading a custom register in the FPGA main chip through a bus interface.
Further, the analog relay access device further comprises a backplane connector for connecting the analog relay access device with a backplane.
Furthermore, the analog relay access device further comprises a buffer and drive circuit for isolating interference information transmitted to the analog relay access device through the backboard from the outside.
Further, the analog relay access device further includes a station and a board number processing module, configured to obtain, after the analog relay access device is connected to the backplane through the backplane connector, an equipment number of the equipment to which the backplane belongs and an identifier allocated to the analog relay access device by the equipment.
Furthermore, the analog relay access device further comprises a power supply module, and the power supply module comprises a hot plug circuit.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
by arranging the caller identification and dual-tone multi-frequency forwarding unit, the caller identification and dual-tone multi-frequency forwarding unit is used for decoding dual-tone multi-frequency signals in the analog four-wire signals into first digital signals and forwarding the first digital signals and frequency shift keying signals in the analog four-wire signals to the logic processing module, the logic processing module is used for sending the first digital signals and the frequency shift keying signals to the main control module, the main control module is used for determining a called user according to the first digital signals and sending the frequency shift keying signals to the called user, and the called user can display the calling number of the calling user according to the frequency shift keying signals.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a communication system according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an analog relay access device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a main control module according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
To better understand the present invention, the following briefly introduces an application scenario of an analog relay access device provided by the present invention, fig. 1 is a schematic structural diagram of a communication system provided by an embodiment of the present invention, and as shown in fig. 1, the system includes four telephones J1, J2, J3, and J4, a first analog relay interface device C1, a second analog relay interface device C2, and PCM (pulse code Modulation), where J1, J2, and the first analog relay interface device C1 form a small office a, J3, J4, and the second analog relay interface device C2 form a small office B, the office a is connected to the PCM switching center P through an analog relay access device, and the office B is connected to the PCM switching center C through another analog relay access device.
An analog relay access device is provided in an embodiment of the present invention, and fig. 2 is a schematic structural diagram of an analog relay access device provided in an embodiment of the present invention, and as shown in fig. 2, the device includes an analog relay interface voice module 100, a logic processing module 200, and a main control module 300.
The analog relay interface voice module 100 includes an analog relay interface circuit unit 110, a caller id and dual tone multi-frequency forwarding unit 120, and a codec unit 130.
The analog relay interface circuit unit 110 is configured to convert an analog two-line signal accessed to the analog relay interface voice module 100 into an analog four-line signal through the analog relay interface circuit unit 110, the caller id display and dual-tone multi-frequency forwarding unit 120 is configured to decode a dual-tone multi-frequency signal in the analog four-line signal into a first digital signal and forward a frequency shift keying signal in the first digital signal and the analog four-line signal to the logic processing module 200, and the logic processing module 200 is configured to send the first digital signal and the frequency shift keying signal to the main control module 300.
The codec unit 130 is configured to convert the voice signal of the analog four-wire signal into a second digital signal, and transmit the second digital signal to the main control module 300 through the logic processing module 200.
The main control module 300 is configured to determine a called user according to the first digital signal, and send the frequency shift keying signal to the called user, and the called user displays the calling number of the calling user according to the frequency shift keying signal.
The embodiment of the invention is provided with the caller identification and dual-tone multi-frequency forwarding unit, wherein the caller identification and dual-tone multi-frequency forwarding unit is used for decoding a dual-tone multi-frequency signal in an analog four-wire signal into a first digital signal and forwarding a frequency shift keying signal in the first digital signal and the analog four-wire signal to the logic processing module, the logic processing module is used for sending the first digital signal and the frequency shift keying signal to the main control module, the main control module is used for determining a called user according to the first digital signal and sending the frequency shift keying signal to the called user, and the called user can display the calling number of a calling user according to the frequency shift keying signal.
The analog relay interface circuit unit 110 may also convert the analog four-wire signal into an analog two-wire signal, among others. The caller identification and dtmf forwarding unit 120 may employ a modem chip CMX 865A.
Specifically, the analog four-wire signal output interface of the analog relay interface circuit unit 110 is connected to the caller id display and dual tone multi-frequency forwarding unit 120 and the codec unit 130, the codec unit 130 is connected to the logic processing module 200 through a TDM (Time division multiplexing) bus, the logic processing module 200 is connected to the main control module 300 through a TDM bus, and the main control module 300 receives the second digital signal through the TDM bus, where the main control module 300 is a minimum system module.
The caller id display and dual tone multi-frequency forwarding unit 120 and the codec unit 130 are connected to the logic processing module 200 through an SPI (Serial peripheral interface) bus, and the logic processing module 200 is connected to the main control module 300 through the SPI bus, so that the main control module 300 configures parameters in the caller id display and dual tone multi-frequency forwarding unit 120 and the codec unit 130.
The codec module 130 may be further configured to convert the second digital signal into an analog four-wire signal.
Specifically, the main core chip of the codec module 130 may adopt LE78D11 produced by Zarlink, which provides the processing capability of separate two-way codec. The chip not only has the function of editing, but also can provide an SPI interface for the main control module 300 and provide a channel for information interaction between the main control module 300 and the caller identification and dual-tone multi-frequency forwarding unit 120. And the chip is internally provided with a compact digital signal processing core, and can process various signal tones and generate various calling process tones with variable parameters.
Further, the analog relay interface circuit unit 110 includes a protection circuit, a power supply and balancing circuit, an 2/4 line conversion circuit, and a subscriber line detection circuit.
The protection circuit is used for high-voltage isolation of the analog two-line signal access terminal of the analog relay interface circuit unit 110.
The protection circuit is a diode protection circuit. A protection diode P3100SC may be optionally used. The protection circuit is applied to the analog two-wire signal access end, and high voltage is introduced to prevent the user line from being exposed to the outside and being struck by lightning so as to damage an internal low-voltage circuit. The protection circuit is positioned at the front stage part of the whole voice processing circuit, isolates high voltage (up to 3KV) introduced by a circuit, and plays a certain protection role for the back-end circuit.
The power taking and balancing circuit is used for intercepting a feed power supply of the analog two-line signal and grounding the feed power supply and a power supply of the analog relay access device.
Specifically, the power taking and balancing circuit adopts a rectifier bridge circuit S1ZB60 and a peripheral circuit to realize the feed power supply provided by intercepting an analog two-wire signal.
The 2/4 line conversion circuit is used to convert the analog two-line signal into an analog four-line signal, and the main control module 300 is used to control the subscriber line detection circuit to perform ringing detection, analog pick-and-hang, polarity inversion detection, and loop test on the analog four-line signal.
Alternatively, the 2/4 wire conversion circuit is also used to convert an analog four-wire signal to an analog two-wire signal.
The 2/4 line conversion circuit and the user line detection circuit are both formed by chips which are integrated highly and adopt the capacitive coupling technology. For example, a dedicated chip CPC5622 with high integration level can be used, and the chip uses a capacitive coupling Circuit as a preceding stage coupling Circuit, so that compared with the prior art which uses a transformer Circuit as a preceding stage coupling Circuit, the reliability of the Circuit is improved, and the Board layout area of a PCB (Printed Circuit Board) is reduced.
Further, the logic processing module 200 includes a main FPGA (Field-Programmable Gate Array), an external clock circuit and a configuration circuit, where the external clock circuit and a phase-locked circuit inside the main FPGA chip form a clock system, the clock system is used to provide a working clock for the main control module, and the main FPGA chip reads a program stored in the configuration circuit.
Specifically, the FPGA main chip may select 10M08SCU169I7, the chip provides 130 pins and +3.3V working voltage to the outside, the external clock circuit is a 16.384MHZ crystal oscillator clock circuit, and forms a clock system with a phase-locked loop circuit provided inside the chip, so as to provide all working clocks for the logic chip, so as to meet the working requirements.
Further, as shown in fig. 2, the main control module 300 is further configured to configure and read a custom register in the FPGA main chip of the logic processing module 200 through a Local Bus interface.
Fig. 3 is a schematic structural diagram of a master control module according to an embodiment of the present invention, and as shown in fig. 3, the master control module 300 includes a central processing unit K1, a RAM random access memory K2, a ROM program read only memory K3, a buffer circuit K4, a hardware watchdog circuit K5, a reset circuit K6, a clock circuit K7, and an ethernet circuit K8.
The RAM random access memory K2, the ROM program read-only memory K3 and the buffer circuit K4 are all connected with the central processing unit K1 through a data bus, an address bus and a control bus, and the data bus and the address bus adopt a multiplexing mode. The hardware watchdog circuit K5, the reset circuit K6, the clock circuit K7 and the Ethernet circuit K8 are connected with the central processor K1.
Specifically, the buffer circuit K4 is provided on the Local Bus.
Specifically, the central processing unit K1 may select an M82359 chip. The RAM K2 can be selected from two chips with 16-bit data width and model MT46V64M8 to form 32 data bus. The ROM program read only memory K3 can select the core chip SST39VF040 of 4M in amount as the storage space (BOOTROM) of the system start code. The buffer circuit K4 may select the chip with model 74FCT541 as the master chip, and the master chip of the hardware watchdog circuit K5 may select IMP 706. The clock circuit K7 selects a crystal oscillator of 25 MHZ.
In this embodiment, a 100M PHY (Physical Layer) chip is connected to the cpu K1 through the mil port of the cpu, and a transformer circuit is added to form a 10M/100M adaptive ethernet circuit K8, and chip selection models of the PHY circuits of the 10M ethernet and the 100M ethernet port are LXT971ALE and ethernet transformer.
The Ethernet circuit K8 is used for downloading debugging programs, detecting and reporting ringing current, and detecting and reporting DTMF signals. And is used for realizing the exchange of the central processing unit K1 and the external IP message data.
Further, the analog relay access device further comprises a backplane connector 500 for connecting the analog relay access device with a backplane. Backplane connector 500 is connected to logic processing module 200.
In particular, backplane connector 500 may be selected for use with a high density 110-core connector.
Further, as shown in fig. 2, the analog relay access device further includes a buffer and driving circuit 400 for isolating the interference information transmitted to the analog relay access device through the backplane from the outside. The buffer and driver circuit 400 is located between the backplane connector 500 and the logic processing module 200.
The buffering and driving circuit 400 may select a chip with model 74FCT541 as the master chip.
Further, the analog relay access device further includes a station and board number processing module 700, where the station and board number processing module 700 is configured to obtain the device number of the device to which the backplane belongs and the identifier allocated by the device to the analog relay access device after the analog relay access device is connected to the backplane through the backplane connector 500. The station number is the equipment number of the equipment (namely, the backplane) where the analog relay access device is located, and the board number is the identity allocated to the analog relay access device by the equipment.
Further, the analog relay access device further includes a power module 600 for supplying power to the analog relay access device. The power module 600 includes a hot-plug circuit for providing a stable operating voltage for the analog relay access device. The hot plug circuit can be used for plugging the analog relay access device without power failure, so that the work of the whole analog relay access device is not influenced. The circuit can also provide a very stable working voltage for the whole analog relay access device.
Specifically, the power module 600 may adopt a main chip of the model TPS2421, where the main chip has a hot plug function and a power smoothing function, and may protect a back-end circuit to some extent. The core chips of the power module 600 are MCP1820D and EN5339QI, and the first chip, in cooperation with a simple peripheral circuit, can provide a power supply with relatively high power and high quality for the whole analog relay access device, and is mainly used for accessing a +12V power supply to convert and output a +5V power supply. The second chip has a higher integration level, and integrates devices such as an inductor, a Pulse Width Modulation (PWM), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the like, and can easily provide +3.3V, 2.5V, +1.8V, and 1.2V working voltages for the whole analog relay access device by adding a precise resistor outside.
In operation, when the system is powered on, the main control module 300 initializes the analog relay voice module 100. At this time, all the ports are in a normal simulated on-hook state, and the functions of ringing current detection and polarity detection of the analog line are simultaneously achieved. If the local side is sent into the ringing current according to the service, the analog relay access device carries out analog off-hook, if a secondary calling process exists, the device is required to be used for an incoming call display and a dual-tone multi-frequency receiving and transmitting module to send a required first digital signal and the frequency shift keying signal. Then, the local side voice is sent to the PCM switching system after being accessed, coded and decoded by the coding and decoding module 300 to complete the following communication function.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An analog relay access device is characterized in that the device comprises an analog relay interface voice module, a main control module and a logic processing module, wherein the analog relay interface voice module comprises an analog relay interface circuit unit, a caller identification and dual-tone multi-frequency forwarding unit and a coding and decoding unit,
the analog relay interface circuit unit is configured to convert an analog two-wire signal accessed to the analog relay interface voice module into an analog four-wire signal, the caller identification and dual-tone multi-frequency forwarding unit is configured to decode a dual-tone multi-frequency signal in the analog four-wire signal into a first digital signal and forward a frequency shift keying signal in the first digital signal and the analog four-wire signal to the logic processing module, and the logic processing module is configured to send the first digital signal and the frequency shift keying signal to the main control module;
the coding and decoding unit is used for converting the voice signal of the analog four-wire signal output by the analog relay interface circuit unit into a second digital signal and sending the second digital signal to the main control module through the logic processing module;
the main control module is used for determining a called user according to the first digital signal and sending the frequency shift keying signal to the called user, and the called user displays the calling number of the calling user according to the frequency shift keying signal.
2. The apparatus of claim 1, wherein the analog relay interface circuit unit includes a protection circuit, a power-taking and balancing circuit, an 2/4 wire conversion circuit, and a subscriber line detection circuit,
the protection circuit is used for right the simulation second-line signal incoming end of simulation relay interface circuit unit carries out high-voltage isolation, it is used for intercepting to get electric and balanced circuit the feed power of simulation second-line signal, and will feed power with the power of simulation relay access device is earthed together, 2/4 line converting circuit be used for with simulation second-line signal converts to simulation four-wire signal, subscriber line detection circuitry is used for right under master control module's control simulation four-wire signal carries out ringing current detection, simulation pick-up and hang-up, polarity reversal detection, loopback test.
3. The apparatus of claim 2, wherein the protection circuit is a diode protection circuit.
4. The apparatus of claim 2, wherein the main control module comprises an ethernet circuit for downloading a debugging program, performing ringing detection and reporting, and performing dual tone multi-frequency signal detection and reporting, and the ethernet circuit is a 10M/100M adaptive ethernet circuit formed by a PHY circuit of a 100M ethernet port and a transformer circuit.
5. The device of claim 1, wherein the logic processing module comprises a Field Programmable Gate Array (FPGA) main chip, an external clock circuit and a configuration circuit, the external clock circuit and a phase-locked circuit inside the FPGA main chip form a clock system, the clock system is used for providing a working clock for the main control module, and the FPGA main chip reads a program stored in the configuration circuit.
6. The device of claim 5, wherein the master control module is further configured to configure and read custom registers in the FPGA master chip through a bus interface.
7. The apparatus of claim 1, wherein the analog relay access device further comprises a backplane connector for connecting the analog relay access device to a backplane.
8. The apparatus of claim 7, wherein the analog trunk access apparatus further comprises a buffer and driving circuit for isolating interference information transmitted to the analog trunk access apparatus through the backplane from the outside.
9. The apparatus according to any one of claims 1 to 8, wherein the analog relay access apparatus further comprises a station and board number processing module, configured to obtain, after the analog relay access apparatus is connected to a backplane through a backplane connector, a device number of a device to which the backplane belongs and an identifier assigned by the device to the analog relay access apparatus.
10. The apparatus of any of claims 1-8, wherein the analog relay access device further comprises a power module, the power module comprising a hot swap circuit.
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| CN201711487729.6A CN108347660B (en) | 2017-12-29 | 2017-12-29 | Analog relay access device |
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| CN201711487729.6A CN108347660B (en) | 2017-12-29 | 2017-12-29 | Analog relay access device |
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| CN112305404B (en) | 2020-09-29 | 2022-11-08 | 上海兆芯集成电路有限公司 | Nuclear partition circuit and test device |
| CN113162654B (en) * | 2021-04-01 | 2022-09-27 | 中国人民解放军63629部队 | Digital multiplexer |
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