CN108334337B - Low-delay instruction dispatcher with automatic management function and filtering guess access method - Google Patents
Low-delay instruction dispatcher with automatic management function and filtering guess access method Download PDFInfo
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- CN108334337B CN108334337B CN201810088578.5A CN201810088578A CN108334337B CN 108334337 B CN108334337 B CN 108334337B CN 201810088578 A CN201810088578 A CN 201810088578A CN 108334337 B CN108334337 B CN 108334337B
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- 238000001914 filtration Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 title claims abstract description 7
- 230000006870 function Effects 0.000 claims abstract description 4
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- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
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Abstract
The invention discloses a low-delay instruction dispatcher with an automatic management function, which is connected with a microprocessor through a local memory bus, and comprises an automatic management module and a speculative access filter, wherein the speculative access filter filters out speculative repeated access from the microprocessor and sends the speculative repeated access to the automatic management module after receiving effective access from the microprocessor. The invention also discloses a filtering guess access method of the low-delay instruction scheduler. The present invention can effectively filter speculative repeat accesses.
Description
Technical Field
The present invention relates to instruction schedulers.
Background
In the existing chip architecture, if an instruction scheduler with an automatic pointer management module is connected with some specific microprocessors through a local memory bus, some redundant repeated accesses are generated, so that the automatic management module generates false operation, and further the system chip is operated wrongly. How to effectively prevent the problem from being generated is a problem to be solved by the technical personnel in the field.
Disclosure of Invention
It is an object of the present invention to provide a low latency instruction scheduler with auto-management that filters speculative repeat accesses.
It is another object of the present invention to provide a method for filtering speculative accesses in a low latency instruction scheduler that effectively filters speculative repeat accesses.
The technical scheme for realizing the purpose is as follows:
a low-delay instruction dispatcher with automatic management function is connected with a microprocessor through a local memory bus, and comprises an automatic management module and a speculative access filter, wherein,
the speculative access filter filters out speculative repeat accesses from the microprocessor and sends valid accesses from the microprocessor to the auto-management module upon receiving them.
Preferably, the speculative access filter records the address to be accessed next each time command data is written, and filters out the access next time if the address written by the next command data is the same as the last time; if the next command data writing address is the same as the address to be accessed next time, it indicates that the access is valid.
Preferably, the system further comprises an instruction memory and an instruction number register which are connected with the automatic management module.
In the second filtering guess access method based on the low latency instruction scheduler of the present invention, when the command data is written each time, the guess access filter records the address to be accessed next time, and if the write address of the command data next time is the same as the previous time, the guess access filter filters out the access; if the next command data write address is the same as the address of the record to be accessed next time, the speculative access filter sends the access to the auto-management module.
The invention has the beneficial effects that: the present invention compares each access by adding a guess access filter, if not conforming to the expectation, the filter discards the access, if conforming to the expectation, the instruction is received and sent to the automatic management module, and thus, the correctness of the system operation is ensured not to be influenced by the guess access.
Drawings
FIG. 1 is a state diagram of a low latency instruction scheduler according to the present invention in an architecture in which speculative repeat accesses are received;
FIG. 2 is a state diagram of a prior art low latency instruction scheduler receiving speculative repeat accesses.
Detailed Description
The invention will be further explained with reference to the drawings.
Referring to FIG. 1, a low-latency instruction scheduler with auto-management according to one embodiment of the present invention, which is coupled to a microprocessor via a local memory bus, includes an auto-management module 1 and a speculative access filter 2. The auto management module 1 is an auto pointer management module.
The speculative access filter 2 filters out speculative repeat accesses from the microprocessor and sends valid accesses from the microprocessor to the hypervisor 1, which the hypervisor 1 acts upon. Specifically, each time the command data is written, the speculative access filter 2 records the address to be accessed next, and if the next command data write address is the same as the previous address, the speculative access filter 2 determines that the access is repeated and filters out the access. If the next command data write address is the same as the address recorded to be accessed next time, indicating that the access is valid, the speculative access filter 2 sends the instruction of the access to the AMM 1. This allows the instruction scheduler associated with a particular local memory bus to operate normally without speculative access effects.
In addition, the low-latency instruction scheduler further comprises an instruction memory and an instruction number register which are connected with the automatic management module 1. FIG. 2 is a block diagram of a prior art low latency instruction scheduler, without filtering, with an instruction number register incremented by 1 when speculative repeat accesses occur. In FIG. 1, speculative repeat accesses are filtered and the instruction number register is unchanged.
In the second filtering guess access method based on the low latency instruction scheduler of the present invention, the speculative access filter 2 records the address to be accessed next time when the command data is written each time, and if the address written by the next command data is the same as the previous time, the speculative access filter 2 filters out the access; if the next command data write address is the same as the address of the next recorded access to be made, the speculative access filter 2 sends the access to the AMM 1.
The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and therefore all equivalent technical solutions should also fall within the scope of the present invention, and should be defined by the claims.
Claims (2)
1. A low-delay instruction dispatcher with automatic management function is connected with a microprocessor through a local memory bus, and comprises an automatic management module and is characterized by also comprising a speculative access filter, wherein,
the speculative access filter filters out speculative repeat accesses from the microprocessor and sends valid accesses from the microprocessor to the auto-management module upon receipt of such accesses;
the speculative access filter records the address to be accessed next time when command data is written every time, and filters out the access next time if the address written by the command data next time is the same as the last time; if the next command data writing address is the same as the recorded address to be accessed next time, the access is effective;
the automatic management system also comprises an instruction memory and an instruction number register which are connected with the automatic management module.
2. A method for filtering speculative access by a low-latency instruction scheduler according to claim 1, wherein the speculative access filter records the address to be accessed next time each time command data is written, and filters out the access next time the address is written the same as the last time; if the next command data write address is the same as the address of the record to be accessed next time, the speculative access filter sends the access to the auto-management module.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810088578.5A CN108334337B (en) | 2018-01-30 | 2018-01-30 | Low-delay instruction dispatcher with automatic management function and filtering guess access method |
| PCT/CN2018/099740 WO2019148793A1 (en) | 2018-01-30 | 2018-08-09 | Low latency instruction scheduler containing automatic management function and method for filtering speculative access |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810088578.5A CN108334337B (en) | 2018-01-30 | 2018-01-30 | Low-delay instruction dispatcher with automatic management function and filtering guess access method |
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| CN108334337A CN108334337A (en) | 2018-07-27 |
| CN108334337B true CN108334337B (en) | 2022-02-01 |
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| WO (1) | WO2019148793A1 (en) |
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| CN108334337B (en) * | 2018-01-30 | 2022-02-01 | 江苏华存电子科技有限公司 | Low-delay instruction dispatcher with automatic management function and filtering guess access method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101498744A (en) * | 2007-08-14 | 2009-08-05 | 福鲁克公司 | Rotary switch memory for digital multimeter |
| CN105677299A (en) * | 2016-01-05 | 2016-06-15 | 天脉聚源(北京)传媒科技有限公司 | Method and device used for identification selection |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000068783A2 (en) * | 1999-05-12 | 2000-11-16 | Analog Devices, Inc. | Digital signal processor computation core |
| US7707396B2 (en) * | 2006-11-17 | 2010-04-27 | International Business Machines Corporation | Data processing system, processor and method of data processing having improved branch target address cache |
| CN101488965B (en) * | 2009-02-23 | 2012-02-15 | 中国科学院计算技术研究所 | Domain name filtering system and method |
| US20110047357A1 (en) * | 2009-08-19 | 2011-02-24 | Qualcomm Incorporated | Methods and Apparatus to Predict Non-Execution of Conditional Non-branching Instructions |
| US9135012B2 (en) * | 2012-06-14 | 2015-09-15 | International Business Machines Corporation | Instruction filtering |
| CN103150265B (en) * | 2013-02-04 | 2015-10-21 | 山东大学 | The fine-grained data distribution method of isomery storer on Embedded sheet |
| US9767026B2 (en) * | 2013-03-15 | 2017-09-19 | Intel Corporation | Providing snoop filtering associated with a data buffer |
| CN108334337B (en) * | 2018-01-30 | 2022-02-01 | 江苏华存电子科技有限公司 | Low-delay instruction dispatcher with automatic management function and filtering guess access method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101498744A (en) * | 2007-08-14 | 2009-08-05 | 福鲁克公司 | Rotary switch memory for digital multimeter |
| CN105677299A (en) * | 2016-01-05 | 2016-06-15 | 天脉聚源(北京)传媒科技有限公司 | Method and device used for identification selection |
Non-Patent Citations (1)
| Title |
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| 基于LLVM的科学计算程序自动性能预测研究;谢虎成;《中国优秀硕士学位论文全文数据库 信息科技辑》;20170215(第 02 期);I138-118 * |
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| CN108334337A (en) | 2018-07-27 |
| WO2019148793A1 (en) | 2019-08-08 |
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