CN108270402B - Voltage detection and control circuit - Google Patents

Voltage detection and control circuit Download PDF

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CN108270402B
CN108270402B CN201810199958.6A CN201810199958A CN108270402B CN 108270402 B CN108270402 B CN 108270402B CN 201810199958 A CN201810199958 A CN 201810199958A CN 108270402 B CN108270402 B CN 108270402B
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voltage
module
output
input end
comparator
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CN108270402A (en
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宁宁
靳泽熙
罗建
夏华松
李靖
吴克军
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold

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Abstract

Voltage detection and control circuit belongs to analog integrated circuit technical field. The voltage comparator comprises a reference voltage output buffer module, a voltage operation module and a comparator module, wherein the input end of the reference voltage output buffer module is connected with reference voltage, and the output end of the reference voltage output buffer module is connected with a second input end of the voltage operation module; the first input end of the voltage operation module is connected with an external adjustment voltage, and a comparison signal is obtained by processing input signals of the first input end and the second input end of the voltage operation module and is output to the first input end of the comparator module; the second input end of the comparator module is connected with the voltage to be detected, and a control signal is obtained by comparing the voltage to be detected and the comparison signal and serves as an output signal of the voltage detection and control circuit. The invention has large detection range and wide application range; the gain-stabilized dynamic amplifier is particularly suitable for a dynamic amplifier, and the amplification factor of the dynamic amplifier which does not change along with the change of the power supply voltage is obtained within a certain change range of the power supply voltage, so that the gain-stabilized dynamic amplifier resisting the power supply voltage fluctuation is obtained.

Description

Voltage detection and control circuit
Technical Field
The invention belongs to the technical field of analog integrated circuits, relates to a voltage detection and control circuit, and is particularly suitable for detection of power supply voltage fluctuation of a dynamic amplifier and correction of gain under the power supply voltage fluctuation.
Background
The progress of the integrated circuit technology enables the working speed of the digital circuit to be continuously improved, the integration density to be continuously increased, the power supply voltage to be gradually reduced, and the data representing the comprehensive performance of the digital circuit to be obviously improved; however, process advances and supply voltage reductions degrade the performance of many important analog circuit blocks, affecting the most important amplifiers of the genus. As a basic module widely used in analog circuits, on the one hand, process progress has produced many non-ideal effects of CMOS devices, which have a large impact on sensitive analog circuits, and on the other hand, the structural choice of amplifiers is limited due to the reduced supply voltage. In view of this, the dynamic amplifier becomes a hot point of design and research, has a simple structure and no static power consumption, well adapts to low power supply voltage, and greatly reduces power consumption, so that the dynamic amplifier is applied to a plurality of circuits, such as an analog-to-digital converter (ADC); however, the gain of the dynamic amplifier is susceptible to the power supply voltage fluctuation, which is difficult to avoid in practical circuits, and this greatly limits the performance and the applicable range of the dynamic amplifier, so when designing and using the dynamic amplifier, it is necessary to consider reducing or eliminating the influence of the power supply voltage fluctuation on the gain.
A dynamic amplifier with common mode detection is shown in figure 1, and in figure 1, the dynamic amplifier mainly comprises a fourth PMOS tube M1, a fifth PMOS tube M2 and a sixth PMOS tube M3 for resetting, a third NMOS tube M4 and a fourth NMOS tube M5 which are used as input geminate transistors, a fifth NMOS tube M6 and a sixth NMOS tube M7 for controlling the amplification process, a capacitor second capacitor C for detecting an output common mode and a second capacitor C7 for detecting the output common mode1A third capacitor C2A first voltage controlled switch SW1 and a second voltage controlled switch SW2 for controlling the input of the output and a fourth capacitor C for representing the loadLNA fifth capacitor CLPAnd (4) forming. In the figure, an external clock signal clk controls the dynamic amplifier to switch between the reset stage and the amplification stage, and a common mode detector CMD outputs a common mode VxPerforming detection when V isxWhen the point voltage is greater than the set fixed voltage, outputting VctrlAt a high level, when VxWhen the point voltage is less than the set fixed voltage, outputting VctrlIs low level; by outputting a control signal VctrlAnd the amplification is controlled to be finished by changing the voltage of the grid end of the fifth NMOS transistor M6, and the load and the dynamic amplifier output are disconnected by controlling the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 which are connected with the load.
Wherein, in the reset phase, the signal clk controlled by the external clock is low, and a fourth signal for resetThe PMOS transistor M1, the fifth PMOS transistor M2 and the sixth PMOS transistor M3 are turned on, the sixth NMOS transistor M7 controlled by clk is turned off, and the internal node V of the dynamic amplifier1、V2、VxCharged to the supply voltage, V output by the common mode detector CMDctrlAt a high level, the fifth NMOS transistor M6 is turned on, the first voltage controlled switch SW1 and the second voltage controlled switch SW2 are turned on, and the fourth capacitor C of the output load is turned onLNA fifth capacitor CLPAnd the amplifier is directly connected and charged to the power supply voltage, which is the reset state.
When the external clock signal clk changes to high level, the dynamic amplifier starts to amplify, which comprises the following specific processes: the fourth PMOS transistor M1, the fifth PMOS transistor M2 and the sixth PMOS transistor M3 controlled by the external clock signal clk are directly turned off, and at the moment, V is directly turned offxMaintain high resistance, then VxThe total amount of node charge is kept constant, the sixth NMOS transistor M7 controlled by clk is turned on, and the input signal V is kept constant during the amplification periodip、VinThe third NMOS transistor M4 and the fourth NMOS transistor M5 are controlled to start to couple V1、V2Discharging the two nodes if the set common mode voltage is VdetNMOS threshold voltage of input pair transistor of dynamic amplifier is Vth，β＝Coxμ W/L, wherein CoxIs unit area gate oxide layer capacitance, mu is carrier mobility, W/L is MOS tube width-length ratio, and load capacitance CLP＝CLN＝CLThen Voutn，VoutpThe voltage variation of the two points is related to the input signal and the time as follows:
Figure GDA0002809021590000021
Figure GDA0002809021590000022
at V1、V2During the discharge process of (V)xThe voltage of the point will pass through the second capacitor C1A third capacitor C2Following V1、V2Variation, usually by taking C1＝C2Then V in the course of dischargexThe expression for the change in dot voltage is:
Figure GDA0002809021590000023
Vxvoltage of point following V1、V2Is continuously reduced, when the discharge is reduced to a set common mode voltage, then V isctrlChanging from high level to low level, the fifth NMOS transistor M6 of the dynamic amplifier is controlled to be turned off, and V is cut off1、V2The first voltage controlled switch SW1 and the second voltage controlled switch SW2 are simultaneously turned off to disconnect the load capacitor and the output of the dynamic amplifier, thereby storing the amplified voltage for an amplification time VxFrom the mains voltage VDDThe time t to discharge to the set common mode voltage can be expressed as:
Figure GDA0002809021590000024
accordingly, the gain can be determined by the amplification time:
Figure GDA0002809021590000025
in the above formula VcmFor inputting differential signals VipAnd VinWhen the common mode level of (V)ipAnd VinWhen the difference of (a) is small, the gain expression can be simplified as follows:
Figure GDA0002809021590000026
obviously, the gain sum V of the dynamic amplifier can be found by the gain expressionDDIn the practical circuit, the power supply voltage is likely to be at different DC voltages, and even if the voltage regulator is used for voltage stabilization, the fluctuation of the power supply voltage can affect the increase of the dynamic amplifierThis, in turn, creates a potential problem for circuit applications requiring fixed gain amplifiers, causing variations in the amplification of the input signal.
Disclosure of Invention
In view of the above disadvantages, the present invention provides a voltage detection and control circuit for detecting voltage and providing a control signal according to the detection result, and is particularly suitable for power supply voltage fluctuation detection of a dynamic amplifier and gain correction under power supply voltage fluctuation.
The technical scheme of the invention is as follows:
the voltage detection and control circuit comprises a reference voltage output buffer module 402, a voltage operation module 403 and a comparator module 404,
the input end of the reference voltage output buffer module 402 is connected to a reference voltage, and the output end thereof is connected to the second input end of the voltage operation module 403;
a first input end of the comparator module 404 is connected to the output end of the voltage operation module 403, a second input end thereof is connected to the voltage to be detected, and an output end thereof is used as an output end of the voltage detection and control circuit;
the voltage operation module 403 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first capacitor C3A first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1 and a second PMOS transistor MP2,
a source of the first PMOS transistor MP1 serving as a first input terminal of the voltage operation module 403 is connected to an external adjustment voltage, a gate thereof is connected to an output terminal of the first inverter INV1, a drain thereof is connected to drains of the first NMOS transistor MN1 and the second PMOS transistor MP2, and the first capacitor C3The upper plate of (1);
the input end of the second inverter INV2 is connected to the input end of the first inverter INV1 and is connected to the external clock signal clk, and the output end of the second inverter INV2 is connected to the gate of the first NMOS transistor MN 1;
the source of the second PMOS transistor MP2 is connected to the source of the first NMOS transistor MN1 and serves as the second input terminal of the voltage operation module 403, and the gate thereof is connected to the input terminal of the third inverter INV3 and the external clock signal clk;
the gate of the second NMOS transistor MN2 is connected to the output terminal of the third inverter INV3, and the drain thereof is connected to the first capacitor C3And the source of the lower plate of the voltage operation module 403 is grounded.
Specifically, the reference voltage output buffer module 402 includes an operational amplifier, a first resistor R1 and a third PMOS transistor MP3,
the positive input end of the operational amplifier is connected with the reference voltage, the negative input end of the operational amplifier is connected with the drain electrode of the third PMOS transistor MP3 and one end of the first resistor R1 and serves as the output end of the reference voltage output buffer module 402, the output end of the operational amplifier is connected with the gate electrode of the third PMOS transistor MP3, the source electrode of the third PMOS transistor MP3 is connected with the power voltage, and the other end of the first resistor R1 is grounded.
Specifically, the comparator module 404 includes a comparator 405, a negative input terminal of the comparator 405 is connected to the output terminal of the voltage operation module 403, a positive input terminal of the comparator is connected to the voltage to be detected, and an output terminal of the comparator is used as the output terminal of the voltage detection and control circuit.
In particular, the external regulation voltage VYIs greater than the voltage value V at the output of the reference voltage output buffer module 402refbuf。
The working principle of the invention is as follows:
reference voltage VrefIs an accurate voltage which does not change with the power supply voltage, temperature and process, and a buffer reference voltage V is obtained after the accurate voltage passes through the reference voltage output buffer module 402refbuf(ii) a The voltage operation module 403 adjusts the voltage V to the external under the control of the external clock signal clkYAnd a buffer reference voltage VrefbufProcessing to obtain a comparison signal Vdet＝VY-Vrefbuf(ii) a By comparing the voltage V to be detectedXAnd a comparison signal VdetVoltage value of the control signal VctrlAt low level or high level by adjusting the comparison signal VdetValue of V to adjust the control signal VctrlA high condition.
The invention has the beneficial effects that: the voltage detection and control circuit provided by the invention has a wide detection range and a wide application range, is particularly suitable for a dynamic amplifier, and can adjust a comparison signal V under the fluctuation of power supply voltagedetThe amplification time of the dynamic amplifier under different power supply voltages is adjusted, and the amplification times of the dynamic amplifier which does not change along with the change of the power supply voltage are obtained within a certain change range of the power supply voltage, so that the gain-stabilized dynamic amplifier resisting the power supply voltage fluctuation is obtained.
Drawings
Fig. 1 is a circuit diagram of a conventional charge transfer type dynamic amplifier with common mode detection.
Fig. 2 is a circuit diagram of the voltage detection and control circuit of the present invention when the voltage detection and control circuit is applied to the gain calibration of the charge transfer dynamic amplifier.
Fig. 3 is a schematic diagram of the internal modules of the voltage detection and control circuit according to the present invention.
Fig. 4 is a schematic diagram of an internal structure of the reference voltage output buffer module in the embodiment.
Fig. 5 is a schematic diagram of an internal structure of the voltage operation module according to the present invention.
Fig. 6 is a schematic diagram of an internal structure of the comparator module in the embodiment.
Fig. 7 is a schematic circuit diagram illustrating a charge transfer dynamic amplifier according to an embodiment of the present invention to achieve gain stabilization under voltage fluctuation.
FIG. 8 is a circuit diagram illustrating an embodiment of the present invention for voltage monitoring.
Detailed Description
The invention is further described with reference to the following figures and specific examples.
As shown in FIG. 3, the present invention comprises a reference voltage output buffer module 402, a voltage operation module 403 and a comparator module 404, wherein the input terminal of the reference voltage output buffer module 402 is connected to a reference voltage VrefThe output end of the buffer voltage reference V outputsrefbufTo voltage operationA second input of the calculation module 403; the first input terminal of the voltage operation module 403 is connected to the external adjustment voltage VYProcessing the signals at its first and second input under the control of an external clock signal clk to obtain a comparison signal Vdet＝VY-VrefbufTo a first input of the comparator module 404; the second input terminal of the comparator module 404 is connected to the voltage V to be detectedXBy comparing the voltage V to be detectedXAnd a comparison signal VdetIs worthy of deriving a control signal Vctrl。
The voltage detection and control circuit provided by the invention adjusts the reference voltage VrefAnd an external regulation voltage VYIs worth obtaining different comparison signals VdetSo that the output control signal V of different conditions can be realized as requiredctrlGenerating, comparing the signal VdetMay range from 0 to VDDAnd the detection range is large.
As shown in fig. 2 and 7, the voltage detection and control circuit provided by the present invention can be applied to a dynamic amplifier instead of the common mode detector CMD in the conventional dynamic amplifier, wherein the first input terminal of the voltage detection and control circuit is connected to the output common mode voltage point in the dynamic amplifier, and the second input terminal thereof is connected to the power supply voltage VDDI.e. the voltage V to be detectedXFor outputting the common-mode voltage, an external regulation voltage VYIs a supply voltage VDDControl signal V of outputctrlThe amplification process of the dynamic amplifier is controlled. The charge transfer type dynamic amplifier in the embodiment comprises a fourth PMOS transistor M1, a fifth PMOS transistor M2, a sixth PMOS transistor M3, a third NMOS transistor M4, a fourth NMOS transistor M5, a fifth NMOS transistor M6, a sixth NMOS transistor M7, a second capacitor C1A third capacitor C2A fourth capacitor CLNA fifth capacitor CLPA first voltage controlled switch SW1 and a second voltage controlled switch SW 2. The third NMOS transistor M4 and the fourth NMOS transistor M5 are input pair transistors of the dynamic amplifier, the gate of the third NMOS transistor M4 is the positive phase input terminal of the dynamic amplifier, the gate of the fourth NMOS transistor M5 is the negative phase input terminal of the dynamic amplifier, and the source of the third NMOS transistor M4 is connected to the source of the fourth NMOS transistor M5 and the source of the third NMOS transistor M6The drain electrode and the grid electrode of the third NMOS tube M6 are connected with a control signal VctrlThe source of the sixth NMOS transistor M7 is connected to the drain of the sixth NMOS transistor M7, the gate of the sixth NMOS transistor M7 is connected to the external clock signal clk, and the source is grounded. The drain of the third NMOS transistor M4 is connected to the drain of the fourth PMOS transistor M1 and the second capacitor C1And the input end of the first voltage-controlled switch SW1 is the negative phase output end V of the dynamic amplifier1The drain of the fourth NMOS transistor M5 is connected to the drain of the sixth PMOS transistor M3 and the third capacitor C2The upper plate of the second voltage-controlled switch SW2 is the non-inverting output terminal V of the dynamic amplifier2The drain electrode of the fifth PMOS pipe M2 is connected with a second capacitor C1And a third capacitance C2The gates of the fourth PMOS transistor M1, the fifth PMOS transistor M2 and the sixth PMOS transistor M3 are all connected to an external clock signal clk, and the sources of the fourth PMOS transistor M1, the fifth PMOS transistor M2 and the sixth PMOS transistor M3 are all connected to a supply voltage VDDControl signal V output by the inventionctrlThe first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 are controlled to be closed and opened, and the output end of the first voltage-controlled switch SW1 is connected with the fourth capacitor CLNThe output end of the second voltage-controlled switch SW2 is connected with the fifth capacitor CLPUpper plate of, a fourth capacitor CLNAnd a fifth capacitance CLPThe lower polar plates are all grounded.
Fig. 4 is a circuit structure diagram of the reference voltage output buffer module 402 in this embodiment, which includes an operational amplifier, a first resistor R1 and a third PMOS transistor MP3, wherein a positive input terminal of the operational amplifier is connected to a reference voltage VrefThe negative input end of the buffer module is connected with the drain electrode of the third PMOS tube MP3 and one end of the first resistor R1 and is used as the output end of the reference voltage output buffer module to output buffer reference voltage VrefbufThe output end of the first PMOS tube MP3 is connected with the grid electrode of a third PMOS tube MP3, and the source electrode of the third PMOS tube MP3 is connected with the power supply voltage VDDThe other end of the first resistor R1 is grounded. The reference voltage V needs to be buffered due to the operation process in the voltage operation module 403refbufHas higher response speed, so the reference voltage V needs to be adjustedrefBuffering to obtain a buffered reference voltage VrefbufThe effects ofMainly improves the driving capability, thereby meeting the requirement of response speed in specific application.
Fig. 5 is a schematic structural diagram of the voltage operation module 403 according to the present invention. Fig. 6 is a circuit structure diagram of the comparator module 404 in this embodiment, which includes a comparator 405, where a negative input terminal of the comparator 405 is connected to the output terminal of the voltage operation module, and a positive input terminal thereof is connected to the voltage V to be detectedXThe output end of the voltage detection and control circuit is used as the output end of the voltage detection and control circuit when the voltage V to be detected is detectedXGreater than the comparison signal VdetAt the voltage value of (V), control signal VctrlThe output is high level; when the voltage V to be detectedXLess than the comparison signal VdetAt the voltage value of (V), control signal VctrlThe output is low.
When the external clock signal clk is at a low level, the gates of the fourth PMOS transistor M1, the fifth PMOS transistor M2 and the sixth PMOS transistor M3 connected to the external clock signal clk are all at a low level, the fourth PMOS transistor M1, the fifth PMOS transistor M2 and the sixth PMOS transistor M3 in the dynamic amplifier are turned on, the gate of the sixth NMOS transistor M7 connected to the external clock signal clk is also at a low level, the sixth NMOS transistor M7 is turned off, and the negative phase output terminal V of the dynamic amplifier is turned off1Positive phase output end V2And an internal node VxIs charged to the power supply voltage VDDThe same external clock signal clk is connected to the voltage operation module 403, wherein the external clock signal clk is connected to the gate of the fifth PMOS transistor M9 to turn on the fifth PMOS transistor M9, the external control clock clk is connected to the input ends of the first inverter INV1, the second inverter INV2 and the third inverter INV3, and the external control clock clk makes the gate of the first NMOS transistor MN1 connected to the output end of the second inverter INV2 high, so as to control the turn on of the first NMOS transistor MN 1; the external clock signal clk makes the gate of the first PMOS transistor MP1 connected to the output terminal of the first inverter INV1 high, thereby controlling the first PMOS transistor MP1 to turn off; the external clock signal clk makes the gate of the second NMOS transistor MN2 connected to the output terminal of the third inverter INV3 high, thereby controlling the second NMOS transistor MN2 to be turned on, and then the first capacitor C3Is charged to the reference voltage output buffer module 402Reference buffer voltage VrefbufFirst capacitor C3Is discharged to ground, then the internal node V of the voltage operation module 403topAnd a comparison signal VdetThe voltage of (d) can be expressed as:
Vtop＝Vrefbuf
Vdet＝0
the negative phase input end voltage of the comparator 405 inside the comparator module 404 is the comparison voltage V output by the voltage operation module 403detFor the comparator 405, the non-inverting input terminal of the comparator is connected to the drain node of the fifth PMOS transistor M2 in the dynamic amplifier, i.e. the first input terminal V of the voltage detection and control circuitxIs charged to the power supply voltage VDDHas a VDD>VdetThe output terminal of the comparator 405 is connected to the output terminal of the comparator module 404, so that the control signal V is outputctrlTo a high level, thereby controlling the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 to be closed, so that the negative phase output end V of the dynamic amplifier is enabled1Is connected to a fourth capacitor CLNThe positive phase output end V of the dynamic amplifier2Is connected to a fifth capacitor CLPUpper plate of the capacitor, a fourth capacitor CLNA fifth capacitor CLPThe voltage of the upper polar plate is the power voltage VDDAnd a control signal VctrlThe gate voltage of the fifth NMOS transistor M6 of the connected dynamic amplifier is high, the fifth NMOS transistor M6 is turned on, but since the sixth NMOS transistor M7 is turned off, the entire dynamic amplifier is in the reset phase, and the voltages at the positive phase output terminal and the negative phase output terminal of the dynamic amplifier are:
Voutn＝V1＝VDD
Voutp＝V2＝VDD
when the external clock signal clk changes from low level to high level, the dynamic amplifier starts to amplify, and the specific process is that the gate of the fourth PMOS transistor M1, the gate of the fifth PMOS transistor M2, and the gate of the sixth PMOS transistor M3 connected by the external clock signal clk all change to high level, and the fourth PMOS transistor M1, the fifth PMOS transistor M2, and the sixth PMOS transistor M3 are all controlled to be turned offAt the same time, the external clock signal clk turns the gate of the sixth NMOS transistor M7 to high, the sixth NMOS transistor M7 is turned on, and the gates of the input pair transistors, the third NMOS transistor M4 and the fourth NMOS transistor M5 are respectively connected to the positive input voltage VipNegative phase input voltage VinStarting to the fourth capacitor CLNUpper plate voltage VoutnAnd a fifth capacitance CLPUpper plate voltage VoutpDischarging (positive phase input voltage V)ipAnd negative phase input voltage VinRemains unchanged during the amplification period), the threshold voltages of the third NMOS transistor M4 and the fourth NMOS transistor M5 are defined to be equal and are all VthBoth beta ═ CoxMu W/L are also equal, and the change relation of the output voltage along with the input voltage and the time is as follows:
Figure GDA0002809021590000071
Figure GDA0002809021590000072
the same external clock signal clk is connected to the power supply voltage fluctuation detection module 403, wherein the external clock signal clk is connected to the gate of the second PMOS transistor MP2 to turn off the second PMOS transistor MP2, the external clock signal clk is connected to the input ends of the first inverter INV1, the second inverter INV2 and the third inverter INV3, the external clock signal clk makes the gate of the first NMOS transistor MN1 connected to the output end of the second inverter INV2 low, and controls the first NMOS transistor MN1 to turn off, the external clock signal clk makes the gate of the first PMOS transistor MP1 connected to the output end of the first inverter INV1 low, so as to control the first PMOS transistor MP1 to turn on, the external clock signal clk makes the gate of the second NMOS transistor MN2 connected to the output end of the third inverter INV3 low, and controls the second NMOS transistor MN2 to turn off, and then the first capacitor C is connected to the first capacitor C3Is charged to the supply voltage VDDFifth capacitor C3Lower plate voltage VdetExpressed as:
Vdet＝VDD-Vrefbuf
comparisonThe negative phase input end voltage of the comparator 405 inside the device module 404 is the comparison signal V outputted by the voltage operation module 403detWith respect to the comparator 405, the non-inverting input terminal of the comparator is connected to the drain terminal V of the fifth PMOS transistor M2 in the dynamic amplifierx，VxThe voltage at the point during amplification is expressed as:
Figure GDA0002809021590000081
during amplification, the positive input voltage V of the comparator 405 inside the comparator module 404xThe negative phase input end is the comparison signal V output by the voltage operation module 403 along with the reduction of the amplification timedetPositive input terminal voltage V of comparator 405xFrom VDDGradually decreases once the non-inverting input voltage V of the comparator 405xLess than negative input terminal voltage VdetControl signal V output by comparator 405ctrlWill change from high level to low level to control the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 to turn off and disconnect the negative phase output end of the dynamic amplifier and the fourth capacitor CLNThe positive phase output end of the dynamic amplifier is disconnected with the fifth capacitor C by the connection of the upper polar plateLPThe connection of the upper plate is turned off at the same time, the fifth NMOS transistor M6 is turned off, and the amplification time is determined by the voltage V at the non-inverting input terminal of the comparator 405xFrom VDDDown to VdetDetermines:
Figure GDA0002809021590000082
after the first voltage-controlled switch SW1 and the second voltage-controlled switch SW2 are turned off, the fourth capacitor CLNAnd a fifth capacitance CLPThe upper plate voltage is the negative phase output voltage and the positive phase output voltage of the amplified dynamic amplifier, and is not changed before the next reset, and the gain of the dynamic amplifier obtained correspondingly is expressed as:
Figure GDA0002809021590000083
in the above formula VcmFor inputting differential signals VipAnd VinWhen the common mode level of (V)ipAnd VinWhen the difference of (a) is small, the gain expression can be simplified as follows:
Figure GDA0002809021590000084
through the above-mentioned series of operations, it can be found that the gain of the dynamic amplifier remains unchanged under the fluctuation of the power supply voltage, and it should be noted that the non-inverting input terminal of the reference voltage output buffer module 402 is the reference voltage V generated outside the module and not changing with the voltagerefV obtained by reference voltage output buffer module 402refbufCan be adjusted by the difference of design structure and design parameters (design V in the embodiment)refbuf＝Vref)。
In summary, the voltage detection and control circuit 401 in this embodiment replaces the common mode detector CMD in the conventional dynamic amplifier, and detects the variation of the power voltage through the voltage operation module 403 to obtain different comparison signals VdetThe value of (2) is obtained by combining the comparator module 404 and the corresponding operation of the dynamic amplifier, changing the amplification time of the dynamic amplifier and correcting the amplification factor of the dynamic amplifier under the fluctuation of the power supply voltage, thereby obtaining the dynamic amplifier with the gain stability under the fluctuation of the voltage, overcoming the influence of the change and the fluctuation of the power supply voltage of the traditional dynamic amplifier on the gain, optimizing the performance of the dynamic amplifier to a certain extent and expanding the application range of the dynamic amplifier.
It should be noted that the voltage detection and control circuit provided by the present invention can be used not only for stabilizing the gain of the dynamic amplifier in the dynamic amplifier, but also for other suitable scenarios for detecting the voltage and providing the control signal according to the need. In the embodiment shown in FIG. 8, in which the present invention is applied to the voltage monitoring field, the input terminal of the reference voltage output buffer module is connected to an external reference voltage Vref2The output end of which is connected toThe second input end is connected with the voltage operation module; the first input end of the voltage operation module is connected with another external reference voltage Vref1The clock signal input end of the clock is connected with an external clock signal clk; the positive input end of the comparator module is connected with the output end of the voltage operation module, and the negative input end of the comparator module is connected with an external voltage V to be detectedi。
When the external clock signal clk is at a low level, the voltage detection and control circuit in this embodiment is in a reset state, and the output signal V of the voltage operation moduledetWhen the external reference voltage V is 0, the external reference voltage V can be selected according to actual needsref1And Vref2After the value is selected and stable, the external clock signal clk is set to high level, the monitoring function is started, and then the voltage operation module processes the obtained Vdet＝Vref1-Vref2In this case, the basic function of the circuit can be expressed as: under normal conditions Vi>VdetOutputs a control signal VctrlHigh, once V occurs during monitoringi<VdetOutputs a control signal VctrlGoes low and the output can be used as a decision ViAnd VdetThe sign signals with the size relation are matched with a peripheral circuit to realize the basic function of voltage monitoring.
The dynamic amplifier structure with the gain correction module of the above embodiment is suitable for use in various Integrated Circuit (IC) systems.
Although the present invention has been described in terms of a circuit for correcting gain of a dynamic amplifier against voltage fluctuation, it is not intended to limit the present invention, and those skilled in the art may make insubstantial changes or modifications without departing from the spirit of the present invention.

Claims (4)

1. The voltage detection and control circuit comprises a reference voltage output buffer module (402), a voltage operation module (403) and a comparator module (404),
the input end of the reference voltage output buffer module (402) is connected with a reference voltage, and the output end of the reference voltage output buffer module is connected with the second input end of the voltage operation module (403);
a first input end of the comparator module (404) is connected with an output end of the voltage operation module (403), a second input end of the comparator module is connected with a voltage to be detected, and an output end of the comparator module is used as an output end of the voltage detection and control circuit;
the voltage operation module (403) comprises a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), and a first capacitor (C)3) A first NMOS transistor (MN1), a second NMOS transistor (MN2), a first PMOS transistor (MP1) and a second PMOS transistor (MP2),
the source of the first PMOS transistor (MP1) is used as the first input end of the voltage operation module (403) to be connected with the external adjustment voltage, the grid thereof is connected with the output end of the first inverter (INV1), the drain thereof is connected with the drains of the first NMOS transistor (MN1) and the second PMOS transistor (MP2) and the first capacitor (C)3) The upper plate of (1);
the input end of the second inverter (INV2) is connected with the input end of the first inverter (INV1) and is connected with the external clock signal (clk), and the output end of the second inverter is connected with the grid electrode of the first NMOS transistor (MN 1);
the source of the second PMOS tube (MP2) is connected with the source of the first NMOS tube (MN1) and is used as the second input end of the voltage operation module (403), and the grid of the second PMOS tube is connected with the input end of the third inverter (INV3) and is connected with the external clock signal (clk);
the gate of the second NMOS transistor (MN2) is connected to the output terminal of the third inverter (INV3), and the drain thereof is connected to the first capacitor (C)3) And the lower polar plate of the voltage operation module (403) is used as the output end of the voltage operation module, and the source electrode of the voltage operation module is grounded.
2. The voltage detection and control circuit of claim 1, wherein the reference voltage output buffer module (402) comprises an operational amplifier, a first resistor (R1) and a third PMOS transistor (MP3),
the positive input end of the operational amplifier is connected with the reference voltage, the negative input end of the operational amplifier is connected with the drain electrode of the third PMOS tube (MP3) and one end of the first resistor (R1) and serves as the output end of the reference voltage output buffer module (402), the output end of the operational amplifier is connected with the grid electrode of the third PMOS tube (MP3), the source electrode of the third PMOS tube (MP3) is connected with the power supply voltage, and the other end of the first resistor (R1) is grounded.
3. The voltage detection and control circuit according to claim 1, wherein the comparator module (404) comprises a comparator (405), a negative input terminal of the comparator (405) is connected to the output terminal of the voltage operation module (403), a positive input terminal thereof is connected to the voltage to be detected, and an output terminal thereof is used as the output terminal of the voltage detection and control circuit.
4. The voltage detection and control circuit of claim 1, wherein the voltage value of the external regulated voltage is greater than the voltage value at the output of the reference voltage output buffer module (402).
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