CN108268239A - Multi-system arithmetic unit assigns meaning fractal algorithm circuit - Google Patents
Multi-system arithmetic unit assigns meaning fractal algorithm circuit Download PDFInfo
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Abstract
A kind of multi-system arithmetic unit assigns meaning fractal algorithm circuit and divides shape node by assigning meaning,Isolation circuit and hold meaning compiling array composition,The tax meaning point shape circuit is a circuit shunt node,It can assign and mean that arithmetic operator (adds,Subtract,Multiply,Except) and other operations,Arithmetic operator generally divides two-way,Carry all the way,One's own department or unit all the way,Carry and one's own department or unit are isolated respectively with conventional logic circuit or other elements,And NOT gate is inputted into common access and divides shape node,The output of NOT gate is entered by operational form holds meaning compiling array,The meaning compiling array that holds is made of multi-system position power line and isolation NOT gate output line,The multi-system position power line is divided to two groups,Into hyte and this hyte,Carry after parsing is isolated in the item number identical with the scale used of each group of line is connected with the output of one's own department or unit NOT gate by operation rule with the corresponding weight value line in carry-out bit power line,One label input, which resolves to carry and the similary label inputs of one's own department or unit two-way output, can resolve to other different a variety of outputs,The whereabouts connection specifically exported,Activation is according to parsing demand fixed pattern,Setting,Fixed point uses isolation output or compiling output.
Description
Technical field
The present invention relates to field of computer technology, specifically realize that one of underlying hardware of multivalue computer " transport by multi-system
It calculates device and assigns meaning fractal algorithm circuit "
Technical background
Computers all so far and its relevant digital display circuit are all two-values, and multivalue is calculated in spite of many excellent
Point, but because of the key hardware without supporting multi-value operation, so development is extremely slow, it may be said that and multivalue computer is particularly
The realization of decade computer is almost nil, and in light of this situation, it is real that the present invention proposes that a kind of simple and effective multivalue calculates
Circuit is applied to be particularly the effective ways of ten values calculating and be particularly the adding of ten values with two-value hardware realization multivalue, subtract, multiply, the calculation removed
Art operation and its Key Circuit of logical operation are called " quantization logic " and its circuit.
Invention content
" quantization logic " is that the label information generated after being quantified with analog information carries out logical operation as operator, is deduced,
The flogic system of judgement
Quantify the simple understanding of logic
The method that mark value continuous, fuzzy, after chaos information quantization carries out logical operation as input and output is just named
Quantization logic is done, realizes that the circuit of its operation is just called quantization logic circuit, then quantifies the input preamble part of logic circuit
Most of weights lines for being quantizer or being quantized.Postposition output par, c weighs line for quantization weight line or quantization width.
Quantization logic has used the basic thought of two-valued function and multi valued logic or even fuzzy logic, and with simple and effective
There is two-value orientation circuit to realize the Key Circuit of multivalue and its fuzzy logic so that be only limited to simple two in logic original paper
It is similary to form multivalue and its fuzzy logical operation circuit in the case of kind state, particularly quantify the compatible operation of logic
Fundamentally solve the problems, such as multi-value operation, deposit with the method for quantization deposit, so as to open computing device of new generation
Update level road.The bustling various operation method of quantization logic can provide effective hardware support to the development of artificial intelligence.
Quantify logic circuit for two-valued function circuit, structure is more complicated, but I believe that in ultra-large collection
Into under the support of circuit engineering, it can realize that performance is more than the machine of two-value computing device by being continuing effort to.
Quantifying logic circuit, there are two types of circuit implementing methods, and one kind is to be transported with amplitude weights as input/output information
" width power type quantifies logic circuit " calculated, another kind are that as input/output information, " position power type quantifies logic with position weight
Circuit ",
Can be " width power type " or " position power type " or " mixed type " in practice.
The numerical value representation method of position power type quantization logic
It is called position power table with one group of method that spatially position weight of the line of parallel arranged or point represents numerical values recited
Show method, position indication has the property that：
1, the quantity of spatial parallelism arranging line is identical with using magnitude carry system, and binary number is represented with two lines, three into
System represents with three lines ... quinary represents with five lines ... the decimal systems represent that N systems are represented with N line with ten lines.
2, the voltage on line is effective for high level, and low level or 0 level represent invalid.Vice versa.
3, uniquely there was only a line in one group of line at any time, remaining line is locked into invalid state for high level.
Quantifying the essential characteristic of logic is
1：It is that logic " state " and information " power " are detached first to quantify logic, and the combination form of logic ensures that logic is closed
Be is complete correct, and the weights of information are attached in logic state and not by logic state restrict, are believed with abundant displaying
Colourful combination performance relationship is ceased, this method actually people are using but are being the failure to detach, such as：Pick up certain
One analog information first has to detection with or without information (logic detection), then just evaluates and tests metric width weights.Obvious information
It is logic judgment to whether there is, and the magnitude of information is then numerical metric, and the meaning of the two is different.Once presentation of information " having " is patrolled
The state of collecting, i.e., to complete logical operation, and the colorful variation of information amplitude later is not limited by logic state " having ".
2：Operation is carried out using " having " "None" Information sign, " having " "None" Information sign is different from the high and low of two value informations
Information, most apparent difference is that two value informations take two logical symbols 0 and 1,0 of height to represent low, 1 represents high, and two kinds of shapes of height
State is both logic state and binary number value information, and quantifies logic and represent logic state, " having " and two with " having " and "None"
There is information in corresponding display position of height of value logic, and so as to show its scale numerical value weights, and "None" then shows that the position does not have
Information does not show weights, and information 0 and 1 is to represent information weights rather than logic state in logic is quantified, and 0 and 1 as with dividend right letter
Breath respectively have oneself occupy " weights line " or " range value ", indicate information when 0 with dividend right line increases, show the position have weights 0. in
It is that 0 bit line increases, it is 0 to show its information weights, and display is without information when which is lower.Not aobvious weights 0 rather than tradition meaning
Zero or low in justice.
3：The value of information is represented with range value and position power
With the amplification value of information carrier represent information state and weighted value method we width is made to weigh method, when information is any
The amplification value at quarter is just called width weights, and information is just called width weighted code in the list of all sample magnitude weights of certain period.
With the position weight of information carrier represent information state and numerical values recited method we position is made to weigh method, information
The weight of carrier any position is just called a weights, and the spatial information that position weights are rearranged by prescription order is just called position power
Code.
4：Quantization logic fetter by logical relation therefore has abundant operation relation and output, can be take greatly, take it is small,
Different value with, with value and, different value or together value or compared with, add, subtract, multiplication and division, many way of outputs such as side by side, different output sides
Method determines the different function of logic circuit.The different function of same circuit can judge that offer is efficiently various to the evaluation and test of information and sentence
Determine tool.
5：Quantization logic circuit does not need to the design of dedicated tandem circuit, with traditional logic circuit can simply, it is effective,
It is reliable to realize multi valued logic operation and multi-system arithmetic operator, particularly it is easy to modular circuit framework particularly suitable for working as
The implementation of modern large scale integrated circuit.
It is multi-system arithmetic operator device algorithm circuit that multi-system arithmetic unit of the present invention, which assigns meaning fractal algorithm circuit, due to quantization
The logical operation output of logic is " label " information, and " label " is a kind of information signal, it is therefore desirable to carry out assigning meaning point
Shape could generate specific meaning, so as to guide on operation result to determining output.
A kind of multi-system arithmetic unit assigns meaning fractal algorithm circuit by assigning meaning point shape node, isolation circuit and holding meaning compiling battle array
Row composition, a tax meaning point shape circuit is a circuit shunt node, can assign and mean arithmetic operator (add, subtract, multiplication and division) and its
Its operation, arithmetic operator generally divide two-way, all the way carry, all the way one's own department or unit, carry and one's own department or unit respectively with conventional logic circuit or its
Its element is isolated, and NOT gate is inputted common access and divides shape node, and the output of NOT gate is entered by operational form holds meaning compiling array,
The meaning compiling array that holds is made of multi-system position power line and isolation NOT gate output line, and multi-system position power line is divided to two
Group, into hyte and this hyte, the item number of each group of line and the scale identical that uses parsing is isolated after carry and one's own department or unit
NOT gate output is weighed the corresponding weight value line in line with carry-out bit by operation rule and is connected, and a label input resolves to carry and one's own department or unit
The similary label inputs of two-way output can resolve to other different a variety of outputs, the connection of the whereabouts that specifically exports, activate according to
Isolation output or compiling output are used according to parsing demand fixed pattern, setting, fixed point.
The whole for assigning meaning add operation is marked isolation output line caused by being parsed by imparting operation
Meaning and operation result are attached formed two-value with the weights line of corresponding carry-out bit power line and assign meaning point shape add operation
Circuit, the operation are to assign meaning two-value add operation, and add operation needs carry, and the output of two kinds of one's own department or unit is dividing shape node J
It is divided to shape and is isolated and generate two image outputs with identical information content, one is set as carry, and one is set as one's own department or unit, described
Connection be：It is 0 to mark a0b0 display input A weights, and input B weights are 0, and add operation 0+0=00, carry is 0, one's own department or unit
It is 0, a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, one's own department or unit that shape is divided to be isolated is exported
It is 0 that line, which is connected to labels a0b1 display input A weights on 0 weights line of one's own department or unit output weights line, and input B weights are 1, addition
Operation 0+1=01, carry are 0, one's own department or unit 1, point carry-out of shape isolation are connected to 0 weights line of carry-out weights line
On, point one's own department or unit output line of shape isolation is connected on 1 weights line of one's own department or unit output weights line；And so on.
The whole for assigning meaning multiplying is marked isolation output line caused by being parsed by imparting operation
Meaning and operation result are attached formed two-value with the weights line of corresponding carry-out bit power line and assign meaning point shape multiplying
Circuit.The operation is to assign meaning two-value multiplying, and multiplying needs carry, and the output of two kinds of one's own department or unit is dividing shape node J
It is divided to shape and is isolated and generate two outputs with identical information content, one is set as carry, and one is set as one's own department or unit, the company
It is connected in：It is 0 to mark a0b0 display input A weights, and input B weights are 0, and multiplying 0*0=0, carry is 0, and one's own department or unit is also 0,
A point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, one's own department or unit output line that shape is divided to be isolated is connected
It is 0 to be connected to labels a0b1 display input A weights on 0 weights line of one's own department or unit output weights line, and input B weights are 1, multiplying
0*1=0, carry are 0, one's own department or unit 0, and a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line,
One's own department or unit output line of point shape isolation is connected to 0 weights line of one's own department or unit output weights line；And so on.
The whole for assigning meaning add operation is marked isolation output line caused by being parsed by imparting operation
Meaning and operation result are attached formed three, four, five, six, seven, eight, nine with the weights line of corresponding carry-out bit power line
Value assigns meaning and divides shape adder operation circuit.
The whole for assigning meaning multiplying is marked isolation output line caused by being parsed by imparting operation
Meaning and operation result are attached formed three, four, five, six, seven, eight, nine with the weights line of corresponding carry-out bit power line
Value assigns meaning and divides shape multiplying operational circuit.
The whole for assigning meaning add operation is marked isolation output line caused by being parsed by imparting operation
Meaning and operation result are attached ten formed values with the weights line of corresponding carry-out bit power line and assign meaning point shape add operation
Circuit.
The whole for assigning meaning multiplying is marked isolation output line caused by being parsed by imparting operation
Meaning and operation result are attached ten formed values with the weights line of corresponding carry-out bit power line and assign meaning point shape multiplying
Circuit.
The whole for assigning meaning add operation is marked isolation output line caused by being parsed by imparting operation
Meaning and operation result are attached formed arbitrary value with the weights line of corresponding carry-out bit power line and assign meaning point shape addition fortune
Calculate circuit.
The whole for assigning meaning multiplying is marked isolation output line caused by being parsed by imparting operation
Meaning and operation result are attached formed arbitrary value with the weights line of corresponding carry-out bit power line and assign meaning point shape multiplication fortune
Calculate circuit.
The whole of the tax meaning operation is marked isolation output line caused by being parsed by the meaning for assigning operation
The arbitrary operation formed is attached with the weights line of corresponding carry-out bit power line and arbitrary value assigns meaning point shape with operation result
Computing circuit.
Based on the fundamental characteristics of quantization logic, multi-system arithmetic unit of the present invention is assigned meaning fractal algorithm circuit and is not limited by scale
System, is not also limited by operation method, can be designed to arbitrary scale, arbitrary operational form.
The present invention " multi-system arithmetic unit assigns meaning fractal algorithm circuit " and patent application " quantization logic circuit and its operation side
Method "." the output design and assignment method of multivalue quantizer "." multivalue register "." multi-system arithmetic unit marks generative circuit ".
" multi-system arithmetic operator device ".And patent and application 00105165.2.00105162.8.00105164.4.00102057.9.
Composition multi-system computer particularly decade computer Key Circuit together
Description of the drawings
The present invention is not limited by scale, the arithmetic circuity of two, three, four, five ... .N values is may be designed to, except defeated
The position power line number amount for entering output becomes outside the pale of civilization with different generate of scale, and operation basic structural unit is constant, for the sake of simple, only
Draw two, three, ten value circuit diagrams.
Fig. 1 is to assign meaning point shape two-value multiplication connection figure.
Fig. 2 is to assign meaning point shape two-value addition connection figure.
Fig. 3 is to assign meaning three value multiplication connection figure of point shape.
Fig. 4 is to assign meaning three value addition connection figure of point shape.
Fig. 5 is to assign meaning ten value multiplication connection figure of point shape.(connection of 100 tax meaning point shape nodes of J00 to J99 is only drawn in figure
Part tie point is gone out)
Fig. 6 is to assign meaning ten value addition connection figure of point shape.(connection of 100 tax meaning point shape nodes of J00 to J99 is only drawn in figure
Part tie point is gone out)
Embodiment
With reference to Fig. 1, the whole of two-value tax meaning multiplying is marked isolation output line caused by being parsed by imparting
The meaning and operation result of operation are attached formed a two-value tax meaning point shape with the weights line of corresponding carry-out bit power line and multiply
Method computing circuit.The operation is to assign meaning two-value multiplying, and multiplying needs carry, and the output of two kinds of one's own department or unit is dividing
Shape node J, which is divided to shape and is isolated, generates two outputs with identical information content, and one is set as carry, and one is set as one's own department or unit,
The connection is：
It is 0 to mark a0b0 display input A weights, and input B weights are 0, assign meaning multiplying 0*0=00, and carry is 0, this
Position is also 0, a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, one's own department or unit that shape is divided to be isolated
Output line is connected on 0 weights line of one's own department or unit output weights line.
It is 0 to mark a0b1 display input A weights, and input B weights are 1, assign meaning multiplying 0*1=00, and carry is 0, this
Position is 0, a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, dividing, one's own department or unit that shape is isolated is defeated
Outlet is connected on 0 weights line of one's own department or unit output weights line.
It is 1 to mark a1b0 display input A weights, and input B weights are 0, assign meaning multiplying 1*0=00, and carry is 0, this
Position is 0, a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, dividing, one's own department or unit that shape is isolated is defeated
Outlet is connected on 0 weights line of one's own department or unit output weights line.
It is 1 to mark a1b1 display input A weights, and input B weights are 1, assign meaning multiplying 1*1=01, and carry is 0, this
Position is 1, a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, dividing, one's own department or unit that shape is isolated is defeated
Outlet is connected on 1 weights line of one's own department or unit output weights line.
With reference to Fig. 2, the whole of two-value tax meaning add operation is marked isolation output line caused by being parsed by imparting
The meaning and operation result of operation are attached formed a two-value tax meaning point shape with the weights line of corresponding carry-out bit power line and add
Method computing circuit, the operation are to assign meaning two-value add operation, and add operation needs carry, and the output of two kinds of one's own department or unit is dividing
Shape node J, which is divided to shape and is isolated, generates two image outputs with identical information content, and one is set as carry, and one is set as this
Position, the connection are：
It is 0 to mark a0b0 display input A weights, and input B weights are 0, assign meaning add operation 0+0=00, and carry is 0, this
Position is also 0, a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, one's own department or unit that shape is divided to be isolated
Output line is connected on 0 weights line of one's own department or unit output weights line.
It is 0 to mark a0b1 display input A weights, and input B weights are 1, assign meaning add operation 0+1=01, and carry is 0, this
Position is 1, a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, dividing, one's own department or unit that shape is isolated is defeated
Outlet is connected on 1 weights line of one's own department or unit output weights line.
It is 1 to mark a1b0 display input A weights, and input B weights are 0, assign meaning add operation 1+0=01, and carry is 0, this
Position is 1, a point carry-out for shape isolation is connected on 0 weights line of carry-out weights line, dividing, one's own department or unit that shape is isolated is defeated
Outlet is connected on 1 weights line of one's own department or unit output weights line.
It is 1 to mark a1b1 display input A weights, and input B weights are 1, assign meaning add operation 1+1=10, and carry is 1, this
Position is 0, a point carry-out for shape isolation is connected on 1 weights line of carry-out weights line, dividing, one's own department or unit that shape is isolated is defeated
Outlet is connected on 0 weights line of one's own department or unit output weights line.
With reference to Fig. 3, Fig. 4, Fig. 5, Fig. 6, according to the above method, whole labels of the tax meaning add operation are solved
Isolation output line caused by analysis is carried out by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
Three, four, five, six, seven, eight, nine formed values of connection, ten values assign meaning and divide shape adder operation circuit.
With reference to Fig. 3, Fig. 4, Fig. 5, Fig. 6, according to the above method, whole labels of the tax meaning multiplying are solved
Isolation output line caused by analysis is carried out by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
Three, four, five, six, seven, eight, nine formed values of connection, ten values assign meaning and divide shape multiplying operational circuit.
Claims (10)
1. a kind of multi-system arithmetic unit assigns meaning fractal algorithm circuit by assigning meaning point shape node, isolation circuit and holding meaning compiling array
Composition；It is characterized in that：The tax meaning point shape circuit is a circuit shunt connecting node and isolating device, and the tax is anticipated
Operation rule is customized for setting, can assign and mean that arithmetic operator adds, subtracts, multiplication and division operation, taking big minimizing operation and other a variety of fortune
It calculates, complicated operation divides shape through repeatedly assigning meaning；The secondary tax meaning of the arithmetic operator generally divides two-way, all the way carry, all the way
One's own department or unit, carry and one's own department or unit form invalid isolation with conventional logic circuit or other components respectively, and by invalid isolating device
The common access of input divides shape node, and the output of invalid isolating device is entered by operational form holds meaning compiling array；Described holds meaning
The output line that compiling array is weighed line and invalid isolating device by multi-system position forms；The multi-system position power line is divided to two groups,
Into hyte and this hyte, the item number of each group of line is identical with the scale used；Carry and one's own department or unit after parsing is isolated is defeated
Go out and connected by operation rule with the corresponding weight value line in carry-out bit power line, a label input resolves to carry and one's own department or unit two-way is defeated
Go out；Similary label input can resolve to other different a variety of outputs, and the whereabouts specifically exported, connection, activation are according to solution
Analysis demand fixed pattern, setting, fixed point use isolation output or compiling output.
2. according to claim 1：Whole labels of described tax meaning add operation parsed caused by be isolated in vain it is defeated
Outlet is attached formed two-value by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
It assigns meaning and divides shape adder operation circuit, the operation is to assign meaning two-value add operation, and add operation needs carry, two kinds of one's own department or unit
Output generates two image outputs with identical information content shape node J is divided to be divided to shape and be isolated, and one is set as carry,
One is set as one's own department or unit, and the connection is：It is 0 to mark a0b0 display input A weights, and input B weights are 0, add operation 0+0=
00, carry is 0, and one's own department or unit is connected to a point carry-out for shape isolation on 0 weights line of carry-out weights line also for 0, dividing
One's own department or unit output line of shape isolation is connected on 0 weights line of one's own department or unit output weights line；It is 0 to mark a0b1 display input A weights, defeated
It is 1 to enter B weights, and add operation 0+1=01, carry is 0, one's own department or unit 1, and a point carry-out for shape isolation is connected to carry-out
On 0 weights line of weights line, point one's own department or unit output line of shape isolation is connected on 1 weights line of one's own department or unit output weights line；Successively
Analogize.
3. according to claim 1：Whole labels of described tax meaning multiplying parsed caused by be isolated in vain it is defeated
Outlet is attached formed two-value by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
It assigns meaning and divides shape multiplying operational circuit.The operation is to assign meaning two-value multiplying, and multiplying needs carry, two kinds of one's own department or unit
Output generates two outputs with identical information content shape node J is being divided to be divided to shape and be isolated, and one is set as carry, one
One's own department or unit is set as, the connection is：It is 0 to mark a0b0 display input A weights, and input B weights are 0, multiplying 0*0=00,
Carry is 0, and one's own department or unit is connected to a point carry-out for shape isolation on 0 weights line of carry-out weights line also for 0, dividing shape
One's own department or unit output line of isolation is connected on 0 weights line of one's own department or unit output weights line；It is 0 to mark a0b1 display input A weights, input
B weights are 1, and multiplying 0*1=00, carry is 0, one's own department or unit 0, and a point carry-out for shape isolation is connected to carry-out power
It is worth on 0 weights line of line, point one's own department or unit output line of shape isolation is connected on 0 weights line of one's own department or unit output weights line；Class successively
It pushes away.
4. according to claim 1：Claim 2：The whole of the tax meaning add operation is marked caused by being parsed
Invalid isolation output line is attached institute by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
Three, four, five, six, seven, eight, nine values of composition assign meaning and divide shape adder operation circuit.
5. according to claim 1：Claim 3：The whole of the tax meaning multiplying is marked caused by being parsed
Invalid isolation output line is attached institute by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
Three, four, five, six, seven, eight, nine values of composition assign meaning and divide shape multiplying operational circuit.
6. according to claim 1：Claim 2：The whole of the tax meaning add operation is marked caused by being parsed
Invalid isolation output line is attached institute by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
Ten values of composition assign meaning and divide shape adder operation circuit.
7. according to claim 1：Claim 3：The whole of the tax meaning multiplying is marked caused by being parsed
Invalid isolation output line is attached institute by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
Ten values of composition assign meaning and divide shape multiplying operational circuit.
8. according to claim 1：Claim 2：The whole of the tax meaning add operation is marked caused by being parsed
Invalid isolation output line is attached institute by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
The arbitrary value of composition assigns meaning and divides shape adder operation circuit.
9. according to claim 1：Claim 3：The whole of the tax meaning multiplying is marked caused by being parsed
Invalid isolation output line is attached institute by the meaning and operation result for assigning operation with the weights line of corresponding carry-out bit power line
The arbitrary value of composition assigns meaning and divides shape multiplying operational circuit.
10. according to claim 1：The whole of the tax meaning operation is marked invalid isolation output line caused by being parsed
By the meaning and operation result for assigning operation the arbitrary operation formed is attached with the weights line of corresponding carry-out bit power line
Meaning, which is assigned, with arbitrary value divides shape computing circuit.
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| CN115565656A (en) * | 2022-10-12 | 2023-01-03 | 广州智链科技有限公司 | Bidirectional doctor seeing recommendation algorithm based on artificial intelligence |
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| 金翊: "三值光计算机原理和结构", 《中国博士学位论文全文数据库 信息科技辑》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115565656A (en) * | 2022-10-12 | 2023-01-03 | 广州智链科技有限公司 | Bidirectional doctor seeing recommendation algorithm based on artificial intelligence |
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