CN108255420A - A kind of solid state disk buffer memory management method and solid state disk - Google Patents
A kind of solid state disk buffer memory management method and solid state disk Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
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Abstract
The invention discloses a kind of solid state disk buffer memory management method and solid state disks, it is characterized in that solid state disk caching is divided into multiple administrative units by 8KB for unit, each administrative unit is divided into the sub- memory management unit of 2 4KB units, and distribution number scale is set to record the assigned number of each administrative unit, external module is cached as unit of 4KB to caching management module application, and new sub- memory management unit is just distributed from new administrative unit when only having the distribution number of administrative unit to be 2 by application sequence.New buffer memory management method is introduced, cooperation concatenation module can improve the formation probability of 8KB Data FIS, and then realize the effect for promoting solid state disk read-write performance.
Description
Technical field
The present invention relates to solid state disk control technology, more particularly to a kind of solid state disk buffer memory management method and solid-state are hard
Disk.
Background technology
Controller design and firmware (FW) design of SATA SSD needs to follow ata interface agreement, and ATA agreements regulation is primary
Data frame information structure (the Data FIS- of command queue NCQ (Native Command Queuing) read write command data transmission
Data Frame Information Structure, abbreviation data packet) also suggestion is 8KB to maximum, because establishing data every time
The transmission of packet needs to consume the regular hour, so the data packet that single command is formed is fewer, caused by establishing data packet transmission
Time loss is fewer.Optimal situation is that each data packet of order is 8KB, data packet of the finishing touch less than 8KB
Except.
Flash translation layer (FTL) FTL (Flash Translation Layer) is used in the firmware design of current SATA SSD
The mapping mechanism of 4KB, natural caching management module are also the management and with chained list format management as unit of 4KB, in this way
Fairly simple practicality, if Fig. 1 is conventional cache management schematic diagram, what is safeguarded on logic chained list is the index of physical cache block
Value, caching Buffer management modules pluck next index value from logic chain table header every time, calculate the corresponding 4KB of the index value
The address of physical cache block is to applicant, and after applicant is using complete give back, caching management module is inversely counted according to caching block address
Corresponding index value is calculated, which is suspended to chained list tail portion.Due to ordering the strategy to reorder in firmware design, Shen at first
The cache blocks that please be gone out not necessarily preferentially transmit data with host, so also not ensuring that the cache blocks that priority requisition is gone out are excellent
First return to caching management module, i.e., the adjacent corresponding physical block address of index value is not necessarily physics on last logic chained list
Continuously, see logic index and the correspondence of physical block in Fig. 1, there are staggered cases.
In order to improve the number of 8KB Data FIS, increase a concatenation module in firmware, as shown in Fig. 2, 4KB
Buffer is first placed into concatenation module, is transmitted to SSD controller again after being combined into the Data FIS of 8KB by concatenation module trial, still
This technology is physically also continuous dependent on the continuous two 4KB buffer gone out from buffer module applications, but by
The strategy to reorder inside SSD in the presence of order, during SSD is run, index adjacent on logic chained list in buffer modules
Value differs, and to establish a capital be that physics is continuous, if this discontinuous probability is very big, then the effect of concatenation module is also little.
In order to ensure being combined into for 8KB Data FIS, the module of a splicing 8KB Data FIS exists in the prior art,
Fig. 2 is the data structure diagram increased after concatenation module, and the buffer block address sections for being committed to Data FISFIFO are first fed into spelling
Connection module decides whether to form Data FIS descriptors by concatenation module, which maintains following field：
1.start_addr：The buffer block initial addresses of caching.
2.end_addr：The buffer block end address of caching.
3.is_valid：Indicate whether valid cache.
Fig. 3 is the splicing flow chart of concatenation module, and it is as follows that concatenation module obtains the process flow after new buffer blocks：Judge
Whether is_valid has put, and is_valid has been put if not put, and juxtaposition start_addr is the starting of new buffer blocks
Address puts end_addr as the end address of new buffer blocks and terminates flow；Judge if is_valid has been put
Whether end_addr is equal to the initial address of new buffer blocks, the buffer cached before concatenation module is illustrated not equal to if
It is discontinuous with new buffer blocks, then the buffer cached before is formed Data FIS descriptors and brush SSD controller
Data FIS FIFO, then new buffer blocks are cached, that is, put the starting point that start_addr is new buffer blocks
Location puts end_addr as the end address of new buffer blocks and terminates flow；If end_addr is equal to new buffer blocks
New buffer blocks are then stitched together by initial address with the buffer cached before, that is, it is new buffer blocks to put end_addr
End address；Terminate flow if spliced buffer is not above 8KB, be otherwise cut into 8KB formation Data FIS and retouch
It states symbol to brush the Data FIS FIFO of SSD controller and record remaining buffer, i.e. start_addr increases 8KB；It is if new
Buffer blocks are not that the final stage buffer of order then terminates flow, otherwise form buffer remaining in concatenation module
Data FIS descriptors brush the Data FIS FIFO of SSD controller, remove is_valid and indicate and terminate flow.
By taking the example in Fig. 2 as an example, one is ordered the buffer for being assigned with six pieces of 4KB, wherein first piece is closed second piece not
Continuously, second piece and third block it is continuous, third block and the 4th piece are discontinuous, and the four, the 5th, the 6th pieces are continuous, they
Processing in concatenation module is as follows：
Step1：First piece of buffer enters concatenation module, it is found that is_valid is invalid, then set start_addr,
End_addr is the whole story address of first piece of buffer, and it is effective to put is_valid.
Step2：Second piece of buffer enters concatenation module, it is found that is_valid is effective, and end_addr is not equal to second
The initial address of block buffer, then first piece of formation Data FIS descriptor, then putting start_addr, end_addr is
The whole story address of second piece of buffer.
Step3：Third block buffer enters concatenation module, it is found that is_valid is effective, and end_addr is equal to third block
The initial address of buffer then merges the second third block buffer, that is, puts the end address that end_addr is third block buffer,
And the buffer cached at this time has expired 8KB, then preceding 8KB is formed Data FIS brushes away, and then residue buffer is 0, then puts
Is_valid is invalid.
Step4：4th piece of buffer enters concatenation module, it is found that is_valid is invalid, then set start_addr,
End_addr is the whole story address of the 4th piece of buffer, and it is effective to put is_valid.
Step5：5th piece of buffer enters concatenation module, it is found that is_valid is effective, and end_addr is equal to the 5th piece
The initial address of buffer then merges the four or five piece of buffer, that is, puts the end address that end_addr is the 5th piece of buffer,
And the buffer cached at this time has expired 8KB, then preceding 8KB is formed Data FIS brushes away, and then residue buffer is 0, then puts
Is_valid is invalid.
Step6：6th piece of buffer enters concatenation module, it is found that is_valid is invalid, then set start_addr,
End_addr is the whole story address of the 6th piece of buffer, and it is effective to put is_valid, and the finishing touch buffer that this is order,
Then the buffer in caching is formed Data FIS and brushed away by pressure.
It is corresponded in addition, the effect of the technology depends on buffer index values adjacent on buffer management module logic chained lists
Physics buffer it is whether continuous, if be all continuous, then the probability that concatenation module is combined into 8KB can reach percent
Hundred, so in order to which new technology is enable to play maximum effect, SSD needs (inside the does not handle host request) resetting during the free time
(Reset) buffer management modules, buffer index values pair adjacent on logic chained list in the buffer management modules after resetting
The physics buffer answered is continuous.
But SSD cannot arbitrarily reset buffer management modules during operation, otherwise firmware can malfunction.So run
The corresponding 4KB buffer physical address of index value adjacent on logic chained list is not necessarily continuously in period buffer module,
This limits the effect of concatenation module from source.
Invention content
For disadvantages described above, the present invention seeks to the present invention seeks to how reduce to establish caused by data packet is transmitted the time
Consumption.
The present invention proposes solid state disk buffer memory management method in order to solve problem above, it is characterised in that by solid state disk
Caching is divided into multiple administrative units by 8KB for unit, and each administrative unit is divided into the sub- memory management unit of 2 4KB units,
And distribution number scale is set to record the assigned number of each administrative unit, external module is as unit of 4KB to cache management mould
Block application caches, and just distributes new son from new administrative unit when only having the distribution number of administrative unit to be 2 by application sequence and delays
Deposit administrative unit.
The solid state disk buffer memory management method, it is characterised in that by the index of logic chained list, by continuous 2 ropes
Drawing value as a memory management unit, each memory management unit often distributes a sub- memory management unit, and distribution number adds 1,
When it is 2 to distribute number, which is removed from logic chained list.
The solid state disk buffer memory management method, it is characterised in that when having distributed two of the memory management unit used
When sub- memory management unit is all recovered, which is suspended to logic chained list tail portion.
The solid state disk buffer memory management method, it is characterised in that every time all from logic chain during application memory management unit
The gauge outfit of table starts to distribute memory management unit.
The solid state disk buffer memory management method, it is characterised in that in SSD controller with increasing in SSD caching management modules
Add concatenation module, continuous cache blocks are spliced into read command that the concatenation module issues host or the cache blocks of write order
The data packet of 8K sizes, and pass through the information of Packet Descriptor table description splicing, the DMA of the SSD controller is according to description
The data transmission that the information control of symbol table description reads or writes；A cache information, includes at least on the concatenation module cache blocks
Block initial address start_addr, the block tail address end_addr of a upper cache blocks and whether effective marker is_valid；Institute
It states concatenation module caching and receives a new cache blocks, by the block initial address start_addr of new cache blocks and upper one caching
The block tail address end_addr of block be compared judges whether it is continuous, if continuous by a upper cache blocks and new cache blocks into
Row splicing is spliced into the data packet of 8K sizes, and corresponding updated data package descriptor table data；The concatenation module is at least safeguarded
Following information：Block initial address start_addr, the block tail address end_addr of cache blocks and whether effective marker is_
valid；The caching block address for being submitted to data packet queue is first fed into the concatenation module, judges whether is_valid is set to
It rises, is_valid has been put if not put, juxtaposition start_addr is the initial address of new cache blocks, and putting end_addr is
The end address of new cache blocks simultaneously terminates this splicing；It is new to judge whether end_addr is equal to if is_valid has been put
The initial address of cache blocks, the caching cached before concatenation module is illustrated not equal to and if new cache blocks are discontinuous,
The caching cached before is then formed the data packet queue that Packet Descriptor table brushes SSD controller, then newcomer is cached
Block caches, that is, puts the initial address that start_addr is new cache blocks, puts the end address that end_addr is new cache blocks
And terminate flow；New cache blocks are spliced with the caching cached before if the initial address that end_addr is equal to new cache blocks
Get up, that is, put the end address that end_addr is new cache blocks；Terminate this spelling if spliced caching is not above 8KB
It connects, is otherwise cut into 8KB formation Data FIS descriptor tables and brushes the data packet queue of SSD controller and record remaining cache；
Terminate to splice if new cache blocks are not the final stage cachings of order, caching remaining in concatenation module is otherwise formed into number
The data packet queue of SSD controller is brushed according to packet descriptor table, is_valid is removed and indicates and terminate to splice；SSD is during idle time
Caching management module is reset, resetting, which is changed, deposits management module and delay the corresponding physics of the index value of cache blocks adjacent in logic chained list
Arrangement is deposited as continuous state.
A kind of solid state disk, it is characterised in that solid state disk caching is divided into multiple administrative units by 8KB for unit, often
A administrative unit is divided into the sub- memory management unit of 2 4KB units, and distribution number scale is set to record each administrative unit and is divided
The number matched, external module are cached as unit of 4KB to caching management module application, there was only point of administrative unit by application sequence
With number for 2 when just new sub- memory management unit is distributed from new administrative unit.
The solid state disk, it is characterised in that by the index of logic chained list, using continuous 2 index values as one
Memory management unit, each memory management unit often distribute a sub- memory management unit, and distribution number adds 1, when distribution number is 2
When, which is removed from logic chained list.
The solid state disk, it is characterised in that when two that have distributed the memory management unit used sub- cache management lists
When member is all recovered, which is suspended to logic chained list tail portion.
The solid state disk, it is characterised in that every time during application memory management unit all since the gauge outfit of logic chained list
Distribute memory management unit.
The beneficial effects of the invention are as follows：New buffer memory management method is introduced, cooperation concatenation module can improve 8KB Data
The formation probability of FIS, and then realize the effect for promoting solid state disk read-write performance.
Description of the drawings
Fig. 1 is conventional cache management schematic diagram；
Fig. 2 is the data structure diagram increased after concatenation module；
Fig. 3 is the splicing flow chart of concatenation module；
Fig. 4 is buffer module management schematic diagrames；
Fig. 5 is 8KB unit internal physical Address d istribution schematic diagrames.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment shall fall within the protection scope of the present invention.
Propose a kind of new buffer management methods so that the adjacent 4KB buffer applied away twice are physically
Location is continuous, and it according to 8KB is Single Component Management buffer that core concept, which is buffer modules, but external module also according to
4KB is unit application or returns to buffer, and Fig. 4 Fig. 4 is buffer module management schematic diagrames, in buffer module initializations,
The corresponding 4KB buffer of adjacent 4KB index values are physically continuous on logic chained list, then we are adjacent two
A 4KB index values provide an administrative unit, we it be referred to as 8KB administrative units, this 8KB administrative unit maintains a change
Amount：Number is distributed, represents the 4KB buffer numbers distributed in this 8KB unit.
The flow that buffer management modules externally distribute 4KB buffer is to check that the 8KB management of logic chain table header is single
Member, if its distribution number is 0, then distribute first 4KB buffer in the unit, then distribute number and add 1 and terminate stream
Otherwise journey distributes number one and is set to 1, then distribute second 4KB buffer in the unit, then distribute number and add 1, at this time
Distribute number centainly be equal to 2, illustrate that two in the unit 4KB are assigned away, then this 8KB administrative unit from
Logic linked list head is extractd and terminates flow.It can ensure two 4KB that continuous dispensing is gone out in same 8KB administrative units in this way
Buffer is physically continuous certainly.
The flow of buffer management modules recycling 4KB buffer is to calculate the corresponding 8KB pipes of 4KB buffer (divided by 2)
Unit is managed, and distributes number and subtracts 1, terminates flow if distribution number is equal to 1, otherwise distributes number and be centainly equal to 0, then by the 8KB
Administrative unit is suspended to logic chained list tail portion and terminates flow.It can ensure in this way on logic chained list in all 8KB administrative units
Two 4KB buffer are physically continuous.
During SSD is run, since the order of firmware is reordered, 4KB buffer are not necessarily returned according to the sequence dispensed
It returns, 8KB unit management technologys, it is impossible to ensure that the corresponding physics buffer addresses of adjacent 8KB units are continuous on logic chained list, but
It can ensure that two inside 8KB units 4KB buffer are that physics is continuous forever, Fig. 5 is 8KB unit internal physicals address point
Cloth schematic diagram, in this way, an order is surely combined into the Data FIS of 8KB in addition to the 4KB on head and tail portion differs, it is intermediate
Data FIS are certainly 8KB, and readwrite performance will greatly promote.
Or by taking the example in Fig. 2 as an example, an order needs to distribute the buffer of six pieces of 4KB, buffer management modules
Distribute buffer the step of be：
Distribute first piece of buffer：Buffer management modules check first 8KB administrative unit of logic linked list head, find to divide
It is 0 with number, then distributes first 4KB buffer in the 8KB administrative units and distribution number adds 1.
Distribute second piece of buffer：Buffer management modules check first 8KB administrative unit of logic linked list head, find to divide
It is 1 with number, then distributes second 4KB buffer in the 8KB administrative units and distribution number adds 1, then the 8KB is managed single
Member is extractd from logic chained list.
Distribute third block buffer：Buffer management modules check first 8KB administrative unit of logic linked list head, find to divide
It is 0 with number, then distributes first 4KB buffer in the 8KB administrative units and distribution number adds 1.
Distribute the 4th piece of buffer：Buffer management modules check first 8KB administrative unit of logic linked list head, find to divide
It is 1 with number, then distributes second 4KB buffer in the 8KB administrative units and distribution number adds 1, then the 8KB is managed single
Member is extractd from logic chained list.
Distribute the 5th piece of buffer：Buffer management modules check first 8KB administrative unit of logic linked list head, find to divide
It is 0 with number, then distributes first 4KB buffer in the 8KB administrative units and distribution number adds 1.
Distribute the 6th piece of buffer：Buffer management modules check first 8KB administrative unit of logic linked list head, find to divide
It is 1 with number, then distributes second 4KB buffer in the 8KB administrative units and distribution number adds 1, then the 8KB is managed single
Member is extractd from logic chained list.
Above disclosed is only an embodiment of the present invention, cannot limit the interest field of sheet with this certainly,
One of ordinary skill in the art will appreciate that realize all or part of flow of above-described embodiment, and according to the claims in the present invention institute
The equivalent variations of work still fall within the range that the present invention is covered.
Claims (10)
1. a kind of solid state disk buffer memory management method, it is characterised in that by solid state disk caching by 8KB for unit be divided into it is multiple
Administrative unit, each administrative unit are divided into the sub- memory management unit of 2 4KB units, and set each management of distribution number scale record
The assigned number of unit, external module are cached to caching management module application as unit of 4KB, only had by application sequence
New sub- memory management unit is just distributed from new administrative unit when the distribution number of administrative unit is 2.
2. solid state disk buffer memory management method according to claim 1, it is characterised in that, will by the index of logic chained list
For continuous 2 index values as a memory management unit, each memory management unit often distributes a sub- memory management unit,
Distribution number adds 1, and when it is 2 to distribute number, which is removed from logic chained list.
3. solid state disk buffer memory management method according to claim 1, it is characterised in that when having distributed the caching pipe that uses
When two sub- memory management units of reason unit are all recovered, which is suspended to logic chained list tail portion.
4. solid state disk buffer memory management method according to claim 2, it is characterised in that apply for memory management unit every time
The gauge outfit of Shi Doucong logic chained lists starts to distribute memory management unit.
5. solid state disk buffer memory management method according to any one of claims 1 to 4, it is characterised in that controlled in SSD
Increase concatenation module in device and SSD caching management modules, read command that the concatenation module issues host or write order it is slow
Continuous cache blocks are spliced into the data packet of 8K sizes in counterfoil, and pass through the information of Packet Descriptor table description splicing, institute
State the data transmission that the information control that the DMA of SSD controller is described according to descriptor table reads or writes；The concatenation module cache blocks
A upper cache information, including at least the block initial address start_addr of a upper cache blocks, block tail address end_addr and
Whether effective marker is_valid；The concatenation module caching receives a new cache blocks, by the block starting point of new cache blocks
The block tail address end_addr of location start_addr and a upper cache blocks, which is compared, to be judged whether continuously, will if continuous
A upper cache blocks and new cache blocks are spliced, and are spliced into the data packet of 8K sizes, and corresponding updated data package descriptor table
Data；The concatenation module at least safeguards following information：Block initial address start_addr, the block tail address end_ of cache blocks
Addr and whether effective marker is_valid；The caching block address for being submitted to data packet queue is first fed into the splicing mould
Block, judges whether is_valid has been set to, and is_valid has been put if not put, and juxtaposition start_addr is new cache blocks
Initial address, put end_addr be new cache blocks end address and terminate this splicing；If is_valid has been put
Then judge whether end_addr is equal to the initial address of new cache blocks, what is cached before concatenation module is illustrated not equal to if is slow
It deposits discontinuous with new cache blocks, then the caching cached before is formed the number that Packet Descriptor table brushes SSD controller
It is cached according to packet queue, then new cache blocks, that is, puts the initial address that start_addr is new cache blocks, put end_
Addr is the end address of new cache blocks and terminates flow；To newly it delay if the initial address that end_addr is equal to new cache blocks
Counterfoil is stitched together with the caching cached before, that is, puts the end address that end_addr is new cache blocks；It is if spliced slow
It deposits and is not above 8KB and then terminates this splicing, be otherwise cut into 8KB and form the number that DataFIS descriptor tables brush SSD controller
According to packet queue and record remaining cache；Terminate to splice if new cache blocks are not the final stage cachings of order, otherwise will spell
Remaining caching forms the data packet queue that Packet Descriptor table brushes SSD controller in connection module, removes is_valid marks
Will simultaneously terminates to splice；SSD resets caching management module during idle time, resetting change deposit management module will be adjacent slow in logic chained list
The corresponding physical cache of index value of counterfoil is arranged as continuous state.
6. a kind of solid state disk, it is characterised in that solid state disk caching is divided into multiple administrative units by 8KB for unit, each
Administrative unit is divided into the sub- memory management unit of 2 4KB units, and it is assigned that distribution number scale is set to record each administrative unit
Number, external module as unit of 4KB to caching management module application cache, there was only the distribution of administrative unit by application sequence
New sub- memory management unit is just distributed from new administrative unit when number is 2.
7. solid state disk according to claim 6, it is characterised in that by the index of logic chained list, by continuous 2 ropes
Drawing value as a memory management unit, each memory management unit often distributes a sub- memory management unit, and distribution number adds 1,
When it is 2 to distribute number, which is removed from logic chained list.
8. solid state disk according to claim 6, it is characterised in that when having distributed two of the memory management unit used
When sub- memory management unit is all recovered, which is suspended to logic chained list tail portion.
9. solid state disk according to claim 7, it is characterised in that every time all from logic chain during application memory management unit
The gauge outfit of table starts to distribute memory management unit.
10. according to the solid state disk described in claim 6 to 9 any one, it is characterised in that cached in SSD controller and SSD
Increase concatenation module in management module, it is continuous in read command that the concatenation module issues host or the cache blocks of write order
Cache blocks are spliced into the data packet of 8K sizes, and pass through the information of Packet Descriptor table description splicing, the SSD controller
The data transmission that the information control that DMA is described according to descriptor table reads or writes；A caching letter on the concatenation module cache blocks
Breath, including at least the block initial address start_addr of a upper cache blocks, block tail address end_addr and whether effective marker
is_valid；
The concatenation module caching receives a new cache blocks, by the block initial address start_addr of new cache blocks and upper one
The block tail address end_addr of a cache blocks, which is compared, to be judged whether continuously, slow by a upper cache blocks and newly if continuous
Counterfoil is spliced, and is spliced into the data packet of 8K sizes, and corresponding updated data package descriptor table data；The concatenation module is extremely
Following information is safeguarded less：Block initial address start_addr, the block tail address end_addr of cache blocks and whether effective marker is_
valid；
The caching block address for being submitted to data packet queue is first fed into the concatenation module, judges whether is_valid is set to
It rises, is_valid has been put if not put, juxtaposition start_addr is the initial address of new cache blocks, and putting end_addr is
The end address of new cache blocks simultaneously terminates this splicing；It is new to judge whether end_addr is equal to if is_valid has been put
The initial address of cache blocks, the caching cached before concatenation module is illustrated not equal to and if new cache blocks are discontinuous,
The caching cached before is then formed the data packet queue that Packet Descriptor table brushes SSD controller, then newcomer is cached
Block caches, that is, puts the initial address that start_addr is new cache blocks, puts the end address that end_addr is new cache blocks
And terminate flow；New cache blocks are spliced with the caching cached before if the initial address that end_addr is equal to new cache blocks
Get up, that is, put the end address that end_addr is new cache blocks；
Terminate this splicing if spliced caching is not above 8KB, be otherwise cut into 8KB and form Data FIS descriptors
Table brushes the data packet queue of SSD controller and records remaining cache；If new cache blocks are not the final stage cachings of order
Then terminate to splice, caching remaining in concatenation module is otherwise formed into the data packet that Packet Descriptor table brushes SSD controller
Queue removes is_valid and indicates and terminate to splice；
SSD resets caching management module during idle time, and resetting, which is changed, deposits management module by the rope of cache blocks adjacent in logic chained list
Draw the corresponding physical cache of value to arrange as continuous state.
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| CN112486852A (en) * | 2020-12-01 | 2021-03-12 | 合肥大唐存储科技有限公司 | Solid state disk and address mapping method thereof |
| WO2021218101A1 (en) * | 2020-04-26 | 2021-11-04 | 北京泽石科技有限公司 | Solid-state hard disk cache management system, method, and apparatus |
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