CN108234252B - Multi-path Ethernet communication system - Google Patents
Multi-path Ethernet communication system Download PDFInfo
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- CN108234252B CN108234252B CN201611196492.1A CN201611196492A CN108234252B CN 108234252 B CN108234252 B CN 108234252B CN 201611196492 A CN201611196492 A CN 201611196492A CN 108234252 B CN108234252 B CN 108234252B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/2854—Wide area networks, e.g. public data networks
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Abstract
The invention provides a multipath Ethernet communication system, comprising: each physical interface transceiver is connected to a corresponding network interface; and N controllers integrated on the FPGA chip; the N controllers are connected with the N physical interface transceivers in a one-to-one correspondence manner; wherein, the controller includes: the sending unit is used for reading the communication data from the external memory and forwarding the communication data to a network through a physical interface transceiver corresponding to the communication data; and the receiving unit is used for receiving the communication data from the network through the corresponding physical interface transceiver, processing the received communication data into the communication data meeting the requirement of the external memory, and writing the communication data meeting the requirement of the external memory into the external memory. The invention realizes the MAC interface through the input and output interface inside the FPGA, and has stronger practical application capability because the FPGA can realize the flexibility of any circuit.
Description
Technical Field
The invention belongs to the technical field of network communication, relates to a communication system, and particularly relates to a multi-path Ethernet communication system.
Background
Ethernet is the most common communication protocol standard used in local area networks today and has wide application in a variety of fields. Gigabit ethernet is a technology built on the underlying ethernet standard. Gigabit ethernet and the heavily used ethernet are fully compatible with fast ethernet and utilize all the specifications specified by the original ethernet standard.
With the development of the internet and intranet, the mode of network communication has existed in the interior of a work group or department from the past 80% of traffic (only 20% of traffic is on the backbone), and the network communication is rapidly expanded to bear 80% of network traffic on the backbone, and only 20% of traffic still exists in the interior of the work group or department. This poses a challenge to the communications capabilities of the backbone network and the rise of gigabit ethernet networks is accommodating this development.
The gigabit Ethernet scheme in the prior art is a structure of an MAC chip, a PHY chip, a network port and a transformer, although the structure is fixed, each path of Ethernet needs one MAC chip and one path of PHY chip under the condition of realizing multipath Ethernet, and the problems of complicated design, cost increase and the like caused by the fact that the constraint of the MAC chip cannot be got rid of are solved.
Therefore, how to provide a multi-path ethernet communication system to solve the defects of the prior art that each path of ethernet needs one MAC plus one PHY chip and cannot get rid of the constraint of the MAC chip, which results in complicated design and increased cost, has become a technical problem to be solved by practitioners in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a multi-path ethernet communication system, which is used to solve the problems that in the prior art, when multiple paths of ethernet are implemented, each path of ethernet needs one MAC plus one PHY chip, and cannot get rid of the constraint of the MAC chip, which results in a complicated design and increased cost.
To achieve the above and other related objects, the present invention provides a multi-path ethernet communication system connected to an external memory, comprising: n physical interface transceivers, wherein N is greater than or equal to 2; each path of physical interface transceiver is connected to a corresponding network interface; and N controllers integrated on the FPGA chip; the N controllers are connected with the N physical interface transceivers in a one-to-one correspondence manner; wherein the controller includes: the sending unit is used for reading the communication data from the external memory and forwarding the communication data to a network through a physical interface transceiver corresponding to the communication data; and the receiving unit is used for receiving the communication data from the network through the physical interface transceiver corresponding to the receiving unit, processing the received communication data into the communication data meeting the requirement of the external memory, and writing the communication data meeting the requirement of the external memory into the external memory.
In an embodiment of the present invention, the controller further includes: and the monitoring unit is connected with the sending unit and the receiving unit and is used for monitoring the sending state information and the receiving state information of the communication data in the process of sending and receiving the communication data.
In an embodiment of the present invention, the transmission status information of the communication data includes exceeding a retry limit value, a transmission delay collision time, and/or a transmission delay time; the reception status information of the communication data includes a reception error or invalidity, a late collision signal, a frame length abnormality, and/or reception overflow data.
In an embodiment of the present invention, the controller further includes: and the independent management interface is connected with the sending unit and the receiving unit and is used for negotiating the transmission rate with the physical interface transceiver and determining the working mode of inputting the communication data into the medium physical interface transceiver and/or outputting the communication data into the external memory.
In an embodiment of the present invention, the independent management interface includes: a clock generating section for generating a clock signal of the independent management interface; a shift register for converting the parallel communication data transmitted by the transmission unit into serial communication data, writing the serial communication data into the medium physical interface transceiver, and converting the serial communication data read from the medium physical interface transceiver into parallel communication data; an input/output control section for determining whether communication data is in an output state or an input state so that the shift register performs a write operation and a read operation.
In an embodiment of the present invention, the sending unit is further configured to receive a start flag and an end flag of communication data, package the start flag and the end flag of the communication data and read the communication data from the external memory, and send the packaged communication data to the network through the independent management interface when a network channel of the network is in an idle state according to a carrier sense signal and a collision detection signal provided by a physical interface transceiver corresponding to the carrier sense signal and the collision detection signal.
In an embodiment of the present invention, the receiving unit is further configured to convert parallel communication data sent by the independent management interface into byte data, perform address detection, CRC check, and protocol judgment on the byte data, and send the communication data meeting the requirement of the external memory to the external memory.
In an embodiment of the present invention, the controller further includes: the data control unit is connected with the sending unit and the receiving unit and is used for controlling the sending unit to send the communication data; and controlling the reception of the communication data by the reception unit.
In an embodiment of the present invention, the data control unit includes: a transmission control unit configured to control the communication data transmitted by the transmission unit when receiving a control request for controlling transmission of the communication data transmitted by the independent management interface; and a reception control unit configured to control the communication data received by the receiving unit when a control reception request for communication data transmitted from the independent management interface is received.
As described above, the multi-path ethernet communication system of the present invention has the following advantages:
the multi-path Ethernet communication system realizes the MAC interface through the input and output interface inside the FPGA, and has obvious advantages in multi-path Ethernet communication because the FPGA can realize the flexibility of any circuit and can realize any number of MAC interfaces under the condition that the number of I/O ports of the FPGA is not exceeded. The whole scheme is flexible and changeable, the communication is stable, the multi-path gigabit Ethernet communication can be performed in parallel, and the practical application capability is strong.
Drawings
Fig. 1 is a schematic diagram illustrating a schematic structure of a multi-path ethernet communication system according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of the controller of the present invention.
Description of the element reference numerals
1 multipath Ethernet communication system
11 controller
12 physical interface transceiver
13 network interface
14 network transformer
111 transmitting unit
112 receiving unit
113 monitoring unit
114 data control unit
115 media independent interface
121 supply circuit
122 clock circuit
123 filter circuit
2 FPGA chip
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a multi-path Ethernet communication system which comprises a sending unit, a receiving unit, a monitoring unit, a data control unit and a medium independent interface, wherein the sending unit and the receiving unit provide the sending and receiving functions of an MAC frame, including frame encapsulation and unpacking, error detection and the like. The data control unit is used for executing the flow control function in the full duplex mode. The monitoring unit is used for monitoring the operation process of the MAC. The media independent interface provides a standard IEEE 802.3 Media Independent Interface (MII) for interfacing with an ethernet PHY. The operating rate may be negotiated with the PHY and the operating mode of the PHY set (full duplex or half duplex).
Examples
This embodiment provides a multi-path ethernet communication system, connected to an external memory, including:
n physical interface transceivers, wherein N is greater than or equal to 2;
each path of physical interface transceiver is connected to a corresponding network interface; and
n controllers integrated on the FPGA chip; the N controllers are connected with the N physical interface transceivers in a one-to-one correspondence manner;
wherein the controller includes:
the sending unit is used for reading the communication data from the external memory and forwarding the communication data to a network through a physical interface transceiver corresponding to the communication data;
and the receiving unit is used for receiving the communication data from the network through the physical interface transceiver corresponding to the receiving unit, processing the received communication data into the communication data meeting the requirement of the external memory, and writing the communication data meeting the requirement of the external memory into the external memory.
The multi-path ethernet communication system according to the present embodiment will be described in detail with reference to the drawings. In this embodiment, the multi-path ethernet communication system is communicatively coupled to an external memory and a network. Please refer to fig. 1, which is a schematic structural diagram of a multi-path ethernet communication system in an embodiment. As shown in fig. 1, the multi-path ethernet communication system 1 includes N controllers 11 integrated on an FPGA chip 2, N physical interface transceivers 12(PHA chips) connected to the N controllers 11 in a one-to-one correspondence, each physical interface transceiver 12 connected to a corresponding network interface 13, and a network transformer 14. Wherein N is greater than or equal to 2.
Please refer to fig. 2, which is a schematic diagram of the controller. As shown in fig. 2, the controller 11 includes a transmitting unit 111, a receiving unit 112, a monitoring unit 113, a data control unit 114, and a media independent interface 115.
The sending unit 111 is configured to read the communication data from the external memory, and forward the communication data to the network through the physical interface transceiver corresponding to the communication data. Specifically, the sending unit 111 receives the start flag and the end flag of the communication data from the external memory, reads the communication data, packages the start flag and the end flag of the communication data, and reads the communication data from the external memory, and sends the packaged communication data to the network through the independent management interface 115 in a width of half byte (four bits) via the corresponding physical interface transceiver 12 when the network channel of the network is in an idle state according to the carrier sense signal and the collision detection signal provided by the corresponding physical interface transceiver.
The receiving unit 112 is configured to receive serial communication data from the network via the corresponding physical interface transceiver 12, convert the serial communication data into parallel data with a width of half a byte, process the received communication data into communication data meeting the requirement of the external memory, and write the communication data meeting the requirement of the external memory into the external memory. Specifically, the receiving unit 112 converts parallel communication data sent by the independent management interface into byte data, performs address detection, CRC check, protocol judgment, and the like on the byte data, sends the communication data meeting the requirements of the external memory to the external memory, and records related information of a data frame in a receiving queue.
The monitoring unit 113 connected to the transmitting unit 111 and the receiving unit 112 is used for monitoring the transmitting status information and the receiving status information of the communication data during the process of transmitting and receiving the communication data. In this embodiment, the monitoring unit 113 monitors various transmission status information and reception status information of the communication data during the transmission and reception of the communication data by the transmitting unit 111 and the receiving unit 112, and writes the various transmission status information and reception status information into corresponding shift registers in the media independent interface 115 after the tape operation is completed. In the present embodiment, the transmission status information of the communication data includes an excess retry limit value, a transmission delay time, and/or a transmission delay time, and the like, wherein the excess retry limit value means that the number of retries due to collision exceeds a rated value. The transmission delay collision time means that a collision signal detected during transmission exceeds a prescribed time. The transmission delay time refers to a time of delaying transmission of communication data due to detection of busy of a network channel before transmission of the communication data. The reception status information of the communication data includes a reception error or invalidity, a late collision signal indicating that a reception process detected a late collision signal, a frame length abnormality, and/or reception overflow data, and the like. The frame length exception is that the received data frame is larger than the frame length of the maximum data frame or smaller than the frame length of the minimum data frame. Receiving overflow data is the time that the receiving unit has not been ready to process the received communication data.
A data control unit 114 connected to the transmitting unit and the receiving unit, for controlling the transmission of the communication data by the transmitting unit 111; and controls the reception of communication data by the reception unit 112. In this embodiment, the data control unit 114 includes:
and a transmission control unit configured to control the communication data transmitted by the transmission unit when receiving a control request for controlling transmission of the communication data transmitted by the independent management interface. Specifically, when the host interface is not in time to process the received data, a control request is sent to the MAC control module, and after receiving the control request, the MAC sends a control frame to a control frame dedicated address or an MAC address of a destination terminal by sending the control frame to the control frame dedicated address or the MAC address of the destination terminal, so that the sending is suspended; the control request is processed after the sending control module sends the current frame, so that the data transmission process is not interrupted.
And a reception control unit for controlling the communication data received by the receiving unit when a control reception request for the communication data transmitted from the independent management interface is received. Specifically, when the reception control section detects a control request, the status notification MAC is set, and the timer is set according to the parameter of the control frame. The transmitting unit 111 transmits data only after the timer is decremented to 0, and sets the timer at a reset parameter if there is a new control frame during the timer counting (cancels the pause in advance if the new timing parameter is 0).
The media independent interface 115 connected to the transmitting unit 111 and the receiving unit 112 is used to negotiate a transmission rate with the physical interface transceiver 12 and determine to input communication data to the media physical interface transceiver and/or to output communication data to an external memory. Specifically, the media independent interface 115 includes:
the clock generation section is configured to generate a clock signal of the independent management interface 115 according to a system clock and a frequency division coefficient in a system setting. For example, the external 25MHz crystal oscillator in the present system is used as a reference clock signal, and the frequency division and multiplication are used to generate the giga clock signal of 125 MHz.
The shift register is used for converting the parallel communication data sent by the sending unit into serial communication data, writing the converted serial communication data into the medium physical interface transceiver, and converting the serial communication data read from the medium physical interface transceiver into the parallel communication data when reading the state information of the PHY.
The input/output control section is used to determine whether communication data is in an output state or an input state so that the shift register performs a write operation and a read operation. Specifically, when the communication data is in an output state, the serial communication data output by the shift register is sent to the PHY12 after being clock-synchronized; when the communication data is in an input state, the shift register converts serial data on the data lines into parallel data.
In the present embodiment, each of the controllers 11 includes the above-mentioned transmitting unit 111, receiving unit 112, monitoring unit 113, data control unit 114, and media independent interface 115. The MAC chip is replaced by the controller 11.
In this embodiment, the gigabit PHY chip 12 includes three sets of power supply circuits 121, 25MHz clock circuits 122, and filter circuits 123, 1.0V, 1.8V, and 3.3V. The 25M clock circuit provides a reference clock for the gigabit PHY chip, and the PHY chip generates 125M clock to provide clock for gigabit Ethernet communication.
Each gigabit network interface 13 is matched with a network transformer 14, and the network transformers can realize electrical isolation, eliminate noise and improve communication stability.
In summary, the multi-path ethernet communication system of the present invention implements the MAC interface through the input/output interface inside the FPGA, and as the FPGA can implement any circuit flexibility, any number of MAC interfaces can be implemented without exceeding the number of I/O ports of the FPGA, which has obvious advantages in multi-path ethernet communication. The whole scheme is flexible and changeable, the communication is stable, the multi-path gigabit Ethernet communication can be performed in parallel, and the practical application capability is strong. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (5)
1. A multi-path ethernet communication system connected to an external memory, comprising:
n physical interface transceivers, wherein N is greater than or equal to 2;
each path of physical interface transceiver is connected to a corresponding network interface; and
n controllers integrated on the FPGA chip; the N controllers are connected with the N physical interface transceivers in a one-to-one correspondence manner;
wherein the controller includes:
the sending unit is used for reading the communication data from the external memory and forwarding the communication data to a network through a physical interface transceiver corresponding to the communication data;
a receiving unit, configured to receive communication data originating from the network via a physical interface transceiver corresponding thereto, process the received communication data into communication data that meets the requirement of the external memory, and write the communication data that meets the requirement of the external memory into the external memory;
the monitoring unit is used for monitoring the sending state information and the receiving state information of the communication data in the process of sending and receiving the communication data; the transmission state information of the communication data includes an excess retry limit value, a transmission delay collision time, and/or a transmission delay time, wherein the excess retry limit value means that the number of retries due to collision exceeds a rated value; the transmission delay collision time means that a collision signal detected in the transmission process exceeds a prescribed time; the transmission delay time refers to a time of delaying transmission of communication data due to detection of busy of a network channel before transmission of the communication data; the receiving state information of the communication data comprises receiving error or ineffectiveness, a lag conflict signal, frame length abnormity and/or receiving overflow data, wherein the lag conflict signal means that a receiving process detects the lag conflict signal; the frame length abnormity is that the received data frame is larger than the frame length of the maximum data frame or smaller than the frame length of the minimum data frame; receiving overflow data as communication data which is not available for the receiving unit to process;
a data control unit connected to the transmitting unit and the receiving unit, the data control unit including:
a transmission control unit configured to control the communication data transmitted by the transmission unit when receiving a control request for controlling transmission of the communication data transmitted by an independent management interface; when the host interface is not in time to process the received data, a control request is sent to the independent management interface, and after the control request is received, a control frame is sent to a special address of the control frame or an MAC address of a destination end by a sending control part to pause the sending; the control request is processed after the sending control part sends the current frame so as not to interrupt the data transmission process;
a reception control unit configured to control the communication data received by the receiving unit when receiving a control request for controlling reception of the communication data transmitted by the independent management interface; when the receiving control part detects a control request, setting a state notification MAC and setting a timer according to the parameters of a control frame; the transmitting unit transmits data only after the timer is decremented to 0, and sets the timer according to the reset parameter if there is a new control frame during the counting of the timer.
2. The multi-lane ethernet communication system according to claim 1, wherein:
the data control unit is used for negotiating the transmission rate with the physical interface transceiver; the independent management interface determines an operating mode for inputting communication data to the media physical interface transceiver and/or outputting communication data to the external memory.
3. The multi-lane ethernet communication system according to claim 2, wherein: the independent management interface includes:
a clock generating section for generating a clock signal of the independent management interface;
a shift register for converting the parallel communication data transmitted by the transmission unit into serial communication data, writing the serial communication data into the medium physical interface transceiver, and converting the serial communication data read from the medium physical interface transceiver into parallel communication data;
an input/output control section for determining whether communication data is in an output state or an input state so that the shift register performs a write operation and a read operation.
4. The multi-lane ethernet communication system according to claim 3, wherein: the sending unit is further configured to receive a start flag and an end flag of communication data, package the start flag and the end flag of the communication data, read the communication data from the external memory, and send the packaged communication data to the network through the independent management interface when a network channel of the network is in an idle state according to a carrier sense signal and a collision detection signal provided by a physical interface transceiver corresponding to the carrier sense signal and the collision detection signal.
5. The multi-lane ethernet communication system according to claim 3, wherein: the receiving unit is further configured to convert the parallel communication data sent by the independent management interface into byte data, perform address detection, CRC check, and protocol judgment on the byte data, and send the communication data meeting the requirement of the external memory to the external memory.
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| CN105262789A (en) * | 2015-09-08 | 2016-01-20 | 天津光电聚能专用通信设备有限公司 | FPGA (Field Programmable Gate Array)-based MAC (Media Access Control) layer to MAC layer communication system and control method |
| CN105406998A (en) * | 2015-11-06 | 2016-03-16 | 天津津航计算技术研究所 | Dual-redundancy gigabit ethernet media access controller IP core based on FPGA |
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| US6651107B1 (en) * | 1999-09-21 | 2003-11-18 | Intel Corporation | Reduced hardware network adapter and communication |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105262789A (en) * | 2015-09-08 | 2016-01-20 | 天津光电聚能专用通信设备有限公司 | FPGA (Field Programmable Gate Array)-based MAC (Media Access Control) layer to MAC layer communication system and control method |
| CN105406998A (en) * | 2015-11-06 | 2016-03-16 | 天津津航计算技术研究所 | Dual-redundancy gigabit ethernet media access controller IP core based on FPGA |
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