CN108199711A - A kind of expansible multiphase clock generation system and method - Google Patents
A kind of expansible multiphase clock generation system and method Download PDFInfo
- Publication number
- CN108199711A CN108199711A CN201711463570.4A CN201711463570A CN108199711A CN 108199711 A CN108199711 A CN 108199711A CN 201711463570 A CN201711463570 A CN 201711463570A CN 108199711 A CN108199711 A CN 108199711A
- Authority
- CN
- China
- Prior art keywords
- clock
- phase
- register
- clock unit
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 9
- 230000000630 rising effect Effects 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000013461 design Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000005070 sampling Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1077—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the phase or frequency detection means
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
This application discloses a kind of expansible multiphase clock generation systems and method, the system includes clock source, clock unit and the phase clock unit to connect one to one with the output terminal of clock source, wherein, the input end of clock of clock unit is connect with the input end of clock of phase clock unit with the output terminal of clock source, and the output terminal of clock unit is connect with the input D ends of phase clock unit.The expansible multiphase clock generation system that the application provides carries out phase expansion by the clock that clock unit and phase clock unit export clock source, and scalability is strong, can expand to and support 16 phases, 32 phases, even more clock phases etc.；And the system structure is simple, simplifies multiphase clock design complexities, largely reduces the specification demands of clock source design, reduces design cost.
Description
Technical field
This application involves electronic technology field more particularly to a kind of expansible multiphase clock generation systems and method.
Background technology
Multiphase clock is frequently used in the various fields such as communication, electronics, for example applied to high speed serialization transceiver, uses
Multiple phases carry out repeated sampling to receiving data, to carry out data recovery etc..Be also applied to need multi-channel sampling or
The function module of person's multichannel access control to improve electromagnetic environmental impact, reduces the interference of interchannel, improves system operation
Stability etc..
Traditional multiphase clock generation, is usually used full analog circuit to realize, full analog circuit include phase discriminator,
Charge pump, loop filter and voltage controlled delay line, phase discriminator are used for defeated to frequency input signal and the frequency fed back
The phase for going out signal is detected and exports corresponding detection signal, and detection signal is rises or falls signal；Charge pump is being examined
It surveys under the control for rising or falling signal of signal and carries out charge or discharge, and control voltage is formed after loop filter；
Voltage controlled delay line is connected in series by multilevel delay unit, and input terminal receives frequency input signal, output terminal output frequency are defeated
Go out signal, delay cells at different levels respectively carry out the signal of input certain delay, and control voltage can be to voltage control delay
The delay time of the delay cells at different levels of line is adjusted, and by the negative feedback control of entire loop, can be so that after locking
Frequency output signal and frequency input signal phase difference be a cycle.
It is but limited using the multiphase clock number of active lanes that full analog circuit generates, it has not been convenient to phase expansion, and full mould
It is high to intend circuit design difficulty, analog parameter adjustment time is long, and the chip area needed is big, and chip cost is caused to increase, and product is ground
The time cycle of hair increases.
Invention content
This application provides a kind of expansible multiphase clock generation system and method, to solve current multiphase clock
The number of active lanes of generation is limited, it has not been convenient to the technical issues of phase expansion.
In order to solve the above-mentioned technical problem, the embodiment of the present application discloses following technical solution：
In a first aspect, the embodiment of the present application discloses a kind of expansible multiphase clock generation system, including clock source,
Clock unit and the phase clock unit to connect one to one with the output terminal of the clock source, wherein,
The input end of clock of the input end of clock of the clock unit and the phase clock unit with the clock source
Output terminal connection, the output terminal of the clock unit connect with the input D ends of the phase clock unit.
Optionally, the clock source includes the first output terminal and second output terminal, and the phase clock unit includes first
Phase clock unit and second phase clock unit, wherein,
The input end of clock of the input end of clock of the clock unit and the first phase clock unit is with described the
One output terminal connects, and the phase output of the clock unit is connect with the input D ends of the first phase clock unit；
The input end of clock of the second phase clock unit is connect with the second output terminal, the first phase clock
The phase output of unit is connect with the input D ends of the second phase clock unit.
Optionally, the clock unit and first phase clock unit become one formula structure.
Optionally, the phase clock unit include 2-4 register, the input end of clock of the register and it is described when
The output terminal connection of Zhong Yuan；
The register is sequentially connected in series according to the sequence of rising edge trigger register connection failing edge trigger register.
Optionally, the phase clock unit includes first order register, second level register, third level register and the
Level Four register, the first order register and the register that third level register is rising edge triggering, the second level deposit
Device and the register that fourth stage register is failing edge triggering；
The first order register, second level register, third level register and fourth stage register input end of clock
Output terminal with the clock source is connect；
The phase output of the first order register is connect with the input D ends of the second level register, and described second
The phase output of grade register is connect with the input D ends of the third level register, and the phase of the third level register is defeated
Outlet is connect with the input D ends of the fourth stage register.
Optionally, the input D ends of first order register and the first phase clock in the second phase clock unit
The phase output connection of first order register in unit.
Optionally, the output QN ends of first order register and the first order register in the first phase clock unit
Input D ends connection.
Optionally, the clock frequency of clock source output is 2 times of the phase clock unit output clock frequency, institute
The clock frequency for stating clock unit output is identical with the clock frequency that the phase clock unit exports.
Second aspect, the embodiment of the present application disclose a kind of expansible multiphase clock production method, the method packet
It includes：
The clock of multiple and different phases is generated by clock source, and the clock of out of phase is respectively sent to corresponding phase
Bit clock unit；
The phase clock unit receives the clock that the clock source generates, and carries out phase expansion to the clock.
Optionally, the phase clock unit receives the clock that clock source generates, and carries out phase expansion to the clock,
Including：
The register of the phase clock unit respectively samples the rising edge of clock with failing edge；
After obtaining sampled data, when the register of the phase clock unit exports the phase of 90 degree of phases of difference respectively
Clock.
Compared with prior art, the application has the beneficial effect that：
The embodiment of the present application provides a kind of expansible multiphase clock generation system and method, which includes clock
Source, clock unit and the phase clock unit to connect one to one with the output terminal of clock source, wherein, the clock of clock unit
Input terminal is connect with the input end of clock of phase clock unit with the output terminal of clock source, the output terminal and phase of clock unit
The input D ends connection of clock unit.The expansible multiphase clock generation system that the application provides passes through clock unit and phase
The clock that bit clock unit exports clock source carries out phase expansion, and scalability is strong, can expand to and support 16 phases, 32 phases
Position, even more clock phases etc.；And the system structure is simple, can simplify multiphase clock design complexities, and it can
The specification demands of clock source design are largely reduced, reduce design cost.
It should be understood that above general description and following detailed description are only exemplary and explanatory, not
The application can be limited.
Description of the drawings
In order to illustrate more clearly of the technical solution of the application, letter will be made to attached drawing needed in the embodiment below
Singly introduce, it should be apparent that, for those of ordinary skills, without creative efforts, also
Other attached drawings can be obtained according to these attached drawings.
Fig. 1 is a kind of structure diagram of expansible multiphase clock generation system provided in an embodiment of the present invention；
Fig. 2 is the structure of clock unit in a kind of expansible multiphase clock generation system provided in an embodiment of the present invention
Schematic diagram；
Fig. 3 is the equivalent of clock unit in a kind of expansible multiphase clock generation system provided in an embodiment of the present invention
Structure diagram；
Fig. 4 is phase clock unit in a kind of expansible multiphase clock generation system provided in an embodiment of the present invention
Structure diagram；
Fig. 5 is phase clock unit in a kind of expansible multiphase clock generation system provided in an embodiment of the present invention
Equivalent structure schematic diagram；
Fig. 6 is that the structure of one embodiment of expansible multiphase clock generation system provided in an embodiment of the present invention is shown
It is intended to；
Fig. 7 is the simulation waveform that multiphase clock expansible in Fig. 6 generates；
Fig. 8 is the equivalent knot of one embodiment of expansible multiphase clock generation system provided in an embodiment of the present invention
Structure schematic diagram；
Fig. 9 is a kind of flow chart of expansible multiphase clock production method provided in an embodiment of the present invention.
Specific embodiment
In order to make those skilled in the art better understand the technical solutions in the application, below in conjunction with the application reality
The attached drawing in example is applied, the technical solution in the embodiment of the present application is clearly and completely described, it is clear that described implementation
Example is only some embodiments of the present application rather than whole embodiments.Based on the embodiment in the application, the common skill in this field
Art personnel all other embodiments obtained without making creative work should all belong to the application protection
Range.
Fig. 1 is participated in, is a kind of structural representation of expansible multiphase clock generation system provided in an embodiment of the present invention
Figure.
Expansible multiphase clock generation system provided by the embodiments of the present application include clock source, clock unit and with
The phase clock unit that the output terminal of clock source connects one to one, wherein,
The input end of clock of clock unit is connect with the input end of clock of phase clock unit with the output terminal of clock source,
For receiving the clock of clock source output；The output terminal of clock unit is connect with the input D ends of phase clock unit, for generating
The initial clock of 0 phase, the work of phase-triggered clock unit.
As shown in Fig. 2, clock unit is a register, its effect is when generating a base frequency and phase
Clock, after phase clock unit all go to make sampling time delay on the basis of it, so as to generate the clock of multiple phases.Clock
Unit includes input end of clock (CK), input terminal (D), phase output (Q) and output terminal (QN), and the CK ends of clock unit connect
The output terminal of clock source, the QN ends of clock unit are connected to the input D ends of register, and effect is in each clock source clock
QN ends are connected to D ends when (pll clock) rising edge, and are negated every time, therefore, need 2 pll clock period shapes in total
The complete signal period is exported into clock unit, i.e., can generate the clock signal of one 2 frequency dividing.That is, clock unit
Output clock frequency be clock source output clock frequency half.Because the input D ends of phase clock unit connect clock unit
Phase output, therefore, phase clock unit output clock frequency it is identical with the clock frequency that clock unit exports.
Because the QN ends of register negate output for Q ends, therefore, the structure diagram of clock unit can be equivalent to Fig. 3, it will
The output terminal Q of register passes through a reverser, is connected to the input terminal D of register, can equally play and generate 2 frequency-dividing clocks letter
Number effect.
Because the output terminal of phase clock unit and clock source connects one to one, therefore, with clock source, there are two output terminals
For.The expansible multiphase clock generation system that the application provides includes clock source, a clock unit and and clock
The first phase clock unit that the output terminal in source connects one to one and second phase clock unit, wherein,
Clock source includes the first output terminal and second output terminal, the clock clka and second output terminal of the output of the first output terminal
There are phase differences between the clock clkb of output.The input end of clock CK and the clock of first phase clock unit of clock unit are defeated
Enter to hold CK to be connect with the first output terminal of clock source, the phase output Q of clock unit is defeated with first phase clock unit
Enter the connection of D ends；The input end of clock CK of second phase clock unit and the second output terminal of clock source connect, first phase clock
The output terminal Q of unit is connect with the input D ends of second phase clock unit.
Clock unit receives the clock clka of the first output terminal output of clock source, and 1/2 frequency is exported after clock is handled
Initial clock, first phase clock unit receives the clock that initial clock and the first output terminal of clock unit output export
After clka, the clock of 2-4 phase is exported, and is exported the clock of a phase as initial clock to second phase clock list
Member.Second phase clock unit receives the phase clock of first phase clock unit output and the clock of second output terminal output
After clkb, the clock of 2 phases is exported.In this way, 2 phase clocks can be extended to 4-8 phase clock.
Phase clock unit generally comprises 2-4 register, and register connects failing edge according to rising edge trigger register
The sequence of trigger register is sequentially connected in series, and the output terminal of the input end of clock CK of register and clock source connects.
As shown in figure 4, it is illustrated so that phase clock unit includes 4 registers as an example.Phase clock unit includes the
Level-one register, second level register, third level register and fourth stage register, first order register and third level register
For the register of rising edge triggering, second level register and the register that fourth stage register is failing edge triggering.The first order is posted
Storage, second level register, third level register and the input end of clock CK of fourth stage register are defeated with one of clock source
Outlet connects, such as the input end of clock CK of first order register, second level register, third level register and fourth stage register
The first output terminal of clock source is all connected with, receives clock clka.
The phase output of the phase output of clock unit or previous phase clock unit is defeated with first order register
Enter the connection of D ends, the phase output of first order register is connect with the input D ends of second level register, second level register
Phase output is connect with the input D ends of third level register, phase output and the fourth stage register of third level register
Input D ends connection, i.e., first order register pair clock unit or previous phase clock unit output clock signal adopted
Sample, output clock go out clk_a0；The clock clk_a0 of second level register pair first order register output is sampled, during output
Clock clk_a1；The clock clk_a1 of third level register pair second level register output is sampled, output clock clk_a2；The
The clock clk_a2 of level Four register pair third level register output is sampled, output clock clk_a3.
Because clock source PLL output clock frequency is 2 times of first order register output clock frequency, and second level register
Be with the failing edge of PLL output clock go sampling first order register output clock, therefore the second level register output clock with
The phase difference of first order register output clock is 90 degree.Therefore, first order register exports the clock clk_a0 of 0 degree of phase,
Second level register exports the clock clk_a1 of 90 degree of phases, and third level register exports the clock clk_a2 of 180 degree phase, the
Level Four register exports the clock clk_a3 of 270 degree of phases.
Because 0 degree and the inverse relationships, and the QN ends of register are the anti-of register Q ends each other of 180 degree, 90 degree and 270 degree
Structure as shown in Figure 5 can be reduced to the structure of output, therefore phase clock unit.Phase clock unit includes 2 in total
Register, first order register is in the rising edge clock sampled data of clka, the clock clk_ of output terminal Q correspondence 0 phases of output
A0, output terminal QN correspond to the clock clk_a2 of output 180 degree phase；Second level register is in the clock falling edge hits of clka
According to output terminal Q corresponds to the clock clk_a2 of 90 degree of phases of output, and output terminal QN corresponds to the clock clk_a3 of 270 degree of phases of output.
Can also be that first order register is in the rising edge clock sampled data of clka, output terminal Q correspondence 0 degree of phase of output
The clock clk_a0 of position, connects a reverser on output terminal Q, and reverser corresponds to the clock clk_a2 of output 180 degree phase；
Second level register clka clock falling edge sampled data, output terminal Q correspond to output 90 degree of phases clock clk_a1,
A reverser is connected on output terminal Q, reverser corresponds to the clock clk_a3 of 270 degree of phases of output.
As long as ensure that the phase difference between the phase clock of clock source output is less than 90 degree, after first phase clock unit
Can be the input D ends connection clock unit of the first register in second phase clock when face connects second phase clock unit
Phase output, initial clock and the clock source second output terminal that first order register receives clock unit output respectively export
Clock clkb, the clock clk_b0 of 0 degree of phase is exported after sampled data；Can also first be posted in second phase clock unit
The phase output of first order register, second phase clock unit in the input D ends connection first phase clock unit of storage
Middle first order register receive respectively 0 degree phase clock clk_a0 that first order register in first phase clock unit exports and
The clock clkb of clock source second output terminal output exports the clock clk_b0 of 0 degree of phase after sampled data.
Can also become one clock unit and first phase clock unit formula structure, i.e., by clock unit and first
The first order register of phase clock unit integrates.Specifically, first order register in first phase clock unit
Input end of clock connects the first output terminal of clock source, receives clock clka, the output terminal QN connections first of first order register
The input D ends of grade register are equivalent to the clock signal that first order register produces one 2 frequency dividing, and the clock signal is by the
The output terminal Q outputs of level-one register；First order register is defeated in phase clock unit after first phase clock unit
Enter the phase output that D ends are all connected with first phase clock unit.
The output terminal QN connections of first order register in each phase clock unit can also be inputted D ends, and during phase
Between clock unit independently of each other, be not connected to.
Clock unit and phase clock unit can also form to a phase expansion module, each phase expansion module with
The output terminal of clock source connects one to one.Specifically, the first output terminal of first phase expansion module and clock source connects, the
The second output terminal of two phase expansion module and clock source connects, and so on, and between phase expansion module independently of each other, no
Connection.
The embodiment of the present application is generated 16 phase clocks and is illustrated with 1 clock unit and 4 phase clock units：
As shown in fig. 6, calling a clock source (PLL modules), it is desirable that it can export 4 phase clocks, respectively clka,
Clkb, clkc, clkd, four phase clock frequencies are identical, their phase relation is respectively 0 degree, 22.5 degree, 45 degree, and 67.5
Degree, the input end of clock CK of the clock clka incoming clock units of 0 degree of phase is posted with the first order in first phase clock unit
Storage, second level register, third level register and fourth stage register input end of clock CK, the phase output of clock unit
Hold the input D ends of Q connection first order registers, the input D of the phase output Q connections second level register of first order register
End, the input D ends of the phase output Q connection third level registers of second level register, the phase output of third level register
Hold the phase output of Q connection fourth stage registers；It will be in the clock clkb access second phase clock units of 22.5 degree of phases
First order register, second level register, third level register and fourth stage register input end of clock CK, during first phase
In clock unit in the phase output Q connection second phase clock units of the first order register first order register input D ends,
It is sequentially connected in series first order register, second level register, third level register and the fourth stage of second phase clock unit
Register.
Later according to such sequence, by the input end of clock of the clock clkc access third phase clock units of 45 degree of phases
CK, the first order is posted in the phase output Q connection third phase clock units of first order register in second phase clock unit
The input D ends of storage；The clock clkd of 67.5 degree of phases is accessed to the input end of clock CK of the 4th phase clock unit, third phase
In bit clock unit in the 4th phase clock unit of phase output Q connections of the first order register first order register input
D ends.So by PLL modules, clock unit, first phase clock unit, second phase clock unit, third phase clock unit
It is connected with the 4th phase clock unit.
After the completion of system line connection, the phase clock phase that first phase clock unit generates is followed successively by 0 degree, 90 degree,
180 degree, 270 degree；The phase clock phase that second phase clock unit generates is followed successively by 0+22.5 degree (22.5 degree), 90+22.5
It spends (112.5 degree), 180+22.5 degree (202.5 degree), 270+22.5 degree (292.5 degree)；The phase that third phase clock unit generates
Bit clock phase is followed successively by 0+45 degree (45 degree), 90+45 degree (135 degree), 180+45 degree (225 degree), 270+45 degree (315 degree)；
The phase clock phase that 4th phase clock unit generates is followed successively by 0+67.5 degree (67.5 degree), 90+67.5 degree (157.5 degree),
180+67.5 degree (47.5 degree), 270+67.5 degree (337.5 degree).In this way, 0 degree that PLL modules are generated, 22.5 degree, 45 degree,
67.5 degree of phase clocks be extended to 0 degree, 22.5 degree, 45 degree, 67.5 degree, 90 degree, 112.5 degree, 135 degree, 157.5 degree, 180 degree,
202.5 degree, 225 degree, 247.5 degree, 270 degree, 292.5 degree, 315 degree, 337.5 degree of phase clocks, greatly expand phase path.
It can be seen from the above, clock unit and the clock frequency of phase clock unit output are clock source output clock frequency
Half, therefore, PLL modules, first phase clock unit second phase clock unit, third phase clock unit and the 4th phase
The clock signal waveform of clock unit output is as shown in Figure 7.
When specific implementation, clock unit and first phase clock unit can be integrated, become such as Fig. 8
Shown circuit structure.
Expansible multiphase clock generation system provided by the embodiments of the present application passes through a clock unit and at least one
A phase clock unit generates multiphase clock fan-out capability, by the way of the realization of digital logic, to PLL when leggies
The clock source of clock is effectively extended phase, is largely reduced the design difficulty in PLL isochronons source, is reduced and set
Count cost；And the system structure is simple, scalability is strong, designer is facilitated to extend more clock phases, for example can extend
To supporting 16 phases, 32 phases, even more clock phases etc.；In addition, the application uses a unified clock source, so
Each phase clock unit is all by the way of following afterwards, so as to ensure that the accuracy of phase clock phase, meets height
Precision applications demand；In addition, the output clock frequency of the application phase clock unit is only the one of clock source output clock frequency
Half, whole system can run to higher clock frequency, to generate the multiphase clock fan-out capability of higher frequency.
Based on expansible multiphase clock generation system provided by the embodiments of the present application, the embodiment of the present application additionally provides
A kind of expansible multiphase clock production method.
As shown in figure 9, expansible multiphase clock production method provided by the embodiments of the present application includes：
S100：It generates the clock of multiple and different phases by clock source, and the clock of out of phase is respectively sent to pair
The phase clock unit answered.
Clock source can generate the clock signal that multiple frequencies are identical, phase is different, and multiple clock signals are respectively connected to
Connect one to one end phase clock unit therewith.Meanwhile by clock signal incoming clock unit, clock unit is according to clock
The clock signal of one 2 frequency dividing of signal bad student, the clock frequency of output are the half of clock source output clock frequency.
S200：The phase clock unit receives the clock that the clock source generates, and carries out phase expansion to the clock
Exhibition.
After phase clock unit receives clock signal, the register in phase clock unit is respectively in the upper of clock signal
Edge and failing edge sampled data are risen, generates delay, respectively the phase clock of 90 degree of phases of output difference.
It should be noted that in the present specification, the relational terms of such as " first " and " second " or the like are used merely to
One entity with another entity is distinguished, and not necessarily requires or imply that there are any this reality between these entities
Relationship or sequence.Moreover, term " comprising ", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion,
So that the circuit structure including a series of elements not only includes those elements, but also other including being not explicitly listed
Element or further include the element intrinsic for this circuit structure.In the absence of more restrictions, there is sentence " packet
Include one ... " limit element, it is not excluded that also there are other identical elements in the circuit structure including the element.
Those skilled in the art will readily occur to the application its after considering specification and putting into practice the disclosure invented here
His embodiment.This application is intended to cover the present invention any variations, uses, or adaptations, these modifications, purposes or
Person's adaptive change follows the general principle of the application and including the undocumented common knowledge in the art of the application
Or conventional techniques.Description and embodiments are considered only as illustratively, and the true scope and spirit of the application will by right
The content asked is pointed out.
Above-described the application embodiment does not form the restriction to the application protection domain.
Claims (10)
1. a kind of expansible multiphase clock generation system, which is characterized in that including clock source, clock unit and with it is described
The phase clock unit that the output terminal of clock source connects one to one, wherein,
The input end of clock of the clock unit and the input end of clock of the phase clock unit are defeated with the clock source
Outlet connects, and the output terminal of the clock unit is connect with the input D ends of the phase clock unit.
2. system according to claim 1, which is characterized in that the clock source includes the first output terminal and the second output
End, the phase clock unit include first phase clock unit and second phase clock unit, wherein,
The input end of clock of the clock unit and the input end of clock of the first phase clock unit are defeated with described first
Outlet connects, and the phase output of the clock unit is connect with the input D ends of the first phase clock unit；
The input end of clock of the second phase clock unit is connect with the second output terminal, the first phase clock unit
Phase output connect with the input D ends of the second phase clock unit.
3. system according to claim 2, which is characterized in that the clock unit is integrated into first phase clock unit
Integral structure.
4. system according to claim 3, which is characterized in that the phase clock unit includes 2-4 register, described
The input end of clock of register is connect with the output terminal of the clock source；
The register is sequentially connected in series according to the sequence of rising edge trigger register connection failing edge trigger register.
5. system according to claim 4, which is characterized in that the phase clock unit includes first order register, the
Two-stage register, third level register and fourth stage register, the first order register are rising edge with third level register
The register of triggering, the second level register and the register that fourth stage register is failing edge triggering；
The first order register, second level register, third level register and fourth stage register input end of clock with
The output terminal connection of the clock source；
The phase output of the first order register is connect with the input D ends of the second level register, and the second level is posted
The phase output of storage is connect with the input D ends of the third level register, the phase output of the third level register
It is connect with the input D ends of the fourth stage register.
6. system according to claim 5, which is characterized in that first order register in the second phase clock unit
Input D ends are connect with the phase output of first order register in the first phase clock unit.
7. system according to claim 5, which is characterized in that first order register in the first phase clock unit
Output QN ends are connect with the input D ends of the first order register.
8. system according to claim 1, which is characterized in that when the clock frequency of the clock source output is the phase
2 times of clock unit output clock frequency, the clock frequency of clock unit output and phase clock unit output when
Clock frequency is identical.
9. a kind of expansible multiphase clock production method, which is characterized in that the method includes：
When the clock of multiple and different phases is generated by clock source, and the clock of out of phase being respectively sent to corresponding phase
Clock unit；
The phase clock unit receives the clock that the clock source generates, and carries out phase expansion to the clock.
10. according to the method described in claim 9, it is characterized in that, the phase clock unit receive clock source generate when
Clock, and phase expansion is carried out to the clock, including：
The register of the phase clock unit respectively samples the rising edge of clock with failing edge；
After obtaining sampled data, the register of the phase clock unit exports the phase clock of 90 degree of phases of difference respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711463570.4A CN108199711A (en) | 2017-12-28 | 2017-12-28 | A kind of expansible multiphase clock generation system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711463570.4A CN108199711A (en) | 2017-12-28 | 2017-12-28 | A kind of expansible multiphase clock generation system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108199711A true CN108199711A (en) | 2018-06-22 |
Family
ID=62585160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711463570.4A Pending CN108199711A (en) | 2017-12-28 | 2017-12-28 | A kind of expansible multiphase clock generation system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108199711A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060115033A1 (en) * | 2004-11-30 | 2006-06-01 | Oki Electric Industry Co., Ltd. | Data transmission circuit with serial interface and method for transmitting serial data |
| US7187738B2 (en) * | 2000-12-06 | 2007-03-06 | Fujitsu Limited | Processing high-speed digital signals |
| CN102404101A (en) * | 2010-09-15 | 2012-04-04 | 索尼公司 | Phase adjustment circuit, receiving apparatus and communication system |
| CN103684362A (en) * | 2012-09-10 | 2014-03-26 | 联咏科技股份有限公司 | Multiphase clock divider |
| CN104753524A (en) * | 2013-12-25 | 2015-07-01 | 中国科学院电子学研究所 | Delay locked loop |
| CN104851402A (en) * | 2015-05-27 | 2015-08-19 | 深圳市华星光电技术有限公司 | Multi-phase clock generation circuit and liquid crystal display panel |
| US20160099717A1 (en) * | 2014-10-06 | 2016-04-07 | Socionext Inc. | Transmission circuit, integrated circuit, and parallel-to-serial conversion method |
| CN106788390A (en) * | 2016-12-20 | 2017-05-31 | 中国电子科技集团公司第五十八研究所 | For DDS digital cores and the circuit interface system of digital analog converter |
-
2017
- 2017-12-28 CN CN201711463570.4A patent/CN108199711A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7187738B2 (en) * | 2000-12-06 | 2007-03-06 | Fujitsu Limited | Processing high-speed digital signals |
| US20060115033A1 (en) * | 2004-11-30 | 2006-06-01 | Oki Electric Industry Co., Ltd. | Data transmission circuit with serial interface and method for transmitting serial data |
| CN102404101A (en) * | 2010-09-15 | 2012-04-04 | 索尼公司 | Phase adjustment circuit, receiving apparatus and communication system |
| CN103684362A (en) * | 2012-09-10 | 2014-03-26 | 联咏科技股份有限公司 | Multiphase clock divider |
| CN104753524A (en) * | 2013-12-25 | 2015-07-01 | 中国科学院电子学研究所 | Delay locked loop |
| US20160099717A1 (en) * | 2014-10-06 | 2016-04-07 | Socionext Inc. | Transmission circuit, integrated circuit, and parallel-to-serial conversion method |
| CN104851402A (en) * | 2015-05-27 | 2015-08-19 | 深圳市华星光电技术有限公司 | Multi-phase clock generation circuit and liquid crystal display panel |
| CN106788390A (en) * | 2016-12-20 | 2017-05-31 | 中国电子科技集团公司第五十八研究所 | For DDS digital cores and the circuit interface system of digital analog converter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105811923B (en) | A kind of clock duty cycle adjustment circuit | |
| KR920006891A (en) | Standard delay generator and electronic device using the same | |
| US20130207703A1 (en) | Edge selection techniques for correcting clock duty cycle | |
| CN102035472B (en) | Programmable digital frequency multiplier | |
| CN102647185A (en) | Clock and data recovery circuit with built-in jitter test function and method thereof | |
| CN110649922B (en) | Digital clock frequency multiplier | |
| US7555089B2 (en) | Data edge-to-clock edge phase detector for high speed circuits | |
| CN110887992A (en) | Clock frequency detection circuit | |
| EP0506595A1 (en) | Data processing system having four phase clocks generated separately on each processor chip | |
| CN107800427A (en) | Clock data recovery module | |
| CN108768396A (en) | A kind of clock phase mismatch calibration circuit for multichannel ADC | |
| CN110492872A (en) | Digital duty-cycle correction circuit system | |
| CN106443692B (en) | A kind of method and apparatus of precise measurement hopping edge arrival time | |
| CN109861690A (en) | Export feedback clock duty cycle adjustment device, method and system | |
| CN108199711A (en) | A kind of expansible multiphase clock generation system and method | |
| CN100578246C (en) | Method for generating testing vector | |
| CN101582693A (en) | Frequency detection circuit and method of clock data restorer | |
| US6999542B1 (en) | Data ready indicator between different clock domains | |
| CN116125148A (en) | Pulse signal width detection circuit and chip | |
| CN105245235A (en) | Serial-to-parallel conversion circuit based on clock phase modulation | |
| CN205657674U (en) | IF converting circuit | |
| EP4012423A1 (en) | Detection circuit and detection method | |
| KR102476654B1 (en) | Clock generating circuit and semiconductor apparatus including the same | |
| US6172544B1 (en) | Timing signal generation circuit for semiconductor test system | |
| CN207732751U (en) | A kind of ultra wide band simulation frequency multiplication excitation system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180622 |
|
| RJ01 | Rejection of invention patent application after publication |