CN108172565B - MOM capacitor and integrated circuit - Google Patents
MOM capacitor and integrated circuit Download PDFInfo
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- CN108172565B CN108172565B CN201711444665.1A CN201711444665A CN108172565B CN 108172565 B CN108172565 B CN 108172565B CN 201711444665 A CN201711444665 A CN 201711444665A CN 108172565 B CN108172565 B CN 108172565B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
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- Semiconductor Integrated Circuits (AREA)
Abstract
The application provides a MOM electric capacity and integrated circuit, the MOM electric capacity includes: a substrate; the shielding layer is positioned on the substrate and has an integral layer structure; the shielding layer is positioned on one side, away from the substrate, of the shielding layer and comprises a plurality of metal layers and a plurality of oxidation layers which are stacked in a crossed mode; each metal layer comprises a plurality of first interdigital structures and second interdigital structures which are mutually crossed; the first interdigital structure in the metal layer closest to the shielding layer in the multiple metal layers is in short circuit with the shielding layer; and the second interdigital structure in the metal layer closest to the shielding layer in the multi-layer metal layer is insulated from the shielding layer. The shielding layer at least can shield the parasitic capacitance formed on the opposite surface between the metal layer and the substrate, so that the parasitic capacitance of one electrode of the MOM capacitor relative to the substrate is reduced, the capacitance value of the MOM capacitor is larger under the same area, the capacitance density of the MOM capacitor is increased, and the application of the MOM capacitor is wider.
Description
Technical Field
The invention relates to the technical field of integrated circuit device manufacturing, in particular to an MOM capacitor and an integrated circuit.
Background
Integrated Circuits (ICs) typically include various passive devices, and capacitors are one common passive device that is widely used in ICs in a variety of applications. Two commonly used capacitor structures in the prior art are MIM (metal insulator metal) capacitors and MOM (metal oxide metal) capacitors. Typically, MIM capacitors include an insulator between two metal layers, while MOM capacitors consist of a large number of parallel "fingers" or electrodes formed on many metal layers.
In the MIM capacitor, the parasitic capacitance is generally small because the bottom plate shields the top plate, however, the MIM capacitor requires an additional mask in the fabrication process, resulting in high fabrication cost.
On the contrary, the manufacture of MOM capacitors can easily form metal layers through equipment, and as the technology of the process is developed, the density of the capacitors is gradually increased, and MOM capacitors are widely used. However, the parasitic capacitance of both electrodes of the MOM capacitor is large compared to the MIM capacitor, so that the application of the MOM capacitor in a circuit is limited.
Disclosure of Invention
In view of the above, the present invention provides an MOM capacitor and an integrated circuit to solve the problem of the prior art that the parasitic capacitance of two electrodes of the MOM capacitor is large.
In order to achieve the purpose, the invention provides the following technical scheme:
a MOM capacitor, comprising:
a substrate;
the shielding layer is positioned on the substrate and has a whole-layer structure;
the shielding layer is positioned on one side, away from the substrate, of the shielding layer and is formed by a plurality of metal layers and a plurality of oxidation layers which are in crossed lamination; each metal layer comprises a plurality of first interdigital structures and second interdigital structures which are mutually crossed; the first interdigital structures in the multiple metal layers are electrically connected to serve as first electrodes of the MOM capacitor, and the second interdigital structures in the multiple metal layers are electrically connected to serve as second electrodes of the MOM capacitor;
a first interdigital structure in a metal layer closest to the shielding layer in the plurality of metal layers is in short circuit with the shielding layer; and the second interdigital structure in the metal layer closest to the shielding layer in the plurality of metal layers is insulated from the shielding layer.
Preferably, the projection of the multilayer metal layer on the plane of the substrate is located in the projection of the shielding layer on the plane of the substrate.
Preferably, the shielding layer is a polysilicon layer.
Preferably, the polysilicon layer is a metal silicide polysilicon layer.
Preferably, the shielding layer is a metal layer.
Preferably, the projected edge of the shielding layer on the plane of the substrate is at least 2 microns further than the projected edge of the multi-layer metal layer on the plane of the substrate.
Preferably, the projected edge of the shielding layer on the plane of the substrate is 2 microns more extended than the projected edge of the multi-layer metal layer on the plane of the substrate.
The present invention also provides an integrated circuit comprising: the MOM capacitor of any of the above.
Preferably, the integrated circuit is a charge pump.
Preferably, the charge pump is a cross-coupled charge pump.
According to the technical scheme, the whole shielding layer is formed between the substrate and the multiple metal layers, and the shielding layer can at least shield the parasitic capacitance formed on the opposite surface between the metal layers and the substrate, so that the parasitic capacitance of one electrode of the MOM capacitor relative to the substrate is reduced, the capacitance value of the MOM capacitor is larger under the same area, the capacitance density of the MOM capacitor is increased, and the application of the MOM capacitor is wider.
The invention also provides an integrated circuit which comprises the MOM capacitor, and the parasitic capacitance of the electrode at one end of the MOM capacitor relative to the substrate is reduced, so that the integrated circuit can be applied to the integrated circuit, and the parasitic capacitance of the integrated circuit is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a three-dimensional schematic diagram of a MOM capacitor in the prior art;
FIG. 2 is a schematic cross-sectional view of a MOM capacitor of the prior art;
FIG. 3 is a simplified equivalent circuit diagram of a MOM capacitor in the prior art;
FIG. 4 is a schematic cross-sectional view of an MOM capacitor provided in an embodiment of the present invention;
FIG. 5 is a simplified equivalent circuit diagram of an MOM capacitor according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of another MOM capacitor provided in an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of another MOM capacitor provided in an embodiment of the present invention;
FIG. 8 is an equivalent circuit diagram of a prior art charge pump without considering parasitic capacitance;
FIG. 9a is a circuit diagram of an equivalent charge pump circuit considering parasitic capacitance in the prior art;
FIG. 9b is an equivalent circuit diagram of a charge pump provided in an embodiment of the present invention;
FIG. 10 is a timing control diagram of the switches in the equivalent circuit diagrams shown in FIGS. 8, 9a, and 9 b;
FIG. 11 is an equivalent circuit diagram of a cross-coupled charge pump without considering parasitic capacitance in the prior art;
FIG. 12a is a prior art equivalent circuit diagram of a cross-coupled charge pump considering parasitic capacitance;
FIG. 12b is an equivalent circuit diagram of a cross-coupled charge pump provided in an embodiment of the present invention;
fig. 13 is a timing control diagram of the clock signals in the equivalent circuit diagrams shown in fig. 11, 12a, 12 b.
Detailed Description
As described in the background section, the parasitic capacitance of the MOM capacitor in the prior art is large.
The inventors have found that this occurs because, referring to fig. 1, fig. 1 is a three-dimensional representation of a stacked metallization structure of a MOM capacitor 100, where the MOM capacitor 100 includes a plurality of metal layers M1-M6, where M1 is a first layer metal of the MOM capacitor, M2 is a second layer metal, and Mn is an nth layer metal, and each metal layer includes interdigitated fingers 110 and 120. The fingers 110 and 120 on the different metal layers M1-M6 are connected by a plurality of vias and may be separated by an oxide layer (not shown). The fingers 110 in each metal layer are connected to form a first electrode a of the MOM capacitor, and the fingers 120 in the metal layers are connected to form a second electrode B of the MOM capacitor.
Referring to fig. 2, fig. 2 is a cross-sectional view of the MOM capacitor 100, in which the capacitor is formed between sidewalls of metal in the same layer. As shown in fig. 2, there is also a large parasitic capacitance in the MOM capacitance, which is formed primarily by the bottom and side surfaces of fingers 110 and 120 and the upper surface of substrate 01. It should be noted that the first metal layer M1 is closest to the substrate, and therefore the parasitic capacitance between the first metal layer M1 and the substrate 01 is the largest, and the parasitic capacitance of each metal layer M2 … … Mn located above the first metal layer M1 is smaller than that of the substrate 01 due to the blocking of the first metal layer M1, and is negligible with respect to the parasitic capacitance of the first metal layer M1 and the substrate 01.
As shown in fig. 2, the parasitic capacitance of the first metal layer M1 to the substrate 01 includes two parts: the bottom surface of the first metal layer M1 is opposite to the substrate 01 to form a parallel plate capacitor, and the sidewall of the first metal layer M1 is opposite to the substrate to form a sidewall capacitor. These two parasitic capacitances are collectively denoted by Cp1, and the parasitic capacitances of the first electrode a and the second electrode B to the substrate 01 are the same in magnitude, each accounting for Cp1/2, that is, in fig. 3, Cp is Cp 1/2. Fig. 3 is a simplified equivalent circuit diagram of fig. 2, wherein the capacitor Cmom is an actually required MOM capacitor of the MOM capacitor, Cp is an undesired parasitic capacitor, and it should be noted that the ground terminal in fig. 3 is the substrate 01 in fig. 2, and in an actual use process, the substrate 01 is grounded, so that the substrate is equivalent to the ground terminal. It can be known from the prior art that both electrodes have parasitic capacitance with respect to the substrate, and the parasitic capacitance is large.
Based on this, the invention provides an MOM capacitor, comprising:
a substrate;
the shielding layer is positioned on the substrate and has a whole-layer structure;
the shielding layer is positioned on one side, away from the substrate, of the shielding layer and is formed by a plurality of metal layers and a plurality of oxidation layers which are in crossed lamination; each metal layer comprises a plurality of first interdigital structures and second interdigital structures which are mutually crossed; the first interdigital structures in the multiple metal layers are electrically connected to serve as first electrodes of the MOM capacitor, and the second interdigital structures in the multiple metal layers are electrically connected to serve as second electrodes of the MOM capacitor;
a first interdigital structure in a metal layer closest to the shielding layer in the plurality of metal layers is in short circuit with the shielding layer; and the second interdigital structure in the metal layer closest to the shielding layer in the plurality of metal layers is insulated from the shielding layer.
According to the MOM capacitor provided by the invention, the whole shielding layer is formed between the substrate and the multiple metal layers, and the shielding layer at least can shield the parasitic capacitor formed on the opposite surface between the metal layers and the substrate, so that the parasitic capacitor of the MOM capacitor is reduced, the capacitance value of the MOM capacitor is larger under the same area, the capacitance density of the MOM capacitor is increased, and the application of the MOM capacitor is wider.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 4, fig. 4 is a schematic cross-sectional structure diagram of an MOM capacitor according to an embodiment of the present invention, where the MOM capacitor includes:
a substrate 1;
the shielding layer 2 is positioned on the substrate 1, and the shielding layer 2 is of a whole-layer structure;
a plurality of metal layers (Mm … … Mn) and a plurality of oxide layers (not shown in the figure) which are crossly laminated on the side of the shielding layer 2 facing away from the substrate 1; each metal layer comprises a plurality of first interdigital structures A0 and second interdigital structures B0 which are mutually crossed; the first interdigital structures in the multiple metal layers are electrically connected to serve as a first electrode A of the MOM capacitor, and the second interdigital structures in the multiple metal layers are electrically connected to serve as a second electrode B of the MOM capacitor;
the first interdigital structure A0 in the metal layer Mm closest to the shielding layer 2 among the plurality of metal layers (Mm … … Mn) is shorted with the shielding layer 2; and the second interdigital structure B0 in the metal layer Mm closest to the shielding layer 2 in the plurality of metal layers (Mm … … Mn) is insulated from the shielding layer 2.
As shown in fig. 4, the first interdigital structure a0 in the lowest metal layer Mm is directly electrically connected to the shielding layer 2, and the second interdigital structure B0 in the lowest metal layer Mm is insulated from the shielding layer 2, so as to form a capacitor.
As shown in fig. 5, an equivalent circuit diagram of an MOM capacitor according to an embodiment of the present invention is provided, in which a ground terminal is the substrate 1 shown in fig. 4 in this embodiment. The capacitor Cmom between the first electrode a and the second electrode B is a capacitor formed by sidewalls of a plurality of same-layer interdigital structures in the MOM capacitor. Also included between the first electrode a and the second electrode B is a capacitance Cp2 formed between the shielding layer 2 and the second interdigital structure B0 in fig. 4. Since the first electrode a is directly short-circuited with the shielding layer 2, the parasitic capacitance between the shielding layer 2 and the substrate 1 is also the parasitic capacitance Cp3 between the first electrode a and the ground terminal.
Comparing fig. 5 and the equivalent circuit diagram of fig. 3, it can be seen that the MOM capacitor provided by the embodiment of the present invention shields the parasitic capacitor Cp between the second electrode B and the substrate 1 in fig. 3 due to the existence of the shielding layer, and the parasitic capacitor disappears. And a parasitic capacitance Cp2 connected in parallel is also added between the first electrode a and the second electrode B, and according to the capacitance parallel principle, the capacitance value between the first electrode a and the second electrode B is increased, that is, the capacitance value of the MOM capacitor is increased. It should be noted that the parasitic capacitance Cp3 is also included between the first electrode a and the substrate, but in practical applications, such as in the charge pump example shown below, the parasitic capacitance Cp3 of the first electrode a with respect to the substrate can be accepted. So long as the parasitic capacitance of the second electrode B is reduced or eliminated.
In this embodiment, the material of the shielding layer is not limited, and the shielding layer may have a certain conductivity, so long as the shielding layer can form a parasitic capacitance with a metal layer located thereon, and can be short-circuited, thereby reducing the parasitic capacitance between the metal layer and the substrate. In this embodiment, the shielding layer is a polysilicon layer or a metal layer with relatively low impedance.
In the manufacturing process of the integrated circuit, a plurality of metal layers may be formed, and the metal layer points away from the substrate, and sequentially includes a first metal layer M1, a second metal layer M2 … …, and an nth metal layer Mn.
Referring to fig. 6, fig. 6 shows that the first metal layer M1 in the integrated circuit is fabricated as a whole layer structure for forming the shielding layer 12 in the embodiment of the present invention, and at this time, since the first metal layer M1 is a whole layer structure, a parasitic capacitance Cp3 is formed between the first metal layer M1 and the substrate 11, and a parasitic capacitance Cp2 is formed with the second finger structure in the second metal layer M2 above the first metal layer M1, which is directly shorted with the first finger structure.
In addition, in this embodiment, other metal layers may also be used as the shielding layer, and in this case, none of the metal layers located between the shielding layer and the substrate exists, and thus the metal layer cannot be used as the interdigital structure of the MOM capacitor. So that the utilization of the metal layer is reduced.
Therefore, in another embodiment of the present invention, a polysilicon layer may be additionally disposed between the multiple metal layers and the substrate as a shielding layer, and it should be noted that "adding" in this embodiment does not separately fabricate a polysilicon layer, but employs a polysilicon layer in an integrated circuit in the prior art as a shielding layer in this embodiment, for example, if an MOS transistor exists in an integrated circuit, the polysilicon layer during fabricating a gate of the MOS transistor may extend to a position above the MOM capacitor substrate in this embodiment to be used as a shielding layer, that is, a gate polysilicon layer without other functions in the prior art is used as a shielding layer of the MOM capacitor in this embodiment, and in the fabrication process, the fabrication step of the MOM capacitor in this embodiment is not added.
Referring to fig. 7, fig. 7 shows a structure of a polysilicon layer as a shielding layer, in which the polysilicon layer 22 is located between the substrate 21 and the first metal layer M1. Compared with the MOM capacitor shown in fig. 5, in this embodiment, the metal layer of the MOM capacitor is not occupied, so that the capacitance value of the MOM capacitor is larger.
In this embodiment, the type of the polysilicon is not limited, and optionally, the polysilicon layer is metal silicided polysilicon (silicided poly-Si) with a smaller square resistance, so that the overall resistance of the shielding layer is smaller, and the shielding effect is better.
In the above embodiments of the present invention, the size of the shielding layer is not limited, as long as the shielding layer can shield the parasitic capacitance between the second interdigital structure in the metal layer and the substrate. It should be noted that, when the shielding layer is smaller, the parasitic capacitance between the sidewall of the second interdigital structure located at the edge and the substrate may not be shielded, so that the parasitic capacitance between the second electrode of the MOM capacitor and the substrate cannot be completely shielded.
In order to be able to locate the parasitic capacitance (including the parasitic capacitance formed by the bottom surface and the substrate and the parasitic capacitance formed by the sidewall and the substrate) between the second electrode of the MOM capacitor and the substrate, the projection of the multi-layer metal layer on the plane where the substrate is located in the projection of the shielding layer on the plane where the substrate is located in this embodiment.
In order to avoid the influence on other devices in the integrated circuit caused by the excessively large area of the shielding layer, in this embodiment, the edge of the projection of the shielding layer on the plane of the substrate is at least 2 micrometers larger than the edge of the projection of the multi-layer metal layer on the plane of the substrate. Preferably, in the manufacturing process, the edge of the projection of the shielding layer on the plane of the substrate may be extended by 2 micrometers from the edge of the projection of the multilayer metal layer on the plane of the substrate, which is not limited in this embodiment, and the design may be selected according to the manufacturing of an actual integrated circuit and components in the integrated circuit.
According to the MOM capacitor provided by the invention, the whole shielding layer is formed between the substrate and the multiple metal layers, and the shielding layer at least can shield the parasitic capacitor formed on the opposite surface between the metal layers and the substrate, so that the parasitic capacitor of the MOM capacitor is reduced, the capacitance value of the MOM capacitor is larger under the same area, the capacitance density of the MOM capacitor is increased, and the application of the MOM capacitor is wider.
The invention also provides an integrated circuit comprising the MOM capacitor described in all of the above embodiments.
It should be noted that the specific structure of the integrated circuit is not limited in this embodiment, and as long as the integrated circuit includes the MOM capacitor, the MOM capacitor with the shielding layer described in the above embodiments of the present invention may be adopted, so as to reduce the parasitic capacitance of one electrode to the substrate and increase the capacitance value of the MOM capacitor.
In order to better illustrate the advantages of the MOM capacitor provided in the above embodiments of the present invention, the integrated circuit is used as a charge pump in the embodiments of the present invention. The MOM capacitor with the shielding layer can improve the efficiency of the charge pump. The method comprises the following specific steps:
please refer to fig. 8, 9a, 9b and 10, wherein fig. 8 is a charge pump equivalent circuit diagram in the prior art, fig. 9a is a charge pump equivalent circuit diagram with parasitic capacitance taken into consideration, and Cmom is the MOM capacitance. FIG. 9b is the equivalent circuit diagram of the charge pump after shielding the parasitic capacitance of one electrode terminal of the MOM capacitor; FIG. 10 is a diagram of the equivalent circuit shown in FIG. 8, FIG. 9a, FIG. 9b
And
the timing control diagram of (1).
Neglecting the switching loss, under the ideal clock condition, the charge pump efficiency shown in fig. 8 can reach 100%, and the output voltage:
Vcpout＝2*Vdd
in fig. 9a, the parasitic capacitance Cp of the MOM capacitance at the second electrode B-terminal to ground affects the charge pump efficiency:
in the period of phi 2 being high level, the first electrode A point of MOM capacitor is connected to VDD, the second electrode B point is connected to Cpout, the voltage across the parasitic capacitor Cp of the second electrode B point is Vdd (V) ((V))
During a high level) to Vcpout: (
During high level), the total charge at the point B of the second electrode is:
b-site charge conservation, therefore:
that is to say that the first and second electrodes,
(Cmom+Cp)*Vdd＝Cmom*(Vout–Vdd)+Cp*Vout
to obtain
If Cp/Cmom is 0.1, Vout is 1.91 Vdd, and the efficiency of the charge pump is 95.5%.
It can be seen that the efficiency of the charge pump is affected by the magnitude of the parasitic capacitance of the second electrode B to ground.
In fig. 9B, the MOM capacitor structure with the shielding layer according to the above embodiment of the present invention is adopted, the second electrode B terminal of the MOM capacitor has no parasitic capacitance to ground, i.e. Cp is 0 in the above formula, the charge pump efficiency is not affected, and in the same area, Cp2 between the first electrode a and the second electrode B is added to be connected in parallel with the original MOM capacitor, so that the MOM capacitor density is increased (wherein, the parasitic capacitance Cp3 of the a terminal to ground does not affect the charge pump efficiency).
Therefore, the MOM capacitor with the shielding layer in the embodiment of the invention can improve the efficiency of the charge pump, increase the capacitance value of the MOM capacitor and increase the density of the MOM capacitor in the same area.
Another embodiment of the present invention further provides a cross-coupled charge pump, which has the structure shown in fig. 11, 12a, 12b and 13, wherein fig. 11 is a charge pump equivalent circuit diagram in the prior art, fig. 12a is a charge pump equivalent circuit diagram after considering parasitic capacitance, and Cmom is a MOM capacitor. FIG. 12b is the equivalent circuit diagram of the charge pump after shielding the parasitic capacitance of one electrode terminal of the MOM capacitor; FIG. 13 is a timing control diagram of clock signals Clk1 and Clk2 in the equivalent circuit diagrams shown in FIG. 11, FIG. 12a, FIG. 12 b;
specifically, fig. 11 illustrates a charge pump structure using two flying capacitors (the flying capacitors refer to fast charging capacitors, namely, the capacitor C1 and the capacitor C2 in fig. 11, and the capacitor between a and B in fig. 8 is also a flying capacitor), in this embodiment, the switch transistor M1 and the switch transistor M3 are NMOS, and the switch transistors M2 and M4 are PMOS.
Neglecting the switching loss, under the ideal condition of the clock, the charge pump efficiency can reach 100%, and the output voltage is:
Vout＝Vin+Vdd
similarly, based on the principle of charge conservation, fig. 12a can be derived, where nodes M and N both have parasitic capacitance Cp to ground, the output voltage of the charge pump is:
the parasitic capacitance Cp affects the charge pump efficiency.
As shown in fig. 12b, by using the MOM capacitor structure with shielding layer in the above embodiment of the present invention, the parasitic capacitance of M and N points to ground can be shielded, but the parasitic capacitance of the clock access terminals Clk1 and Clk2 to ground does not substantially affect the charge pump efficiency, and only the size of the inverter needs to be increased to make the inverter have sufficient driving capability.
Therefore, in the embodiment, the MOM capacitor with the shielding layer according to the embodiment of the present invention can improve the efficiency of the charge pump, and increase the capacitance value of the MOM capacitor, so that the density of the MOM capacitor is increased in the same area.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A MOM capacitor, applied to an integrated circuit, the MOM capacitor comprising:
a substrate;
the shielding layer is positioned on the substrate and has a whole-layer structure;
the shielding layer is positioned on one side, away from the substrate, of the shielding layer and is formed by a plurality of metal layers and a plurality of oxidation layers which are in crossed lamination; each metal layer comprises a plurality of first interdigital structures and second interdigital structures which are mutually crossed; the first interdigital structures in the multiple metal layers are electrically connected to serve as first electrodes of the MOM capacitor, and the second interdigital structures in the multiple metal layers are electrically connected to serve as second electrodes of the MOM capacitor;
a first interdigital structure in a metal layer closest to the shielding layer in the plurality of metal layers is in short circuit with the shielding layer; the second interdigital structure in the metal layer closest to the shielding layer in the plurality of metal layers is insulated from the shielding layer;
the projection of the multilayer metal layer on the plane of the substrate is positioned in the projection of the shielding layer on the plane of the substrate;
the integrated circuit also comprises an MOS tube, and a polycrystalline silicon layer used for manufacturing a grid electrode of the MOS tube extends to the upper part of the MOM capacitor substrate and is used as the shielding layer.
2. The MOM capacitor of claim 1, wherein the shield layer is a polysilicon layer.
3. The MOM capacitor of claim 2, wherein the polysilicon layer is a metal-silicided polysilicon layer.
4. The MOM capacitor of claim 1, wherein the shielding layer is a metal layer.
5. The MOM capacitor of any one of claims 1-4, wherein the projected edge of the shielding layer on the plane of the substrate is at least 2 microns further than the projected edge of the multi-layer metal layer on the plane of the substrate.
6. The MOM capacitor of claim 5, wherein the projected edge of the shielding layer on the plane of the substrate is 2 microns further than the projected edge of the multi-layer metal layer on the plane of the substrate.
7. An integrated circuit, comprising: the MOM capacitor of any of claims 1-6.
8. The integrated circuit of claim 7, wherein the integrated circuit is a charge pump.
9. The integrated circuit of claim 8, wherein the charge pump is a cross-coupled charge pump.
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| CN1851921A (en) * | 2005-04-21 | 2006-10-25 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN101465385A (en) * | 2007-12-20 | 2009-06-24 | 联发科技股份有限公司 | Capacitor structure |
| CN101908563A (en) * | 2009-06-03 | 2010-12-08 | 联发科技股份有限公司 | Capacitor and metal-oxide-metal capacitor |
| CN102983117A (en) * | 2011-09-07 | 2013-03-20 | 台湾积体电路制造股份有限公司 | Horizontal interdigitated capacitor structure with vias |
| CN104241244A (en) * | 2013-06-13 | 2014-12-24 | 台湾积体电路制造股份有限公司 | Variable capacitance devices |
| CN106252353A (en) * | 2011-05-24 | 2016-12-21 | 旺宏电子股份有限公司 | There is integrated circuit and the manufacture method thereof of the capacitor of three-dimensional anti-and memorizer |
| CN107154394A (en) * | 2016-03-02 | 2017-09-12 | 扬智科技股份有限公司 | Capacitance structure |
-
2017
- 2017-12-27 CN CN201711444665.1A patent/CN108172565B/en active Active
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|---|---|---|---|---|
| CN1572002A (en) * | 2000-10-17 | 2005-01-26 | 英特尔公司 | Noise suppression for open bit line DRAM architectures |
| CN1851921A (en) * | 2005-04-21 | 2006-10-25 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN101465385A (en) * | 2007-12-20 | 2009-06-24 | 联发科技股份有限公司 | Capacitor structure |
| CN101908563A (en) * | 2009-06-03 | 2010-12-08 | 联发科技股份有限公司 | Capacitor and metal-oxide-metal capacitor |
| CN106252353A (en) * | 2011-05-24 | 2016-12-21 | 旺宏电子股份有限公司 | There is integrated circuit and the manufacture method thereof of the capacitor of three-dimensional anti-and memorizer |
| CN102983117A (en) * | 2011-09-07 | 2013-03-20 | 台湾积体电路制造股份有限公司 | Horizontal interdigitated capacitor structure with vias |
| CN104241244A (en) * | 2013-06-13 | 2014-12-24 | 台湾积体电路制造股份有限公司 | Variable capacitance devices |
| CN107154394A (en) * | 2016-03-02 | 2017-09-12 | 扬智科技股份有限公司 | Capacitance structure |
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| CN108172565A (en) | 2018-06-15 |
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