CN108170634A - A kind of isomerous multi-source data reconstruction transient state reliable treatments method - Google Patents

A kind of isomerous multi-source data reconstruction transient state reliable treatments method Download PDF

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CN108170634A
CN108170634A CN201711427893.8A CN201711427893A CN108170634A CN 108170634 A CN108170634 A CN 108170634A CN 201711427893 A CN201711427893 A CN 201711427893A CN 108170634 A CN108170634 A CN 108170634A
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byte
fpga
dynamic area
bram
data
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CN108170634B (en
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陶飞
邹孝付
左颖
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Beihang University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

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Abstract

The invention discloses a kind of isomerous multi-source data reconstruction transient state reliable treatments method, including：FPGA dynamic area condition adjudgements；FPGA establishes static zones caching of the BRAM realizations to reconstruct instantaneous data；After the completion of reconstruct, FPGA dynamic areas send inquiry frame to static zones, and inquiry frame includes the dynamic area in the coordinate in fpga chip internal physical region and the functional identity of the reconfiguration code run on the dynamic area；The inquiry frame that FPGA static zones parsing dynamic area is sent, and acknowledgement frame is returned, acknowledgement frame includes the data being buffered in BRAM reconstruct moment.Method disclosed by the invention can solve the problems, such as that the data interaction between dynamic area and static zones due to occurring when dynamic area caused by the failure of FPGA dynamic areas or function switch reconstructs is interrupted, and improve the reliability of isomerous multi-source data processing.

Description

A kind of isomerous multi-source data reconstruction transient state reliable treatments method
Technical field
The invention belongs to electronic engineering and computer science, and in particular to a kind of isomerous multi-source data reconstruction transient state can By processing method.
Background technology
With the proposition of national strategy " made in China 2025 ", intelligence manufacture has become the hot spot noun of contemporary China.But It is to realize that intelligence manufacture be unable to do without data, these data more specifically show as the data at manufacture scene, so the live number of manufacture According to reliable acquisition, processing, to exchange with transmission be exactly to realize that the Floor layer Technology of intelligence manufacture supports.The data at scene are manufactured in number According to isomery is shown as in agreement, multi-source is shown as in data volume, how while efficient process isomerous multi-source data, is ensured The reliability of data processing just seems most important.Since FPGA has born hardware concurrent and dynamic restructuring characteristic, The acquisition of data, such as voltage, the electricity of acquisition lathe are completed in one static zones of FPGA internal builds and multiple dynamic areas, static zones Stream, rotating speed, acquire realtime image data and environmental parameter of production line etc.；Each dynamic area runs different Processing Algorithms, Such as 1 working voltage filtering process algorithm of dynamic area, 2 operation image gray proces algorithm of dynamic area, 3 running environment of dynamic area ginseng Several Preprocessing Algorithm etc. can be achieved with the efficient process of isomerous multi-source data in this way.
But manufacture scene, there is certain radiation and ionization, the micro-chip processor including FPGA is all very possible There are the failures such as hardware damage and code " run and fly ", but FPGA can improve the reliability of data processing by dynamic restructuring, It is embodied in when " run and fly " occurs in the code run on some dynamic area, FPGA static zones are stored in by state machine reading Dynamic code in the outer flash of piece, and being re-loaded in the dynamic area of failure, to realize the failure of dynamic area from extensive It is multiple；Or FPGA static zones are read not another dynamic code and are loaded into the dynamic area, are cut with the function of realizing dynamic area It changes.But during dynamic area reconstructs, the data interaction between static zones and dynamic area is to interrupt, even if FPGA dynamics Reconstruct time generally in Millisecond, but for the data processing occasion harsher to requirement of real-time, reconstruct causes Data processing interruption also directly affect the reliability of data processing.Therefore, the present invention proposes a kind of isomerous multi-source data reconstruction Transient state reliable treatments method, the data interaction that this method can solve during FPGA dynamic restructurings between static zones and dynamic area occur The problem of interruption, can realize the reliable treatments of isomerous multi-source data.
Invention content
The technical problem to be solved in the present invention is：A kind of isomerous multi-source data reconstruction transient state reliable treatments method is provided, it should Method can solve the problems, such as that data interaction during FPGA dynamic restructurings between static zones and dynamic area is interrupted, and can realize The reliable treatments of isomerous multi-source data.
The present invention solves its technical problem and following technical scheme is taken to realize：A kind of isomerous multi-source data reconstruction transient state Reliable treatments method, includes the following steps：
Step 1：FPGA dynamic area condition adjudgements, are implemented as follows：
1. it is 1 to establish a width, depth is 1 dual-port BRAM, and under the driving of FPGA master clocks, static zones pass through The numerical value that port A puts the BRAM is high level, and after 10 master clock cycles, judgement is read in static zones by port A The level state of the numerical value of the BRAM：When for high level, show that dynamic area is in restructuring procedure：When for low level, table Bright dynamic area is in non-restructuring procedure；
2. dynamic area under the driving of FPGA master clocks by port B reads and judges the level of the numerical value of the BRAM in real time When for high level, low level is reset in next clock cycle by state for the level state of the numerical value of the BRAM；
3. when there is n dynamic area, it is 1 to need to establish n width in static zones, depth is 1 dual-port BRAM, each The judgement of dynamic zone state is as 1. and 2.；
Step 2：FPGA establishes static zones caching of the data buffer storage BRAM realizations to reconstruct instantaneous data, and specific implementation is such as Under：
1. FPGA establishes static zones a BRAM, when static zones monitor that dynamic area is in restructuring procedure, static zones By pending data buffer storage in this BRAM；
2. FPGA static zones are according to each dynamic area in the coordinate in fpga chip internal physical region and on the dynamic area The difference of the functional identity of the reconfiguration code of operation, respectively by data buffer storage in the different offset address of the BRAM；
Step 3：After the completion of reconstruct, FPGA dynamic areas send inquiry frame to static zones, and frame format is implemented as follows：
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2-11 is data field, wherein byte 2-3 represents the dynamic area on the left side in fpga chip internal physical region The abscissa on upper vertex；Byte 4-5 represents ordinate of the dynamic area in the left upper apex in fpga chip internal physical region；Word Section 6-7 represents abscissa of the dynamic area in the bottom right vertex in fpga chip internal physical region；Byte 8-9 represents the dynamic area In the ordinate of the bottom right vertex in fpga chip internal physical region；The reconstruct that byte 10-11 expressions are run on the dynamic area The functional identity of code；
3. byte 12 is data field end identifier, i.e. hexadecimal 00；
4. byte 13 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte 14-15 is the length of data field, wherein byte 14 is high byte；
6. byte 16-17 is postamble, i.e. hexadecimal 5A, FE；
When inquiring that postamble, i.e. hexadecimal 5A, FE occurs in the data field in frame, need to be inserted into escape before 5A, the FE Character hexadecimal 00；The length of data field does not include the escape character being inserted into；
Step 4：The inquiry frame that FPGA static zones parsing dynamic area is sent needs to turn insertion when frame is inquired in parsing Adopted character removal, obtains the dynamic area in the coordinate in fpga chip internal physical region and the reconstruct generation run on the dynamic area The functional identity of code, then static zones read corresponding data in data buffer storage BRAM；
Step 5：FPGA static zones return to acknowledgement frame to dynamic area, and frame format is implemented as follows：
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2- (n+1) is data field, that is, the data being buffered in when reconstructing in BRAM, wherein n is data byte length；
3. byte n+2 is data field end identifier, i.e. hexadecimal 00；
4. byte n+3 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte n+4, n+5 is the length of data field, wherein byte n+4 is high byte；；
6. byte n+6, n+7 is postamble, i.e. hexadecimal 5A, FE；
When postamble, i.e. hexadecimal 5A, FE occurs in the data field in acknowledgement frame, need to be inserted into escape before 5A, the FE Character hexadecimal 00；The length of data field does not include the escape character being inserted into.
A kind of isomerous multi-source data reconstruction transient state reliable treatments method that the present invention designs is suitable for Xilinx companies Virtex-5FPGA chips.
The advantages of the present invention over the prior art are that：
(1) traditional method that FPGA dynamic restructuring reliabilities are improved using triplication redundancy etc., not only increases FPGA The consumption of resource, and improve merely by the mode of prepare more part the reliability of dynamic area, it is basic without solving reconstruct when Transient problem.The data interaction when present invention can solve FPGA dynamic restructurings between static zones and dynamic area occurs what is interrupted Problem can realize the reliable treatments of isomerous multi-source data.
(2) FPGA dynamic areas condition adjudgement proposed by the present invention, establish BRAM to cache the data and static state during reconstruct Inquiry frame, acknowledgement frame between area and dynamic area can fundamentally solve FPGA reconstruct transient problems.
Description of the drawings
Fig. 1 is the structure diagram of the present invention.
Specific embodiment
Further detailed description is done to the present invention below in conjunction with the accompanying drawings.
The present invention relates to a kind of isomerous multi-source data reconstruction transient state reliable treatments method, using Xilinx companies Virtex-5FPGA chips.This method is asked for the reconstruct transient state of the isomerous multi-source Data processing based on FPGA dynamic restructurings Topic, during the data interaction when reconstruct transient problem of so-called FPGA is exactly FPGA dynamic restructurings between static zones and dynamic area occurs It is disconnected.It is proposed method of the present invention can solve FPGA reconstruct transient problems, realize the reliable treatments of isomerous multi-source data.
The structure diagram of the present invention is as shown in Figure 1, specific embodiment is as follows：
(1) FPGA dynamic areas condition adjudgement, is implemented as follows：
1. it is 1 to establish a width, depth is 1 dual-port BRAM, and under the driving of FPGA master clocks, static zones pass through The numerical value that port A puts the BRAM is high level, and after 10 master clock cycles, judgement is read in static zones by port A The level state of the numerical value of the BRAM：When for high level, show that dynamic area is in restructuring procedure：When for low level, table Bright dynamic area is in non-restructuring procedure；
2. dynamic area under the driving of FPGA master clocks by port B reads and judges the level of the numerical value of the BRAM in real time When for high level, low level is reset in next clock cycle by state for the level state of the numerical value of the BRAM；
3. when there is n dynamic area, it is 1 to need to establish n width in static zones, depth is 1 dual-port BRAM, each The judgement of dynamic zone state is as 1. and 2.；
(2) data buffer storage BRAM realizations are established to the caching of reconstruct instantaneous data in FPGA static zones, are implemented as follows：
1. FPGA establishes static zones a BRAM, when static zones monitor that dynamic area is in restructuring procedure, static zones By pending data buffer storage in this BRAM；
2. FPGA static zones are according to each dynamic area in the coordinate in fpga chip internal physical region and on the dynamic area The difference of the functional identity of the reconfiguration code of operation, respectively by data buffer storage in the different offset address of the BRAM；
(3) after the completion of reconstruct, FPGA dynamic areas send inquiry frame to static zones, and frame format is implemented as follows：
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2-11 is data field, wherein byte 2-3 represents the dynamic area on the left side in fpga chip internal physical region The abscissa on upper vertex；Byte 4-5 represents ordinate of the dynamic area in the left upper apex in fpga chip internal physical region；Word Section 6-7 represents abscissa of the dynamic area in the bottom right vertex in fpga chip internal physical region；Byte 8-9 represents the dynamic area In the ordinate of the bottom right vertex in fpga chip internal physical region；The reconstruct that byte 10-11 expressions are run on the dynamic area The functional identity of code；
3. byte 12 is data field end identifier, i.e. hexadecimal 00；
4. byte 13 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte 14-15 is the length of data field, wherein byte 14 is high byte；
6. byte 16-17 is postamble, i.e. hexadecimal 5A, FE；
When inquiring that postamble, i.e. hexadecimal 5A, FE occurs in the data field in frame, need to be inserted into escape before 5A, the FE Character hexadecimal 00；The length of data field does not include the escape character being inserted into；
(4) the inquiry frame that parsing dynamic area in FPGA static zones is sent is needed when frame is inquired in parsing by the escape word of insertion Symbol removal obtains the dynamic area in the coordinate in fpga chip internal physical region and the reconfiguration code run on the dynamic area Functional identity, then static zones read corresponding data in data buffer storage BRAM；
(5) FPGA static zones return to acknowledgement frame to dynamic area, and frame format is implemented as follows：
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2- (n+1) is data field, that is, the data being buffered in when reconstructing in BRAM, wherein n is data byte length；
3. byte n+2 is data field end identifier, i.e. hexadecimal 00；
4. byte n+3 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte n+4, n+5 is the length of data field, wherein byte n+4 is high byte；；
6. byte n+6, n+7 is postamble, i.e. hexadecimal 5A, FE；
When postamble, i.e. hexadecimal 5A, FE occurs in the data field in acknowledgement frame, need to be inserted into escape before 5A, the FE Character hexadecimal 00；The length of data field does not include the escape character being inserted into.
In conclusion the invention discloses a kind of isomerous multi-source data reconstruction transient state reliable treatments method, including：FPGA is moved State zone state judges；FPGA establishes static zones caching of the BRAM realizations to reconstruct instantaneous data；FPGA dynamic areas are sent out to static zones The acknowledgement frame that the inquiry frame sent and FPGA static zones are returned to dynamic area.This method can be solved based on FPGA dynamic restructurings The reconstruct transient problem of isomerous multi-source Data processing realizes the reliable treatments of isomerous multi-source data.
The content not being described in detail in description of the invention belongs to the prior art well known to professional and technical personnel in the field.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should It is considered as protection scope of the present invention.

Claims (2)

  1. A kind of 1. isomerous multi-source data reconstruction transient state reliable treatments method, it is characterised in that：Include the following steps：
    Step 1：FPGA dynamic area condition adjudgements, are implemented as follows：
    1. it is 1 to establish a width, depth is 1 dual-port BRAM, and under the driving of FPGA master clocks, static zones pass through port The numerical value that A puts the BRAM is high level, and after 10 master clock cycles, static zones are read by port A and judge this The level state of the numerical value of BRAM：When for high level, show that dynamic area is in restructuring procedure：When for low level, show Dynamic area is in non-restructuring procedure；
    2. dynamic area under the driving of FPGA master clocks by port B reads and judges the level shape of the numerical value of the BRAM in real time When for high level, low level is reset in next clock cycle by state for the level state of the numerical value of the BRAM；
    3. when there is n dynamic area, it is 1 to need to establish n width in static zones, and depth is 1 dual-port BRAM, each dynamic The judgement of zone state is as 1. and 2.；
    Step 2：FPGA establishes static zones data buffer storage BRAM realizations to the caching of reconstruct instantaneous data, is implemented as follows：
    1. FPGA establishes static zones a BRAM, when static zones monitor that dynamic area is in restructuring procedure, static zones will treat The data buffer storage of processing is in this BRAM；
    2. FPGA static zones are run according to each dynamic area in the coordinate in fpga chip internal physical region and on the dynamic area Reconfiguration code functional identity difference, respectively by data buffer storage in the different offset address of the BRAM；
    Step 3：After the completion of reconstruct, FPGA dynamic areas send inquiry frame to static zones, and frame format is implemented as follows：
    1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
    2. byte 2-11 is data field, wherein byte 2-3 represents that the dynamic area is pushed up in the upper left in fpga chip internal physical region The abscissa of point；Byte 4-5 represents ordinate of the dynamic area in the left upper apex in fpga chip internal physical region；Byte 6- 7 represent abscissa of the dynamic area in the bottom right vertex in fpga chip internal physical region；Byte 8-9 represents that the dynamic area exists The ordinate of the bottom right vertex in fpga chip internal physical region；The reconstruct generation that byte 10-11 expressions are run on the dynamic area The functional identity of code；
    3. byte 12 is data field end identifier, i.e. hexadecimal 00；
    4. byte 13 is verification, i.e., the logic sum of each byte takes low byte in data field；
    5. byte 14-15 is the length of data field, wherein byte 14 is high byte；
    6. byte 16-17 is postamble, i.e. hexadecimal 5A, FE；
    When inquiring that postamble, i.e. hexadecimal 5A, FE occurs in the data field in frame, need to be inserted into escape character before 5A, the FE Hexadecimal 00；The length of data field does not include the escape character being inserted into；
    Step 4：The inquiry frame that FPGA static zones parsing dynamic area is sent, needs when frame is inquired in parsing by the escape word of insertion Symbol removal obtains the dynamic area in the coordinate in fpga chip internal physical region and the reconfiguration code run on the dynamic area Functional identity, then static zones read corresponding data in data buffer storage BRAM；
    Step 5：FPGA static zones return to acknowledgement frame to dynamic area, and frame format is implemented as follows：
    1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
    2. byte 2- (n+1) is data field, that is, the data being buffered in when reconstructing in BRAM, wherein n is data byte length；
    3. byte n+2 is data field end identifier, i.e. hexadecimal 00；
    4. byte n+3 is verification, i.e., the logic sum of each byte takes low byte in data field；
    5. byte n+4, n+5 is the length of data field, wherein byte n+4 is high byte；
    6. byte n+6, n+7 is postamble, i.e. hexadecimal 5A, FE；
    When postamble, i.e. hexadecimal 5A, FE occurs in the data field in acknowledgement frame, need to be inserted into escape character before 5A, the FE Hexadecimal 00；The length of data field does not include the escape character being inserted into.
  2. 2. a kind of isomerous multi-source data reconstruction transient state reliable treatments method as described in claim 1, it is characterised in that：Described Method is suitable for Xilinx companies Virtex-5FPGA chips.
CN201711427893.8A 2017-12-26 2017-12-26 A kind of isomerous multi-source data reconstruction transient state reliable treatments method Expired - Fee Related CN108170634B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108804232A (en) * 2018-06-26 2018-11-13 郑州云海信息技术有限公司 A kind of method, host server and the system of supporting high in the clouds FPGA to dispose
CN110045691A (en) * 2019-03-13 2019-07-23 东北大学 A kind of multitasking fault monitoring method of multi-source heterogeneous big data
CN112214448A (en) * 2020-10-10 2021-01-12 中科声龙科技发展（北京）有限公司 Data dynamic reconstruction circuit and method of heterogeneous integrated workload proving operation chip

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110264888A1 (en) * 2010-04-23 2011-10-27 Utah State University Dynamically Reconfigurable Systolic Array Accelorators
US8271924B1 (en) * 2006-05-05 2012-09-18 Altera Corporation Self-configuring components on a device
US20140040911A1 (en) * 2001-07-20 2014-02-06 Searchlite Advances Llc Dynamic job processing based on estimated completion time and specified tolerance time
CN104008024A (en) * 2014-06-12 2014-08-27 北京航空航天大学 Dynamic reconstruction technology application platform based on FPGA
CN104603750A (en) * 2012-08-30 2015-05-06 微软公司 Layout and execution of software applications using BPRAM
CN106372032A (en) * 2016-09-08 2017-02-01 北京航空航天大学 FPGA (field programmable gate array) dynamic reconstruction method
CN106682294A (en) * 2016-12-15 2017-05-17 西安交通大学 Layout method for dynamically reconfigurable FPGA

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140040911A1 (en) * 2001-07-20 2014-02-06 Searchlite Advances Llc Dynamic job processing based on estimated completion time and specified tolerance time
US8271924B1 (en) * 2006-05-05 2012-09-18 Altera Corporation Self-configuring components on a device
US20110264888A1 (en) * 2010-04-23 2011-10-27 Utah State University Dynamically Reconfigurable Systolic Array Accelorators
CN104603750A (en) * 2012-08-30 2015-05-06 微软公司 Layout and execution of software applications using BPRAM
CN104008024A (en) * 2014-06-12 2014-08-27 北京航空航天大学 Dynamic reconstruction technology application platform based on FPGA
CN106372032A (en) * 2016-09-08 2017-02-01 北京航空航天大学 FPGA (field programmable gate array) dynamic reconstruction method
CN106682294A (en) * 2016-12-15 2017-05-17 西安交通大学 Layout method for dynamically reconfigurable FPGA

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
RIKUS LE ROUX, ET AL: "《Block RAM Implementation of a Reconfigurable Real-Time PID Controller》", 《2012 IEEE 14TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS》 *
杜林，邹孝付: "《基于FPGA的动态重构技术研究与实现》", 《自动化与仪器仪表》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108804232A (en) * 2018-06-26 2018-11-13 郑州云海信息技术有限公司 A kind of method, host server and the system of supporting high in the clouds FPGA to dispose
CN110045691A (en) * 2019-03-13 2019-07-23 东北大学 A kind of multitasking fault monitoring method of multi-source heterogeneous big data
CN110045691B (en) * 2019-03-13 2021-03-16 东北大学 Multi-task processing fault monitoring method for multi-source heterogeneous big data
CN112214448A (en) * 2020-10-10 2021-01-12 中科声龙科技发展（北京）有限公司 Data dynamic reconstruction circuit and method of heterogeneous integrated workload proving operation chip
CN112214448B (en) * 2020-10-10 2024-04-09 声龙(新加坡)私人有限公司 Data dynamic reconstruction circuit and method of heterogeneous integrated workload proving operation chip

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