CN108153698A - Data interactive method - Google Patents
Data interactive method Download PDFInfo
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- CN108153698A CN108153698A CN201711131883.XA CN201711131883A CN108153698A CN 108153698 A CN108153698 A CN 108153698A CN 201711131883 A CN201711131883 A CN 201711131883A CN 108153698 A CN108153698 A CN 108153698A
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- China
- Prior art keywords
- data
- byte
- gate array
- spi
- programmable gate
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
Data interactive method provided by the invention, includes the following steps：Step 1, the spi interfaces of processor are set as main side by the spi interfaces of configuration processor；Step 2, the spi interfaces of field programmable gate array are configured, the spi interfaces of field programmable gate array are set as to carry out data interaction from end, processor and field programmable gate array by main and slave terminal；Step 3, data interactive mode and agreement, main side active transmission data packet, from end by interrupt mode come transmission data packet are formulated；Main and slave terminal carries out data interaction as unit of data packet.Compared with prior art, beneficial effects of the present invention are as follows：The data interaction of production domesticization processor and field programmable gate array is present invention can be suitably applied to, the transmission mode of data interaction is full duplex, and peak transfer rate has filled up the blank of domestic related field up to tens of Mbps.
Description
Technical field
The present invention relates to embedded system field, more particularly to a kind of processor and field programmable gate array number
According to interactive method.
Background technology
As the consciousness of independence and controllability is continuously improved, the development for the electronic component that domesticizes is increasingly swift and violent, especially
CPU, FPGA, DSP for core etc. have huge growth requirement and application prospect.For the embedded system of complete set
System, the data interaction of each core devices is extremely important.Production domesticization processor at this stage, general purpose interface bus is less, past
Toward processor module itself cannot be directly invoked data interaction is done directly with other devices.And for production domesticization FPGA (scenes
Programmable gate array), common I/O port itself is only existed, with greater need for inventing and design a set of perfect method and other devices
Part completes data interaction.
Invention content
For the defects in the prior art, the object of the present invention is to provide a kind of data interactions for solving above-mentioned technical problem
Method.
In order to solve the above technical problems, data interactive method provided by the invention, includes the following steps：
Step 1, the spi interfaces of processor are set as main side by the spi interfaces of configuration processor；
Step 2, the spi interfaces of field programmable gate array are configured, the spi of field programmable gate array is connect
Mouth is set as carrying out data interaction from end, processor and field programmable gate array by main and slave terminal；
Step 3, data interactive mode and agreement are formulated, active transmission data packet in main side is sent out from end by interrupt mode
Send data packet；Main and slave terminal carries out data interaction as unit of data packet.
Preferably, step 1 includes：
Step 1.1, by the spi interfaces of driver deployment process device, spi parameters are set；
Step 1.2, configuration processor is interrupted, and the data packet since end is received in a manner of interrupt response.
Preferably, in step 1.1, parameter includes frequency division coefficient and principal and subordinate is set.
Preferably, in step 2, according to spi agreements, programmable gate array writes spi from end interface module at the scene,
The spi interface pins of processor and the spi interface pins of field programmable gate array are interconnected.
Preferably, step 3 includes：
Step 3.1, interactive mode is formulated, main side actively generates clock and chip selection signal when sending, active transmission data,
Data are received by interrupt mode when receiving；From end when sending by interrupt mode transmission data, when receiving according to when
Clock and chip selection signal receive data；
Step 3.2, formulate data-bag interacting agreement, processor and field programmable gate array by spi interfaces with
The form of data packet carries out data interaction；Wherein
Data pack protocol is：1st byte is data packet head, and the 2nd byte is data packet length low byte, and the 3rd byte is number
According to packet length high byte, the 4th byte is command byte, and the 5th byte is reserve bytes, and byte thereafter is effective data packets word
Section.
Preferably, in step 5, data interaction uses full-duplex mode.
Compared with prior art, beneficial effects of the present invention are as follows：It present invention can be suitably applied to production domesticization processor and scene
The data interaction of programmable gate array, the transmission mode of data interaction is full duplex, and peak transfer rate is up to tens of
Mbps has filled up the blank of domestic related field.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature mesh of the invention
And advantage will become more apparent upon.
Fig. 1 is data interactive method processor of the present invention and field programmable gate array connection diagram；
Fig. 2 is data interactive method flow diagram of the present invention；
Fig. 3 is data interactive method spi sequence diagrams of the present invention；
Fig. 4 is data interactive method agreement schematic diagram of the present invention.
Specific embodiment
With reference to specific embodiment, the present invention is described in detail.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill to this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection domain.
The production domesticization processor model used in the embodiment of this example is Godson 1B, and domesticize field programmable logic
The micro- HWD2V6000 of gate array (Field-Programmable Gate Array) model China.Practical connection diagram is as schemed
Shown in 1, by four lead-foot-lines of the spi interfaces of Godson 1B processors be connected to four of field programmable gate array it is common
I/O pin, wherein ss are chip select pin, and sck is clock pins, and mosi is exported for main side from end input data pin, based on miso
End is inputted from end output data pin；In addition, an external interrupt pin of Godson 1B is connected to field programmable gate
A piece common I/O pin of array.
Fig. 2 shows one embodiment of the present invention method, the method specifically includes following steps：
Step 1：
The spi interfaces at Godson 1B ends are configured.According to Godson 1B handbook contents, the d4 of SPCR registers is put 1, meets spi
Mouth is set as main side；By d3, d2 position 11 of SPCR registers, make the clock polarity of spi interfaces and phase be set as cpol=1,
Cpha=1 patterns；By d1, d0 position of SPCR registers, d1, d0 position 00,01 of SPER registers, make the frequency dividing of spi interfaces
Coefficient is set as 8, and since the source clock of frequency dividing is the half of DDR_CLK (125Mhz), then the clock frequency sck of spi is in example
15.625Mhz。
The external interrupt of Godson 1B is configured.According to Godson 1B handbook content, external interrupt used is enabled and is set as effective,
And down trigger pattern is set as high level trigger mode.
Step 2：
Programmable gate array (the micro- HWD2V6000 of China) end at the scene, field-programmable is completed by writing spi interfaces
The spi interfaces at field programmable gate array end are set as from end by the data transmit-receive at logic gate array end；Due to using asynchronous
Transceiver mode, at the scene programmable gate array end the treble frequency (i.e. 62.5Mhz) of sck is used to receive data as from end
Asynchronous-sampling clock.
Step 3：
Data interaction agreement is formulated, data interaction is as unit of data packet, Godson 1B active transmission data packets, Hua Wei
HWD2V6000 is by interrupt mode come transmission data packet.
Formulate interactive mode.Main side actively generates clock signal sck and chip selection signal ss when sending, on data line mosi
Active transmission data.Data are received by interrupt mode when main side receives.From end when sending by interrupt mode transmission data,
After main side receives interruption, it is divided into two kinds of situations：One main side is in itself in hair number at this time, i.e., there are clock line and data line, then
From end directly on data line miso transmission data；Two at this time main side not hair number, then need main side receive interruption after clock is provided
Signal sck and chip selection signal ss, from end after confirmation has sck, ss on data line miso transmission data.From end receive when root
Data are received according to clock and chip selection signal.Specific sequence diagram is as shown in Figure 3.
Formulate data-bag interacting agreement.Godson 1B is carried out in the form of data packet with the micro- HWD2V6000 of China by spi interfaces
Data interaction, data pack protocol are：1st byte is data packet head, and the 2nd byte is data packet length low byte, and the 3rd byte is number
According to packet length high byte, the 4th byte is command byte, and the 5th byte is reserve bytes, behind byte be valid data packet byte.
Since length byte is two bytes, so maximum data packet is 65536 bytes.Specific data pack protocol is as shown in Figure 4.
As it can be seen that this example provides a kind of production domesticization processor (Godson 1B) and production domesticization field programmable gate array
The method of (the micro- HWD2V6000 of China) data interaction, data-bag interacting use full-duplex mode, and duplexing rate is 31.25Mbps.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or change within the scope of the claims, this not shadow
Ring the substantive content of the present invention.In the absence of conflict, the feature in embodiments herein and embodiment can arbitrary phase
Mutually combination.
Claims (6)
1. a kind of data interactive method, which is characterized in that include the following steps：
Step 1, the spi interfaces of processor are set as main side by the spi interfaces of configuration processor；
Step 2, the spi interfaces of field programmable gate array are configured, the spi interfaces of field programmable gate array are set
To carry out data interaction from end, processor and field programmable gate array by main and slave terminal；
Step 3, data interactive mode and agreement are formulated, active transmission data packet in main side sends number from end by interrupt mode
According to packet；Main and slave terminal carries out data interaction as unit of data packet.
2. data interactive method according to claim 1, which is characterized in that step 1 includes：
Step 1.1, by the spi interfaces of driver deployment process device, spi parameters are set；
Step 1.2, configuration processor is interrupted, and the data packet since end is received in a manner of interrupt response.
3. data interactive method according to claim 2, which is characterized in that in step 1.1, parameter include frequency division coefficient and
Principal and subordinate is set.
4. data interactive method according to claim 1, which is characterized in that in step 2, according to spi agreements, at the scene may be used
Programmed logic gate array writes spi from end interface module, by the spi interface pins and field programmable gate array of processor
Spi interface pins interconnection.
5. data interactive method according to claim 1, which is characterized in that step 3 includes：
Step 3.1, interactive mode is formulated, main side actively generates clock and chip selection signal when sending, and active transmission data is connecing
Time receiving receives data by interrupt mode；From end when sending by interrupt mode transmission data, when receiving according to clock and
Chip selection signal receives data；
Step 3.2, data-bag interacting agreement is formulated, processor is with field programmable gate array by spi interfaces with data
The form of packet carries out data interaction；Wherein
Data pack protocol is：1st byte is data packet head, and the 2nd byte is data packet length low byte, and the 3rd byte is data packet
Length high byte, the 4th byte are command byte, and the 5th byte is reserve bytes, and byte thereafter is valid data packet byte.
6. data interactive method according to claim 5, which is characterized in that in step 5, data interaction uses full duplex mould
Formula.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711131883.XA CN108153698A (en) | 2017-11-15 | 2017-11-15 | Data interactive method |
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| CN201711131883.XA CN108153698A (en) | 2017-11-15 | 2017-11-15 | Data interactive method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109783409A (en) * | 2019-01-24 | 2019-05-21 | 北京百度网讯科技有限公司 | Method and apparatus for handling data |
| CN112559430A (en) * | 2020-12-24 | 2021-03-26 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | CPU and FPGA data interaction method and system suitable for narrow-band channel unit |
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| US20090172216A1 (en) * | 2006-06-20 | 2009-07-02 | Freescale Semiconductor. Inc. | Method and apparatus for transmitting data in a flexray node |
| CN202870808U (en) * | 2012-07-04 | 2013-04-10 | 四川九洲电器集团有限责任公司 | FPGA realization device of SPI serial port module |
| CN104020704A (en) * | 2014-06-19 | 2014-09-03 | 大连理工大学 | Mini embedded controller device and method for simulating SPI interface through I/O port |
| CN104077258A (en) * | 2014-07-03 | 2014-10-01 | 成都智科通信技术有限公司 | SPI (Serial Peripheral Interface) and Localbus intercommunication method and application thereof |
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2017
- 2017-11-15 CN CN201711131883.XA patent/CN108153698A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090172216A1 (en) * | 2006-06-20 | 2009-07-02 | Freescale Semiconductor. Inc. | Method and apparatus for transmitting data in a flexray node |
| CN202870808U (en) * | 2012-07-04 | 2013-04-10 | 四川九洲电器集团有限责任公司 | FPGA realization device of SPI serial port module |
| CN104020704A (en) * | 2014-06-19 | 2014-09-03 | 大连理工大学 | Mini embedded controller device and method for simulating SPI interface through I/O port |
| CN104077258A (en) * | 2014-07-03 | 2014-10-01 | 成都智科通信技术有限公司 | SPI (Serial Peripheral Interface) and Localbus intercommunication method and application thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109783409A (en) * | 2019-01-24 | 2019-05-21 | 北京百度网讯科技有限公司 | Method and apparatus for handling data |
| CN112559430A (en) * | 2020-12-24 | 2021-03-26 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | CPU and FPGA data interaction method and system suitable for narrow-band channel unit |
| CN112559430B (en) * | 2020-12-24 | 2022-07-05 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | CPU and FPGA data interaction method and system suitable for narrow-band channel unit |
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Application publication date: 20180612 |