CN108112069B

CN108112069B - Method and system for maintaining synchronization of TDD-L TE equipment

Info

Publication number: CN108112069B
Application number: CN201711372820.3A
Authority: CN
Inventors: 卓新疆
Original assignee: Ankexun Fujian Technology Co ltd
Current assignee: Ankexun Fujian Technology Co ltd
Priority date: 2017-12-19
Filing date: 2017-12-19
Publication date: 2020-08-04
Anticipated expiration: 2037-12-19
Also published as: CN108112069A; CN111954295A; CN111954295B

Abstract

The invention provides a method and a system for maintaining synchronization of TDD-L TE equipment, wherein the method comprises the steps of recording each second pulse signal by a CP L D under the condition of receiving a GPS signal, acquiring a calibration value for storage, calibrating and synchronizing the second pulse signals by a clock chip according to a reference clock signal, outputting a first synchronous second pulse signal, acquiring a first synchronous second pulse signal from the clock chip by a processor according to a preset strategy for synchronization under the condition of not receiving the GPS signal, acquiring a second synchronous second pulse signal from the clock chip for synchronization, acquiring a second synchronous second pulse signal from the CP L D for synchronization, acquiring a third synchronous second pulse signal from the CP L D for synchronization, acquiring the second synchronous second pulse signal in an air interface synchronization mode, and outputting the third synchronous second pulse signal by the CP L D according to the last second pulse signal and the calibration value recorded by the CP L D, thereby realizing the synchronization of the equipment under the condition of not having the GPS signal.

Description

Method and system for maintaining synchronization of TDD-L TE equipment

Technical Field

The invention relates to the field of TDD-L TE network application, in particular to a method and a system for maintaining the synchronization of TDD-L TE equipment.

Background

With the rapid development of 4G networks, especially the rapid development of the TDD-L TE network by the china mobile, the TDD-L TE system is extended to many related new products, such as positioning products of TDD-L TE, fence products of TDD-L TE, emergency communication vehicles of TDD-L TE, frame code base stations, etc.

The TDD-L TE network requires synchronization between base stations, and also between base stations and terminals, TD-L TE is a TDD system, if the time between the base stations is not synchronous, the interference of uplink and downlink cross time slots can be caused, and the network performance is seriously affected, therefore, the synchronization between the base stations needs to be synchronized, the synchronization is divided into time synchronization and clock synchronization, the clock synchronization mainly refers to ground clock synchronization and radio frequency carrier synchronization, the TDD-L TE network needs both frequency synchronization and time synchronization, and the time synchronization of TDD-L TE mainly refers to OFDM symbol alignment, SFN alignment and uplink and downlink switching alignment of a physical layer.

The first kind is based on TDM, mainly PDH/SDH/SONET, the mode is mainly used for clock synchronization, the second kind is based on PTN, mainly synchronous ether, TOP, 1588v2, the synchronization can only be frequency synchronization with TOP, 1588v2 can perform frequency synchronization and time synchronization under the condition of high time service precision, the third kind is based on global positioning system, mainly referring to GPS or Beidou, the precision of the time synchronization is highest in the current mode, a large amount of TDD-L TE network system, the fourth kind is air interface synchronization, mainly referring to TDD-L TE system, the base station can receive air interface signals of adjacent areas, analyze SFN and SF, perform synchronization according to SFN and SF, as the synchronization source base station in figure 1 is synchronized with GPS, the base station 1 and the base station 2 are synchronized with the synchronization source base station by using air interface signals, and the mode is also called as sniffer mode.

Currently, TDD-L TE related products are synchronized mainly by means of GPS synchronization and sniffer synchronization, as shown in fig. 2, the left side of a processor in the figure is GPS synchronization, and the right side of the processor is sniffer air interface synchronization, however, fence products, positioning products and emergency communication vehicles often come in places with complex environments, and may not receive GPS signals or downlink signals of neighboring areas, so that there is no way to synchronize by using GPS or sniffer, and the system cannot normally operate, and at this time, a system capable of replacing GPS or sniffer to generate 1pps pulse or SFN indication to maintain normal operation of the equipment is needed.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method and a system for maintaining the synchronization of TDD-L TE equipment, which can ensure the synchronization of the equipment under the condition of no GPS signal.

In order to solve the technical problems, the invention adopts the technical scheme that:

a method for maintaining synchronization of TDD-L TE equipment comprises the following steps:

the clock chip is used for respectively sending second pulse signals generated according to the GPS signals to a clock chip and a CP L D under the condition that the GPS signals can be received, wherein the CP L D records each second pulse signal, acquires a calibration value according to a count value between every two second pulse signals and stores the calibration value, and meanwhile, the clock chip carries out calibration synchronization on the second pulse signals according to a reference clock signal and outputs first synchronous second pulse signals aligned with the second pulse signals;

under the condition that the GPS signal cannot be received, the processor acquires the first synchronous second pulse signal from the clock chip for synchronization according to a preset strategy, or acquires the second synchronous second pulse signal from the CP L D for synchronization, or acquires the third synchronous second pulse signal from the CP L D for synchronization;

acquiring a trigger signal by acquiring air interface signal synchronization of an adjacent cell, then calibrating and synchronizing the trigger signal according to the calibration value stored in the CP L D, and outputting a second synchronous pulse per second signal aligned with the pulse per second signal;

wherein the CP L D outputs a third sync pulse-per-second signal aligned with the pulse-per-second signal according to the last pulse-per-second signal recorded by the CP L D and the calibration value.

The invention provides another technical scheme as follows:

a synchronization maintenance system for a TDD-L TE device, comprising:

the clock chip is used for receiving a pulse per second signal generated according to the GPS signal; calibrating and synchronizing the pulse per second signal according to a reference clock signal, and outputting a first synchronous pulse per second signal aligned with the pulse per second signal;

CP L D, which is used for receiving the second pulse signal generated according to GPS signal, recording each second pulse signal, and obtaining the calibration value according to the counting value between each second pulse signal and then storing the calibration value, and carrying out calibration synchronization on the trigger signal obtained by obtaining the air interface signal synchronization of the adjacent area according to the stored calibration value, and outputting the second synchronous second pulse signal aligned with the second pulse signal, and outputting the third synchronous second pulse signal aligned with the second pulse signal according to the last second pulse signal recorded by the calibration value;

and the processor is used for acquiring the first synchronous second pulse signal from the clock chip for synchronization, acquiring the second synchronous second pulse signal from the CP L D for synchronization, or acquiring the third synchronous second pulse signal from the CP L D for synchronization according to a preset strategy under the condition that the GPS signal cannot be received.

The clock chip provided by the invention has the beneficial effects that the clock chip can calibrate and synchronously output the first synchronous second pulse synchronous with the second pulse signal based on the second pulse signal generated by the GPS signal, simultaneously, the second synchronous second pulse is synchronously acquired by utilizing an air interface under the condition that the air interface signal of the adjacent region can be acquired through the CP L D, and the third synchronous second pulse is acquired by utilizing a self counter under the condition that the air interface signal of the adjacent region cannot be acquired.

Drawings

Fig. 1 is a schematic diagram of an air interface synchronization principle in the prior art;

FIG. 2 is a schematic diagram of information interaction in a prior art TDD-L TE device synchronization process;

FIG. 3 is a flow chart of the synchronization maintaining method of TDD-L TE equipment according to the present invention;

fig. 4 is a flowchart illustrating a synchronization maintaining method for TDD-L TE devices according to a first embodiment of the present invention;

FIG. 5 is a schematic diagram of signal interaction for implementing the first 1PPS output by the clock chip in the first embodiment of the invention;

fig. 6 is a schematic diagram of signal interaction between the CP L D obtaining a calibration value and performing synchronization maintenance based on the calibration value according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a structure composition and signal interaction for implementing pulse per second output by a clock chip in the third embodiment of the present invention;

fig. 8 is a schematic diagram of the structural composition and signal interaction of the CP L D for implementing pulse-per-second output according to the third embodiment of the present invention;

fig. 9 is a flowchart illustrating a process of maintaining a handover operation according to a third embodiment of the present invention.

Detailed Description

In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

The most key concept of the invention is that based on the pulse per second signal generated by the GPS signal, the clock chip acquires the first synchronous pulse per second signal, and the CP L D acquires the second synchronous pulse per second signal and the third synchronous pulse per second signal, so that the equipment can flexibly select one of the second synchronous pulse per second signal and the third synchronous pulse per second signal to keep accurate synchronization when the GPS signal cannot be received.

The technical terms related to the invention are explained as follows:

referring to fig. 3, the present invention provides a method for maintaining synchronization of TDD-L TE devices, including:

The device has the advantages that the first synchronous second pulse signal or the second synchronous second pulse signal or the third synchronous second pulse signal can be obtained according to a preset strategy for keeping the device synchronous and ensuring accurate synchronization so as to maintain the normal operation of the device when the device cannot receive the GPS signal.

Further, the preset policy is:

under the condition that an air interface signal of an adjacent region can be obtained, synchronizing by obtaining the second synchronous second pulse signal;

under the condition that the air interface signal of the adjacent region cannot be acquired, the first synchronous second pulse signal is preferentially acquired for synchronization; and when the first synchronous second pulse signal cannot be acquired, acquiring the third synchronous second pulse signal for synchronization.

According to the description, the synchronization precision GPS synchronization > air interface synchronization > clock chip synchronization > CP L D counting synchronization is comprehensively considered, the synchronization strategy is established, the synchronization signal output required time is longer than the air interface synchronization < CP L D counting synchronization < clock chip synchronization, and the equipment can acquire the synchronization signal in time and can also ensure higher synchronization precision.

Further, the clock chip calibrates and synchronizes the pulse per second signal according to a reference clock signal, and outputs a first synchronized pulse per second signal aligned with the pulse per second signal, specifically:

the clock chip receives the pulse-per-second signal and a reference clock signal output by the constant-temperature crystal oscillator;

and the clock chip takes the reference clock signal as a reference, and adjusts the digital phase-locked loop of the clock chip by continuously training the pulse per second signal so as to output a first synchronous pulse per second signal which is synchronous with the frequency and the phase of the pulse per second signal.

From the above description, it can be known that the chip is trained based on the high-stability pulse-per-second signal generated by the GPS signal and the high-precision low-jitter reference clock signal, so as to ensure that the chip can output the high-precision first synchronous pulse-per-second signal which is synchronous with both the frequency and the phase of the pulse-per-second signal for a long time, and prepare for later-stage selection of equipment synchronization for replacing GPS synchronization or air interface synchronization.

Further, the CP L D records each pulse-per-second signal, and obtains a calibration value according to a count value between each pulse-per-second signal, and stores the calibration value, specifically:

the CP L D takes a reference clock signal output by the constant temperature crystal oscillator as a main clock, records the count value between each second pulse signal received through the main clock, and records the phase position of each second pulse signal;

after the calibration time is reached, the count value is acquired and stored in F L ASH as a calibration value.

From the above description, the CP L D can obtain the pulse-per-second signal based on the high-precision GPS signal, use the high-precision low-jitter reference clock signal as the clock source of the counter, and obtain the calibration value for the later synchronization maintenance by recording the count value between the received pulse-per-second signals, so as to ensure that the second synchronization pulse and the third synchronization pulse obtained in the later period can be synchronized with the pulse-per-second signal of the GPS signal as much as possible, thereby improving the precision of the later synchronization maintenance.

Further, the method also comprises the following steps:

the GPS module receives the GPS signal and then generates a pulse per second signal and a world clock signal;

the GPS module sends the world clock signal to a processor;

the processor records the received world clock signal;

under the condition that the GPS signal can not be received, the processor calculates and maintains the world clock signal through the reference clock signal according to the recorded world clock signal;

and the processor performs physical layer air interface symbol alignment, subframe alignment and radio frequency switch uplink and downlink switching indication according to the acquired first synchronous second pulse signal, second synchronous second pulse signal or third synchronous second pulse signal and the calculated world clock signal until the GPS signal is recovered.

As can be seen from the above description, the lost output of the world clock signal is calculated and maintained at the same time, so that the device can also acquire the world clock signal and the pulse per second signal to perform symbol alignment of a physical layer gap, subframe alignment, and uplink and downlink switching indication of the radio frequency switch under the condition that the device cannot receive the GPS signal, so as to ensure normal operation of the device.

Further, the obtaining of the trigger signal by obtaining the synchronization of the air interface signal of the neighboring cell specifically includes:

the equipment receives a downlink air interface signal of a neighboring cell;

the equipment obtains the SFN and the SF through the physical layer according to the analysis of the downlink empty port signal, generates a trigger pulse corresponding to the SFN through interruption, and sends the trigger pulse corresponding to the SFN to the CP L D.

As can be seen from the above description, air interface synchronization can be performed based on the air interface signal of the neighboring cell, so as to obtain the trigger pulse, and the CP L D can output the third synchronous pulse per second according to the trigger pulse.

The invention provides another technical scheme as follows:

a synchronization maintenance system for a TDD-L TE device, comprising:

From the above description, the invention has the advantages that the synchronization keeping system of the TDD-L TE equipment is provided, the clock chip of the system is used for acquiring the first synchronous second pulse signal, the CP L D is used for acquiring the second synchronous second pulse signal and the third synchronous second pulse signal, and when the GPS synchronous signal cannot be received by the equipment, the synchronous second pulse signal can be flexibly acquired from the clock chip or the CP L D through the processor according to the preset strategy, so that the equipment is synchronized, the normal operation of the equipment is maintained, and the synchronization precision is high.

Further, the preset policy is:

Further, the clock chip includes:

the first receiving circuit is used for receiving the pulse per second signal and a reference clock signal output by the constant temperature crystal oscillator, and receiving the reference clock signal output by the constant temperature crystal oscillator;

and the phase-locked loop circuit is used for adjusting a digital phase-locked loop of the phase-locked loop circuit by continuously training the pulse per second signal by taking the reference clock signal as a reference so as to output a first synchronous pulse per second signal which is synchronous with the frequency and the phase of the pulse per second signal.

Further, the CP L D includes:

the second receiving circuit is used for receiving the pulse per second signal and the reference clock signal output by the constant temperature crystal oscillator, and receiving the reference clock signal output by the constant temperature crystal oscillator;

the recording unit is used for taking a reference clock signal output by the constant-temperature crystal oscillator as a main clock, recording a count value between each second pulse signal received through the main clock, and recording the phase position of each second pulse signal;

and the calibration value acquisition unit is used for acquiring the count value stored in the F L ASH as the calibration value after the calibration time is reached.

Further, the CP L D further includes:

and a synchronous signal acquisition unit for outputting a third synchronous second pulse aligned with the second pulse signal of the GPS module according to the phase position of the last second pulse signal recorded by the CP L D and the calibration value acquired from the F L ASH.

Further, the system further comprises:

the GPS module is used for receiving the GPS signal and then generating a pulse per second signal and a world clock signal; and sending the world clock signal to a processor;

the processor is used for recording the received world clock signal; under the condition that the GPS signal can not be received, the processor calculates and maintains the world clock signal through the reference clock signal according to the recorded world clock signal; and according to the acquired first synchronous second pulse signal, the acquired second synchronous second pulse signal or the acquired third synchronous second pulse signal and the calculated world clock signal, performing physical layer air interface symbol alignment, subframe alignment and radio frequency switch uplink and downlink switching indication until the GPS signal is recovered.

Further, the system further comprises:

an air interface synchronization unit, configured to receive a downlink air interface signal of a neighboring cell;

Example one

Referring to fig. 3 to 6, this embodiment provides a method for maintaining synchronization of TDD-L TE devices, which can ensure that TDD-L TE devices such as fence products, positioning products, emergency communication vehicles, etc. do not receive GPS signals or downlink signals of neighboring cells when entering a complex environment, such as a place with a relatively poor GPS signal environment, such as a cave, a tunnel, an underground garage, etc., and therefore the system cannot operate normally due to no way of using GPS or sniffer to synchronize.

The method of the embodiment is implemented based on that a TDD-L TE device is internally provided with a GPS module, a clock chip, a CP L D, a microprocessor (such as an ARM (STM32), abbreviated as M3), and a high-precision crystal oscillator (OCXO, such as a 10M constant temperature crystal oscillator).

Specifically, referring to fig. 4, the method may include the following steps:

s1, a preset synchronization strategy can be set according to requirements in a self-defined manner, the synchronization mode can be automatically or manually switched according to specific conditions, and the actual requirements of a user can be met as much as possible.

The synchronization precision can be comprehensively considered, namely GPS synchronization, air interface synchronization, clock chip synchronization and CP L D counting synchronization, the time length required by synchronous signal output is realized, GPS synchronization, air interface synchronization, CP L D counting synchronization and clock chip synchronization are realized, and a synchronization strategy is formulated.

Optionally, the synchronization policy is:

when the device does not receive a GPS signal,

under the condition that an air interface signal of the adjacent region can be obtained, a second synchronous pulse per second signal is obtained from the CP L D for synchronization;

under the condition that an air interface signal of an adjacent region cannot be acquired, a first synchronous second pulse signal is preferentially acquired from a clock chip for synchronization;

when the air interface signal of the adjacent cell cannot be acquired and the first synchronous second pulse signal cannot be acquired from the clock chip (the clock chip cannot successfully output the first synchronous second pulse signal), the third synchronous second pulse signal is acquired from the CP L D for synchronization.

It can be known that, when the device cannot receive the GPS signal, the air interface synchronization with the highest synchronization accuracy is considered first, and if the air interface synchronization cannot be achieved, the clock synchronization is performed, and if the clock synchronization cannot be achieved, the synchronization is achieved through the CP L D according to its own counter.

The synchronization strategy can ensure that the equipment can acquire the synchronization signal in time and can also ensure higher synchronization precision.

S2, under the condition that the GPS signal can be normally received, the GPS module sends a pulse per second signal (1PPS) and a universal clock signal (UTC) generated according to the GPS signal to a clock chip and a CP L D respectively;

when the device can receive the GPS signal, the device firstly carries out GPS synchronization, and the 1PPS output by the GPS module is divided into a path to be sent to a clock holding chip and a CP L D to be carried out 1PPS holding and clock holding besides being sent to a physical layer of the device for synchronization.

S3, the CP L D records the phase position of each 1PPS after receiving the 1PPS continuously sent by the GPS module, and simultaneously records the count value between the received 1PPS to obtain the calibration value and stores the phase position and the calibration value of each 1 PPS;

specifically, referring to fig. 6, the process of acquiring the calibration value by the CP L D includes:

after the device is powered on, the CP L D receives a second pulse of a GPS module or a TRIG (such as 40ms) pulse of a TDD-L TE system, the high-precision 10M constant-temperature crystal oscillator is multiplied by frequency to 100M to serve as a main clock of the system, a count (count value) of each 1PPS received by the clock is recorded, the count value is stored in a RAM1 (first storage) of the CP L D, then after the calibration time is up, the microprocessor actively reads the values in the RAM1(count send to flash), stores the values in F L ASH, and waits for a calibration value which is synchronously kept when the next device is started.

The above process CP L D is used as an algorithm, ARM is used to control CP L D, count of CP L D is stored in F L ASH, count value of F L ASH is written back to CP L D, GPS is used to generate 1PPS, and 10M constant temperature crystal oscillator is used as a clock source of the counter.

S4: after receiving 1PPS continuously sent by a GPS module, a clock chip calibrates and synchronizes a pulse per second signal of the GPS according to a high-precision low-jitter reference clock signal provided by a high-precision crystal oscillator and outputs a first synchronous pulse per second signal aligned with the pulse per second signal;

specifically, referring to fig. 5, the process of outputting the first synchronous pulse-per-second signal by the clock chip may include the following steps:

s41: the clock chip receives the pulse-per-second signal and a stable reference clock signal (such as 10MHz) output by the constant temperature crystal oscillator;

s42: the clock chip takes the reference clock signal as a reference, and adjusts the digital phase-locked loop of the clock chip by continuously training the second pulse signal (1PPS) of the GPS, so that the clock chip outputs a first synchronous second pulse signal (first 1PPS) which is synchronous with the frequency and phase of the second pulse signal.

Specifically, in S42, a digital phase-locked loop circuit (P LL) is built in the clock chip, which can perform up-conversion on the received 1PPS, and reduce the input clock jitter and phase jitter related to the external reference to 300 femtoseconds, where the clock chip uses a 10M crystal oscillator as a reference, adjusts its own digital phase-locked loop by continuously training the 1PPS, and drives a frequency phase discriminator to realize phase adjustment, lock the phase, and output the first 1PPS aligned with the 1PPS of the GPS signal (the same phase and the same frequency).

The clock chip can maintain the output of the first 1PPS signal and can maintain the previous accurate 10MHz output so that the processor can acquire the output for device synchronization when no GPS signal exists subsequently.

Preferably, the clock chip adopts an AD9548 chip as a main chip. Because the requirements on the stability of the crystal oscillator and the time precision of the pulse per second for synchronization are high, a constant temperature crystal oscillator with high precision is preferably adopted for the 10M crystal oscillator.

The process from the reception of the GPS signal to the clock holding of the AD9548 is long, roughly fifteen to twenty minutes, but once the AD9548 clock is locked, the holding time is long, generally 3 hours or more within 3us, which is long enough for the emergency to enter a tunnel or a basement.

And S5, when the equipment cannot receive the GPS signal, the processor acquires the first synchronous second pulse signal (first 1PPS) from the clock chip for synchronization according to a preset strategy, or acquires the second synchronous second pulse signal (second 1PPS) from the CP L D for synchronization, or acquires the third synchronous second pulse signal (third 1PPS) from the CP L D for synchronization, wherein the specific strategy is shown in S1.

Specifically, a trigger signal is obtained by obtaining the synchronization of the air interface signal of the adjacent cell, and then CP L D calibrates and synchronizes the trigger signal according to the stored calibration value, so as to output a second synchronous pulse per second signal (second 1PPS) aligned with the pulse per second signal of the GPS.

The third 1PPS is obtained based on the counter of CP L D, and particularly, the third synchronous pulse per second signal aligned with the pulse per second signal of the GPS is output through the last pulse per second signal recorded by CP L D and the calibration value.

The above-mentioned manner of acquiring the pulse per second signal is implemented based on the check value stored in CP L D and the stable reference clock signal output by the constant temperature crystal oscillator.

The process of acquiring the second 1PPS based on the air interface synchronization may include:

1. the equipment receives a downlink air interface signal of a neighboring base station;

2. the equipment obtains the SFN and the SF through the analysis of the physical layer according to the downlink air interface signal, and generates a trigger pulse (such as a 40ms pulse) corresponding to the SFN through interruption;

3. the CP L D records a 40ms movement track through a high-precision constant-temperature crystal oscillator, and simulates a GPS module to generate 1PPS information through 25 40ms time intervals and SFN information (i.e., simulates the second 1PPS synchronized with the 1PPS output by the GPS).

When the base station device enters an environment without GPS signals and without air interface synchronization, the second 1PPS signal output by the CP L D may provide a synchronization signal for the device.

The process of acquiring the third 1PPS for the CP L D-based counter may include:

the CP L D outputs a third sync second pulse aligned with the second pulse signal of the GPS module according to its recorded phase position of the last second pulse signal and the calibration value obtained from the F L ASH.

Specifically, referring to fig. 6, the process of the CP L D using its own counter to keep synchronization corresponding to the content of the check value obtained in the step S3 may include:

after the device is powered on, the device waits for the CP L D and the M3 (microprocessor) to be started completely, M3 actively reads the calibration value in the F L ASH and writes the calibration value into a RAM2(count from flash, namely a second memory) of the CP L D, and the CP L D synchronously keeps generating 1PPS according to the calibration value.

If the device is turned on to receive the GPS PPS seconds, the CP L D outputs the GPS PPS seconds, and after the GPS signal is lost, the CP L D records the phase position of the last 1PPS in the phase positions of each 1PPS according to the GPS seconds, and generates the third 1PPS by playing the count value, wherein the third 1PPS is kept aligned with the 1PPS of the GPS by the calibration value.

When the GPS signal is coming again, the device may reset CP L D by sending a reset command (corresponding to the calibration time), and then the third 1PPS generated by CP L D will be realigned with the 1PPS of GPS, achieving an update of the pulse-per-second signal, ensuring synchronization of signal accuracy, while CP L D continues to output the 1PPS signal of GPS.

Compared with a clock chip, the time consumption of the above synchronization method based on the CP L D counter or the air interface signal is short, and synchronization can be performed by only starting the device and finding the TRIG signal source (trigger signal, e.g. 40ms) of the TDD-L TE system or 1PPS of the synchronization source GPS, but the deviation within 3us of the method can only be kept about 1 hour.

In a specific embodiment, the processor of the device further receives and records a world clock signal sent by the GPS module; then, under the condition that the GPS signal can not be received, calculating and maintaining a world clock signal through a reference clock signal according to the recorded world clock signal;

and when the processor is used for synchronizing, the processor performs physical layer air interface symbol alignment, subframe alignment and radio frequency switch uplink and downlink switching indication according to the acquired first synchronous second pulse signal, second synchronous second pulse signal or third synchronous second pulse signal and the calculated world clock signal until the GPS signal is recovered.

Example two

The system may include a processor, a clock chip (e.g., AD9548), a CP L D, GPS module, a microprocessor (e.g., ARM (STM32), M3 for short, or PSC9132), a high-precision constant-temperature crystal oscillator (e.g., 10M constant-temperature crystal oscillator), and F L ASH.

The GPS module is used for receiving GPS signals, generating pulse per second signals (1PPS) and universal clock signals (UTC) and respectively sending the signals to the clock chip and the CP L D;

the constant temperature crystal oscillator is used for providing a high-precision low-jitter reference clock signal, such as a 10MHz clock signal.

The clock chip is used for receiving the pulse-per-second signal sent by the GPS module; and calibrating and synchronizing the pulse per second signal according to a reference clock signal, and outputting a first synchronous pulse per second signal aligned with the pulse per second signal.

Preferably, the clock chip takes AD9548 as a main chip, and the AD9548 is a clock holding chip derived from ADI.

In one embodiment, the clock chip includes:

and the phase-locked loop circuit (P LL) is used for taking the reference clock signal as a reference, and adjusting the digital phase-locked loop of the phase-locked loop circuit by continuously training the pulse-per-second signal to enable the digital phase-locked loop circuit to output a first synchronous pulse-per-second signal which is synchronous with the frequency and the phase of the pulse-per-second signal.

The CP L D is used for receiving the pulse per second signals generated according to GPS signals, recording each pulse per second signal, acquiring a calibration value according to the count value between each pulse per second signal and then storing the calibration value, performing calibration synchronization on the trigger signal obtained by acquiring the air interface signal synchronization of the adjacent region according to the calibration value stored in the CP L D, and outputting a second synchronous pulse per second signal aligned with the pulse per second signal;

in the foregoing specific embodiment, the CP L D specifically includes:

Optionally, in the foregoing specific embodiment, the CP L D further includes:

The processor is used for acquiring the first synchronous second pulse signal from the clock chip for synchronization according to a preset strategy under the condition that the GPS signal cannot be received, or acquiring the second synchronous second pulse signal from the CP L D for synchronization, or acquiring the third synchronous second pulse signal from the CP L D for synchronization, and is also used for recording the received world clock signal, calculating and maintaining the world clock signal by referring to the clock signal according to the recorded world clock signal under the condition that the GPS signal cannot be received, and performing physical layer air interface symbol alignment, subframe alignment and radio frequency switch uplink and downlink switching indication according to the acquired first synchronous second pulse signal, the second synchronous second pulse signal or the third synchronous second pulse signal and the calculated world clock signal until the GPS signal is recovered.

The microprocessor (M3) is used for controlling the CP L D, storing the count of the CP L D into the F L ASH, and writing the count value of the F L ASH back to the CP L D, namely controlling the CP L D to obtain the check value.

In the above specific embodiment, the system further includes:

EXAMPLE III

This embodiment provides a specific implementation corresponding to the first and second embodiments, and in this specific implementation, the same contents are not repeated, but the following contents are specifically detailed:

when there is a GPS signal, the device obtains a calibration value through 1PPS of GPS, when the device cannot receive the GPS signal but TDD-L TE can receive a signal from an adjacent area, at this time TDD-L TE can be synchronized by sniffer, when the sniffer is synchronized, the TDD-L TE system can generate a 40ms TRIG signal (trigger signal), which can be sent to CP L D for synchronization calibration, because 1s is 40ms 25, CP L D generates a 1PPS signal with N (0-24) 40ms difference from the GPS 1PPS signal through a counter.

Aiming at the condition that the CP L D acquires a second synchronous pulse per second signal (based on the air interface synchronization condition), if a downlink signal of a base station of a neighboring cell can be received, the SFN and the SF can be analyzed through a TDD-L TE device at the moment, the device can be synchronized with the base station of the neighboring cell at the moment, a 40ms pulse is generated according to the SFN and the SF, the 40ms pulse is sent to a CP L D chip, the CP L D chip recovers a 1PPS signal (namely, a second 1PPS) aligned with the SFN according to a 40ms running track, when the downlink signal of the neighboring cell is weakened or disappears, the sniffer synchronization can not be performed at the moment, the device is automatically switched to a CP L D counter-based synchronization keeping method, and the synchronization at the moment is based on a third 1PPS pulse recovered by CP L D.

In this embodiment, the idea of the device performing synchronization maintenance is as follows:

in the first case, referring to fig. 7, when the base station is powered on with GPS signals, the GPS module receives GPS signals and generates 1PPS and UTC, and transmits 1PPS to the clock chip AD9548, and transmits UTC signals to the processor PSC9132, and the clock chip AD9548 maintains synchronization of 1PPS and performs clock calibration, and generates a 10M calibrated clock, and transmits 1PPS (first 1PPS) to the TDD-L TE system device for synchronization.

When the GPS signal disappears, the clock chip AD9548 will keep the first 1pps signal output and will keep the previous accurate 10M output, pass the previously recorded UTC, and use 10M to calculate and maintain the UTC time information that has been lost.

Referring to fig. 8, when the base station is powered on and has no GPS signal, the TDD-L TE device receives the downlink signal of the neighboring base station in sniffer mode for synchronization, and the physical layer of the TDD-L TE system generates a 40ms pulse aligned with the SFN at this time, and transmits the pulse to the CP L D, and the CP L D records the 40ms trace by using the frequency accuracy and high stability of the constant temperature crystal oscillator.

Specifically, when the TDD-L TE device cannot receive downlink signals of the neighboring cell, the CP L D restores the 40ms trajectory by memorizing, and restores 1PPS pulses (i.e., the third 1PPS) by 25 time intervals of 40ms, where when the base station cannot receive signals of the neighboring cell, the base station of the device receives 1PPS pulses (i.e., the third 1PPS) generated by CP L D in an analog manner for synchronization, and at this time, the sniffer synchronization mode is switched to the GPS synchronization mode.

In this embodiment, referring to fig. 7 and fig. 8, the operation principle of the device synchronization keeping is as follows:

(one), the device can receive the GPS signal condition when just powering on: GPS sends UTC information and 1PPS pulse to PSC9132 for synchronization, and sends 1PPS to clock chip AD9548, and clock chip AD9548 receives GPS's 1PPS signal and the stable 10MHz of constant temperature crystal oscillator, outputs adjusted 10MHz and 1PPS pulse (first 1 PPS).

When the base station can not receive the GPS signal, the base station can acquire the synchronous signal source and automatically switch to a clock chip AD9548 from the GPS module, and if the base station enters an area which can not receive the GPS signal, the holding module can replace the GPS module within a period of time, and outputs a stable 1PPS signal to the base station equipment for use.

The base station equipment can be synchronized at an air interface, the base station obtains SFN and SF through physical layer analysis, generates a 40ms pulse corresponding to the SFN through interruption, the pulse and the SFN information are output to CP L D, CP L D records a 40ms running track through a high-precision constant-temperature crystal oscillator, and generates 1PPS information (second 1PPS) through 25 40ms time intervals and an SFN information simulation GPS module;

when the base station equipment enters an environment without GPS signals and without air interface synchronization, the 1PPS signal (the first 1PPS) output by the clock chip can provide a synchronization signal, or the third 1PPS is acquired from the CP L D to provide the synchronization signal, the synchronization precision of the first 1PPS output by the clock chip is greater than that of the third 1PPS output by the CP L D, therefore, the synchronization is preferably carried out according to the first 1PPS, and the synchronization is carried out according to the third 1PPS when the first 1PPS is not acquired.

As shown in fig. 6, the third 1PPS output by CP L D may be based on a system trigger signal (40ms) or a 1PPS acquisition of GPS signals.

Wherein the process based on the system trigger signal (40ms) comprises:

referring to fig. 8, a downlink signal of the radio frequency antenna interface adjacent to the base station is received by the radio frequency filter and then transmitted to the low noise amplifier, the low noise amplifier then transmits the signal to the AD9362 for analog-to-digital conversion, at this time, the converted baseband signal is analyzed by the PSC9132 processor to analyze the SFN and the SF, at this time, the base station achieves air interface synchronization, and outputs a 40ms pulse to the CP L D, the pulse is aligned with the SFN, the CP L D converts 25 40ms cycles into 1s time cycles through a counter, and each 1s cycle generates a pulse 1PPS (i.e., the second 1 PPS).

The high-precision constant-temperature crystal oscillator records the running track of each 1PPS by using the 10M of the high-precision constant-temperature crystal oscillator, and stores the recorded period of each time into the RAM, so that the running track of five to ten minutes can be recorded. Of course, the longer the recording time, the more practical the 1PPS error is within 1us for 25 40ms periods. The errors of 1PPS are not accumulated, because the sniffer is calibrated at all times, if the current 40ms period is longer, the errors are supplemented back by the next several periods, but the errors are deviated at all times, and it is unknown which period is supplemented back. According to actual measurement, whether you record 1000 40ms or 10000 40ms, the deviation of the recorded time is always within 3us, so that the longer the recorded time is, the error of 1PPS is smaller after the average. The length of time for polling the 40ms trace can be determined according to the time situation. According to practical tests, the constant temperature crystal oscillator needs to be preheated, when the running time of the constant temperature crystal oscillator is more than 10 minutes, the stability of the constant temperature crystal oscillator is high, so that the 40ms running track is recorded after the crystal oscillator is preheated for 10 minutes, and then the track is recorded for 5 to 10 minutes, so that the time length of 15 minutes to 20 minutes is also needed for synchronous maintaining through the sniffer, and if the 10 minute length maintaining track is recorded, 15000(10 × 60 × 25) tracks of 40ms need to be recorded. The recording is of course ongoing until the sniffer is out of sync, the 10 minute length trace referring to ten minutes before the sniffer is out of sync. Thus the crystal oscillator characteristic is the one closest to the current operation and then outputs a pulse 1PPS every 25 40ms (third 1 PPS).

When the equipment cannot receive the sniffer signal and the GPS signal, the equipment is automatically switched to be in GPS synchronization, but the GPS synchronization source at the moment is not from a GPS module, and the synchronization source at the moment is the running track of the third 1PPS recovered by the CP L D.

The synchronization maintenance method of the present embodiment is performed in combination with the above two maintenance principles.

As shown in FIG. 9, the system uses PSC9132 as the core, and the periphery includes a GPS module, a constant temperature crystal oscillator, a clock chip AD9548, a CP L D, a MCU, an AD9362, a power amplifier and low noise amplifier module, a radio frequency filter, an antenna, etc. the design includes the above two holding methods, and the PSC9132 processor determines which method to use for holding according to a preset strategy.

When the equipment is powered on and started, the equipment scans GPS information and downlink signals of a neighboring cell, when the equipment can receive GPS synchronization signals, the equipment actively performs GPS synchronization, a line marked 1 is a GPS synchronization mode, a GPS module directly sends 1PPS pulses to a PSC9132 for synchronization, a clock chip AD9548 performs holding action according to the first 1PPS and 10M output by a constant temperature crystal oscillator, after the clock chip AD9548 can lock frequency and lock phase with second pulses of the GPS, if the equipment does not receive the 1PPS pulses output by the GPS, the equipment performs sniffer holding according to the downlink signals of a neighboring cell base station scanned when starting, namely, the equipment performs synchronization by acquiring a second PPS output by a CP L D.

If the sniffer signal is not scanned at this time, the device may automatically switch the holding source to the first 1PPS output by the clock chip AD9548 for synchronization.

And if the sniffer is scanned at the moment, the device keeps through the sniffer, namely, synchronization is carried out by acquiring the second PPS output by the CP L D, the PSC9132 processor simultaneously outputs 40ms to the CP L D, the CP L D records a 40ms track, and after the sniffer disappears, the device automatically switches the synchronization source to the third 1PPS output by the CP L D.

In summary, the synchronization maintaining method and system for TDD-L TE devices provided by the present invention can flexibly select the first sync second pulse, the second sync second pulse, or the third sync second pulse according to a preset policy to maintain synchronization in time in a specific scene where the device cannot receive GPS signals, so as to ensure normal operation of the device and ensure synchronization accuracy.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.

Claims

1. A method for maintaining synchronization of TDD-L TE equipment is characterized by comprising the following steps:

wherein the CP L D outputs a third synchronous pulse-per-second signal aligned with the pulse-per-second signal according to the last recorded pulse-per-second signal and the calibration value;

wherein the preset strategy is as follows:

2. The method for maintaining synchronization of a TDD-L TE device according to claim 1, wherein the clock chip calibrates and synchronizes the pulse-per-second signal according to a reference clock signal, and outputs a first synchronized pulse-per-second signal aligned with the pulse-per-second signal, specifically:

3. The method for maintaining the synchronization of the TDD-L TE device according to claim 1, wherein the CP L D records each pulse per second signal, and obtains a calibration value according to the count value between each pulse per second signal for storage, specifically:

4. The method for maintaining synchronization of a TDD-L TE device according to claim 3, wherein the CP L D outputs a third sync second pulse signal aligned with the second pulse signal according to its recorded last second pulse signal and the calibration value, specifically:

5. The method for maintaining synchronization of a TDD-L TE device of claim 1, further comprising:

the GPS module sends the world clock signal to a processor;

the processor records the received world clock signal;

6. The method for maintaining synchronization of TDD-L TE devices according to claim 1, wherein the obtaining of the trigger signal by obtaining synchronization of air interface signals of neighboring cells specifically includes:

the equipment receives a downlink air interface signal of a neighboring cell;

7. A system for maintaining synchronization of a TDD-L TE device, comprising:

the processor is used for acquiring the first synchronous second pulse signal from the clock chip for synchronization according to a preset strategy under the condition that the GPS signal cannot be received, or acquiring the second synchronous second pulse signal from the CP L D for synchronization, or acquiring the third synchronous second pulse signal from the CP L D for synchronization;

wherein the preset strategy is as follows:

8. The synchronization maintenance system of the TDD-L TE device of claim 7, wherein the clock chip comprises:

the first receiving circuit is used for receiving the pulse per second signal and a reference clock signal output by the constant temperature crystal oscillator;