CN108073481B - Server system capable of providing hardware operation information and processing method thereof - Google Patents
Server system capable of providing hardware operation information and processing method thereof Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention provides a server system capable of providing hardware operation information and a processing method thereof. The server device includes a baseboard management control unit having a serial port and a baseboard management controller, a processing unit, a storage unit, and a basic input/output unit. The processing method comprises a step (A) of sleeving the serial port by a port and starting the server device, a step (B) of executing a detection instruction of the basic input/output unit by the processing unit to the substrate management controller, and a step (D) of executing a debugging mode of the basic input/output unit and taking out the operation information of the storage unit if the serial port is sleeved by the port and the electric connection is normal, thereby simplifying the complex action of entering the debugging mode, reducing the number of times of restarting the computer and saving the time.
Description
Technical Field
The present invention relates to a server system, and more particularly, to a server system capable of providing hardware operation information and a processing method thereof.
Background
In the server system monitoring and management, the manager usually needs to monitor the hardware operation status, such as the status of Central Processing Unit (CPU), the operation signal strength of the storage Unit, and so on, so as to further grasp the operation status of the system and eliminate the real-time exception.
Generally, when a system administrator wants to confirm operation information of storage units in the system, such as: the signal setting value, signal strength and information during initialization of a Dual In-line Memory Module (DIMM) need to enter a debug mode (debug mode) to obtain the information, and the conventional method for entering the debug mode is to press a hot key to enter a setting menu of a Basic Input/Output System (BIOS) and set the debug mode, and restart the System after setting and storing, wherein a central processing unit executes an instruction of the debug mode of the BIOS to obtain the operation information of a storage unit. After the execution is completed, to finish \ leave the debug mode, the administrator needs to restart the system, press the hot key to enter the setting menu of the basic input/output unit to cancel the setting of entering the debug mode, then restart the system to finish \ leave the debug mode, and switch back to executing the normal boot process, i.e., the central processing unit will not execute the boot process of the instruction of the debug mode of the basic input/output unit. However, the above-mentioned process of continuously and repeatedly executing system boot is very time consuming, and the number of storage units of the server system is usually large, the system boot usually takes 5 to 10 minutes, and the administrator of the execution process needs to wait aside, which not only causes the trouble of the administrator, but also is not in line with the economic benefit.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to provide a time-saving and efficient server system capable of providing hardware operation information.
To achieve the above object, the present invention provides a server system for providing hardware operation information, which includes a server device and a processing device electrically connected to the server device.
The server device includes a baseboard management control unit, a south bridge electrically connected to the baseboard management control unit, a processing unit electrically connected to the south bridge, a storage unit electrically connected to the processing unit, and a BIOS unit electrically connected to the south bridge and having a debug mode. The BMC has a serial port and a BMC connected to the serial port.
The processing device comprises a computer unit and a connecting unit for connecting the computer unit and the baseboard management control unit, wherein the connecting unit is provided with a connecting piece for linking the computer unit and a port which is arranged on the connecting piece and can be sleeved on the serial port of the baseboard management control unit. When the server device is powered on, the processing unit receives a detection command from the BIOS through the south bridge and executes the detection command to the BMC of the BMC through the south bridge.
When detecting that the serial port of the baseboard management control unit is sleeved by the port of the connection unit and is normally electrically connected, the processing unit executes the debug mode of the BIOS to take out the operation information of the storage unit.
When detecting that the serial port of the baseboard management control unit is sleeved by the port of the connection unit and is abnormally electrically linked, the processing unit does not take out the operation information of the storage unit by executing the debug mode and continues to complete the booting operation of the BIOS. When detecting that the serial port of the baseboard management control unit is not sleeved by the port, the processing unit will not extract the operation information of the storage unit by executing the debug mode and the processing unit continues to complete the booting operation of the BIOS.
Therefore, another objective of the present invention is to provide a time-saving and efficient processing method capable of providing hardware operation information.
Therefore, the invention can provide a processing method of hardware operation information, which is applied to a server system. The server system comprises a server device and a processing device. The server device includes a baseboard management control unit, a south bridge, a processing unit, a storage unit, and a BIOS with a debug mode. The BMC has a serial port and a BMC connected to the serial port. The processing device comprises a computer unit and a connecting unit. The connection unit has a connection piece linking the computer unit and a port which is arranged on the connection piece and can be sleeved on the serial port of the baseboard management control unit. The processing method capable of providing hardware operation information comprises a step (A), a step (B), a step (C), a step (D) and a step (E).
In the step (a), after the serial port of the bmc unit is sleeved by the port of the connection unit, the server device is turned on.
In the step (B), when the server device is powered on, the processing unit receives a detection command from the bios through the south bridge and executes the detection command to the bmc of the bmc unit through the south bridge.
In the step (C), the processing unit detects and determines whether the serial port of the bmc unit is plugged by the port of the connection unit and the electrical connection is normal through the bmc.
In the step (D), if the result of the determination in the step (C) is yes, the processing unit executes the debug mode of the bios unit to retrieve the operation information of the storage unit.
In the step (E), if the determination result of the step (C) is negative, the processing unit will not fetch the operation information of the storage unit by executing the debug mode and the processing unit continues to complete the booting operation of the bios.
Compared with the prior art, the processing unit executes the detection instruction of the basic input/output unit, and when the serial port of the baseboard management control unit is detected to be sleeved by the port and is normally electrically linked, the processing unit executes the debugging mode of the basic input/output unit to take out the operation information of the storage unit, complex actions of entering the debugging mode and restarting can be set without pressing a hot key first, and the repeated execution system is effectively reduced and the time is saved.
[ description of the drawings ]
FIG. 1 is a block diagram illustrating an embodiment of a server system for providing hardware operational information according to the present invention;
FIG. 2 is a block diagram to assist in explaining FIG. 1; and
FIG. 3 is a flowchart illustrating an embodiment of a method for processing hardware operation information according to the present invention.
[ detailed description ] embodiments
Before the present invention is described in detail, it should be noted that in the following description, similar components are denoted by the same reference numerals.
Referring to fig. 1 and fig. 2, the server system for providing hardware operation information according to the present invention includes a server device 1 and a processing device 2 electrically connected to the server device 1.
The server device 1 includes a baseboard management control unit 11, a south bridge 12 electrically connected to the baseboard management control unit 11, a processing unit 13 electrically connected to the south bridge 12, a storage unit 14 electrically connected to the processing unit 13, and a BIOS 15 electrically connected to the south bridge 12. The BMC 11 has a serial port 111, and a BMC 115 connected to the serial port 111. The serial port 111 has a set of handshake pins 112, the set of handshake pins 112 having an input pin 113 and an output pin 114. The BIOS 15 has a debug mode and a normal mode.
The processing device 2 includes a computer unit 21, and a connection unit 22 connecting the computer unit 21 and the baseboard management control unit 11, wherein the connection unit 22 has a connection member 221 for connecting the computer unit 21, and a port 222 disposed on the connection member 221 and capable of being sleeved on the serial port 111 of the baseboard management control unit 11.
First, the port 222 of the connection unit 22 of the processing apparatus 2 is sleeved on the serial port 111 of the bmc unit 11, so that the computer unit 21 and the serial port 111 are electrically connected. When the server apparatus 1 is powered On, during the period when the processing unit 13 executes post (power On Self test), the processing unit 13 receives a detection command from the bios 15 via the south bridge 12 and executes the detection command to the bmc 115 of the bmc 11 via the south bridge 12.
When the serial port 111 of the bmc 11 is sleeved by the port 222 of the connection unit 22 and the handshake pins 112 of the serial port 111 and the port 222 establish normal electrical connection, the input pin 113 of the handshake pin 112 generates a corresponding high-level signal and the output pin 114 generates a corresponding high-level signal. When the input pin 113 and the output pin 114 are both at the high level signal, the set of handshaking pins 112 generates a handshaking high level signal and transmits the handshaking high level signal to the baseboard management controller 115. In this embodiment, the serial port 111 is a male connector, and the port 222 is a female connector, but not limited thereto, as long as the serial port 111 and the port 222 are electrically connected and perform a signal handshake function therebetween.
When the processing unit 13 executes the detection command and detects the handshake high level signal received by the bmc 115, the processing unit 13 executes the debug mode of the bios 15, and fetches the operation related information of the storage unit 14 and continues to complete the booting of the bios 15. The operation information of the memory unit 14 taken out by the memory unit is transmitted to the baseboard management controller 115 of the baseboard management control unit 11 through the south bridge 12, and is transmitted to the computer unit 21 through the link of the serial port 111 and the port 222 for the user to use in subsequent analysis and test. In the present embodiment, the storage unit 14 is a Dual In-line Memory Module (DIMM), and the information related to the operation of the storage unit 14 is fetched, for example: the signal setting value, the signal strength, and the information during the operation process, etc. are provided to the user to clearly understand the status of the storage unit 14, which is convenient for the subsequent data analysis, real-time detection and exception elimination.
When the serial port 111 is sleeved by the port 222 and the electrical connection between the set of handshake pins 112 of the serial port 111 and the port 222 is abnormal, the set of handshake pins 112 will generate a handshake low level signal indicating that the port 222 and the set of handshake pins 112 cannot establish a normal electrical connection, for example: when the input pin 113 of the handshake pin 112 is unable to establish electrical connection with the port 222, the input pin 113 generates a corresponding low-level signal, so that the handshake pin 112 generates the handshake low-level signal. Or when the output pin 114 and the port 222 cannot establish electrical connection, the output pin 114 will generate a corresponding low-level signal, so that the set of handshake pins 112 generates the handshake low-level signal. And when the input pin 113 and the output pin 114 cannot be electrically connected to the port 222, the input pin 113 and the output pin 114 respectively generate corresponding low-level signals, so that the handshake pin 112 generates the handshake low-level signal.
The handshake low level signal generated by the handshake pin 112 is transmitted to the bmc 115, when the processing unit 13 executes the detection command and detects the handshake low level signal received by the bmc 115, the processing unit 13 cannot fetch the operation information of the storage unit 14 by executing the debug mode, that is, the processing unit 13 cannot execute the command in the debug mode and the processing unit 13 executes the normal mode of the bios 15, and continues to complete the boot operation of the bios 15. In addition, when the electrical connection between the set of handshake pins 112 and the port 222 is abnormal, which may be the case that the port 222 and the serial port 111 are not completely inserted or the set of handshake pins 112 is abnormal, the user can re-check the link between the port 222 and the serial port 111 and then reboot the system, so that the processing unit 13 can detect the handshake high level signal and execute the debug mode of the basic input/output unit 15. Or when the processing unit 13 is executing the normal mode of the bios 15 and before entering the OS system after completing the POST stage, the user can enter the bios 15 setting menu by entering a hot key, and after setting and storing the bios setting menu into the debug mode, the processing unit 13 is restarted to execute the debug mode.
It should be particularly noted that, when the serial port 111 of the bmc 11 is not sleeved by the port 222 of the connection unit 22, it means that the set of handshake pins 112 cannot be electrically connected to the port 222, that is, neither the input pin 113 nor the output pin 114 can be electrically connected to the port 222, and the input pin 113 nor the output pin 114 respectively generate corresponding low-level signals, so that the handshake pins 112 generate the handshake low-level signals and transmit the handshake low-level signals to the bmc 115. When the processing unit 13 executes the detection command and detects the handshake low level signal received by the bmc 115, the processing unit 13 cannot fetch the operation information of the storage unit 14 by executing the debug mode, and the processing unit 13 executes the normal mode of the bios 15 to continue to complete the booting operation.
Referring to fig. 1, fig. 2 and fig. 3, the present invention can provide an embodiment of a method for processing hardware operation information, which is applied to the server system as described above. The processing method capable of providing hardware operation information comprises a step (A), a step (B), a step (C), a step (D) and a step (E).
First, in the step (a), after the serial port 111 of the bmc unit 11 is sleeved by the port 222 of the connection unit 22, the server apparatus 1 is turned on. In the step (B), when the server apparatus 1 is powered on, the processing unit 13 receives a detection command from the bios 15 via the south bridge 12 and executes the detection command to the bmc 115 of the bmc 11 via the south bridge 12. In the present embodiment, the south bridge 12 and the bios 15 perform data reading and transmission by using Serial Peripheral Interface (SPI) access. The processing unit 13 performs data transmission with the south bridge 12 by a Direct Media Interface (DMI) bus. The data transmission from the south bridge 12 to the bmc 11 is performed by a Low Pin Count (LPC) bus.
Next, in the step (C), the processing unit 13 determines whether the serial port 111 of the bmc 11 is plugged by the port 222 of the connection unit 22 and the electrical connection is normal through the bmc 115. Briefly, the port 222 is firstly sleeved on the serial port 111 of the bmc unit 11, and then the server apparatus 1 is turned on, and when the server apparatus 1 is turned on, the processing unit 13 executes the detection command to detect the bmc 115, so as to detect and determine the electrical connection relationship between the serial port 111 and the port 222.
Specifically, the step (C) includes a step (C1), and a step (C2).
In the step (C1), when the group of handshake pins 112 of the serial port 111 of the bmc 11 is sleeved by the port 222 of the connection unit 22 and is normally connected, a handshake high level signal is generated and transmitted to the bmc 115. In detail, when the serial port 111 is sleeved by the port 222 of the connection unit 22 and the set of handshake pins 112 of the serial port 111 is normally electrically connected to the port 222, the input pin 113 of the set of handshake pins 112 generates a corresponding high-level signal and the output pin 114 generates a corresponding high-level signal. When the input pin 113 and the output pin 114 are both at the high level signal, the set of handshake pins 112 generates the handshake high level signal and transmits the handshake high level signal to the bmc 115. In contrast, when the serial port 111 is sleeved by the port 222 but the electrical connection between the handshake pins 112 and the port 222 is abnormal or the serial port 111 is not sleeved by the port 222, the handshake pins 112 generate the handshake low-level signal and transmit the handshake low-level signal to the baseboard management controller 115, and the description of generating the handshake low-level signal is described in detail in the above embodiment of the server system capable of providing hardware operation information, and is not described herein again. In addition, in this embodiment, the handshake high level signal and the handshake low level signal are transmitted to a serial data port (not shown) of the bmc 115 by Asynchronous serial data transmission (UART) and stored in an internal chip (not shown) of the bmc 115, and the processing unit 13 executes the detection command of the bios 15 from the south bridge 12 to the serial data port of the bmc 115 to read the handshake high level signal or the handshake low level signal stored in the internal chip.
In the step (C2), the detection command determines whether the handshake high level signal is detected via the bmc 115. That is, the processing unit 13 executes the detection command to detect whether the bmc 115 receives the handshake high level signal generated by the handshake pins 112. In this embodiment, the handshake pins 112 and the port 222 of the serial port 111 are used for signal transmission by hardware handshake and the input pin 113 is cts (clear to send) and the output pin 114 is rts (request to send) as a handshake signal, so that the handshake pins 112 generate the handshake high-level signal, but not limited thereto, the input pin 113 may be dtr (data Terminal ready) and the output pin 114 may be dsr (data Set ready) as a handshake signal.
If the result of the determination in the step (C2) is yes, it represents that the handshake high level signal received by the bmc 115 is detected, then in the step (D), the processing unit 13 executes the debug mode of the bios 15 to retrieve the operation information of the storage unit 14, and continues to complete the booting of the bios 15. The operation information of the storage unit 14 taken out by the storage unit is transmitted to the baseboard management controller 115 of the baseboard management control unit 11 through the south bridge 12, and the information is transmitted to the computer unit 21 through the link of the serial port 111 and the port 222, so as to be available for the user to use in the following analysis and test.
If the determination result in the step (C2) is "no", which means that the handshake low level signal received by the bmc 115 is detected, in the step (E), the processing unit 13 cannot fetch the operation information of the storage unit 14 by executing the debug mode, and the processing unit 13 executes the normal mode of the bios 15 and continues to complete the booting operation.
Furthermore, if the user has obtained the operation information required by the storage unit 14, only by pulling the port 222 of the connection unit 22 out of the serial port 111, when the system is powered on next time, the bmc 115 receives the handshake low level signal, so that the processing unit 13 cannot detect the handshake high level signal, and simply executes the normal mode of the bios 15 to continue to complete the operation, thereby effectively improving the problem that the system needs to be powered on again after the debug mode is executed, then the hot key is pressed to cancel the setting of entering the debug mode, and then the system is powered on again to execute the normal complex procedure of the power-on process, thereby improving the working efficiency.
By means of the design that the handshake pins 112 of the serial port 111 and the port 222 are handshake-generated and transmitted to the bmc 115, and when the server device 1 is powered on, the processing unit 13 detects the handshake high level signal received by the bmc 115, the processing unit 13 executes the debug mode of the bios 15 to fetch the operation information of the storage unit 14, without pressing a hot key first to set the complex action of entering the debug mode, thereby effectively reducing the repeated execution of system power-on and saving time.
In summary, the present invention provides a server system of hardware operation information and a processing method thereof, wherein when the processing unit 13 executes the detection command of the bios 15 and detects that the serial port 111 is sleeved by the port 222 and is normally electrically connected, the processing unit 13 executes the debug mode of the bios 15 to retrieve the operation related information of the storage unit 14, thereby improving the complex operation of restarting the execution system and effectively saving time, so as to achieve the object of the present invention.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A server system for providing hardware operational information, comprising:
a server device, which includes a baseboard management control unit, a south bridge electrically connected to the baseboard management control unit, a processing unit electrically connected to the south bridge, a storage unit electrically connected to the processing unit, and a basic input/output unit electrically connected to the south bridge and having a debug mode, wherein the baseboard management control unit has a serial port and a baseboard management controller connected to the serial port; and
a processing device electrically connected to the server device, including a computer unit, and a connection unit connecting the computer unit and the baseboard management control unit, the connection unit having a connection member linking the computer unit, and a port disposed on the connection member and capable of being sleeved on the serial port of the baseboard management control unit, when the server device is powered on, the processing unit receives a detection command of the basic input/output unit through the south bridge and executes the detection command to the baseboard management controller of the baseboard management control unit through the south bridge, when the serial port of the baseboard management control unit is detected to be sleeved by the port of the connection unit and normally electrically linked, the processing unit executes the debugging mode of the basic input/output unit to take out the operation information of the memory unit; when detecting that the serial port of the baseboard management control unit is sleeved by the port of the connection unit and is abnormally electrically linked, the processing unit does not take out the operation information of the storage unit by executing the debug mode and continues to complete the booting operation of the BIOS; when detecting that the serial port of the baseboard management control unit is not sleeved by the port, the processing unit will not extract the operation information of the storage unit by executing the debug mode and the processing unit continues to complete the booting operation of the BIOS.
2. The server system of claim 1, wherein the serial port of the bmc unit has a set of handshake pins, when the set of handshake pins of the serial port is sleeved by the port of the connection unit and is normally electrically connected, a handshake high-level signal is generated and transmitted to the bmc, and the processing unit executes the detection command of the bios and detects the handshake high-level signal, the processing unit executes the debug mode of the bios; when the set of handshake pins is sleeved by the port and abnormally electrically connected, a handshake low-level signal is generated and transmitted to the baseboard management controller, the processing unit executes the detection instruction of the basic input/output unit and detects the handshake low-level signal of the baseboard management controller, the processing unit cannot take out the operation information of the storage unit through executing the debug mode and the processing unit continues to execute the boot-up action of the basic input/output unit.
3. The server system of claim 2, wherein the set of handshaking pins of the serial port has an input pin and an output pin, and when the input pin and the output pin of the set of handshaking pins are sleeved by the port of the connection unit and are normally electrically connected, a high-level signal corresponding to the input pin and a high-level signal corresponding to the output pin are generated, so as to generate the handshaking high-level signal; when the input pin and the output pin of the handshake pins are sleeved by the port of the connection unit, but one of the input pin and the output pin is abnormally connected with the port, a corresponding low-level signal is generated, and then the handshake low-level signal is generated.
4. The server system of claim 1, wherein the bios further has a normal mode, when detecting that the serial port of the bmc is sleeved by the port of the connection unit and is normally electrically connected, the processing unit executes the debug mode of the bios to retrieve the operation information of the storage unit and continues to complete the booting operation of the bios, and when the processing unit detects that the serial port of the bmc is sleeved by the port of the connection unit and is abnormally electrically connected, the processing unit does not retrieve the operation information of the storage unit and executes the normal mode of the bios by executing the debug mode and continues to complete the booting operation; when detecting that the serial port of the baseboard management control unit is not sleeved by the port, the processing unit executes the normal mode of the basic input/output unit and cannot take out the operation information of the storage unit, and continues to complete the booting action.
5. A processing method for providing hardware operation information is applied to a server system, the server system comprises a server device and a processing device, the server device comprises a baseboard management control unit with a serial port and a baseboard management controller, a south bridge, a processing unit, a storage unit and a basic input and output unit with a debug mode, the processing device comprises a computer unit and a connection unit, the connection unit has a connection piece linking the computer unit and a port which is arranged on the connection piece and can be sleeved on the serial port of the baseboard management control unit, the processing method is characterized in that the processing method comprises the following steps:
(A) after the serial port of the baseboard management control unit is sleeved by the port of the connection unit, the server device is turned on;
(B) when the server device is powered on, the processing unit receives a detection command from the BIOS through the south bridge and executes the detection command to the BMC of the BMC through the south bridge;
(C) the processing unit detects and judges whether the serial port of the baseboard management control unit is sleeved by the port of the connection unit and the connection is normal through the baseboard management controller;
(D) if the result of the judgment in the step (C) is yes, the processing unit executes the debug mode of the BIOS to retrieve the operation information of the storage unit; and
(E) if the determination result in the step (C) is negative, the processing unit will not fetch the operation information of the storage unit by executing the debug mode and the processing unit continues to complete the booting operation of the BIOS.
6. The processing method as claimed in claim 5, wherein the serial port of the bmc of the server system has a set of handshake pins, and step (C) of the processing method includes
(C1) When the group of handshaking pins of the serial port of the baseboard management control unit are sleeved by the port of the connection unit and are normally electrically connected, a handshaking high-level signal is generated and transmitted to the baseboard management controller,
(C2) the detection command determines whether the handshake high level signal is detected through the baseboard management controller.
7. The processing method as claimed in claim 6, wherein the set of handshaking pins of the serial port has an input pin and an output pin, and the step (C1) of the processing method generates a high-level signal corresponding to the input pin and a high-level signal corresponding to the output pin when the input pin and the output pin of the set of handshaking pins of the serial port are sleeved by the port of the connection unit and are normally electrically connected, thereby generating the high-level signal; when the input pin and the output pin of the handshake pins are sleeved by the port, but one of the input pin and the output pin is abnormally connected with the port, a corresponding low-level signal is generated, and then a handshake low-level signal is generated.
8. The method according to claim 5, wherein the BIOS further has a normal mode, in step (D) of the method, if the result of the step (C) is yes, the processing unit executes the debug mode of the BIOS to retrieve the operation information of the storage unit and continues to complete the booting operation of the BIOS, in step (E) of the method, if the result of the step (C) is no, the processing unit does not retrieve the operation information of the storage unit by executing the debug mode and the processing unit executes the normal mode of the BIOS and continues to complete the booting operation.
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