CN108052739B - Method for designing quick channel of semi-custom back-end design of integrated circuit - Google Patents
Method for designing quick channel of semi-custom back-end design of integrated circuit Download PDFInfo
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- CN108052739B CN108052739B CN201711326399.2A CN201711326399A CN108052739B CN 108052739 B CN108052739 B CN 108052739B CN 201711326399 A CN201711326399 A CN 201711326399A CN 108052739 B CN108052739 B CN 108052739B
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Abstract
The invention discloses a method for designing a fast channel of semi-custom back-end design of an integrated circuit. Step S1: the back-end design tool obtains the original data and the updated data. Step S2: and forming data difference information by comparing the original data and the updated data, and analyzing the data difference information to generate an execution command. Step S3: the execution command is executed to synthesize design data for a fast channel design. Step S4: the design data is applied to the actual engineering design to record critical execution information. Step S5: and analyzing and judging whether the key execution information meets the preset design standard. The invention discloses a method for designing a quick channel of semi-custom back-end design of an integrated circuit, which avoids the situation that the back-end design lags behind the front-end design, enables the back-end design to be synchronously carried out with the front-end design in advance, improves the design efficiency of a back-end design link, and shortens the design period of the whole chip.
Description
Technical Field
The invention belongs to the technical field of design automation (EDA) in the integrated circuit design industry, and particularly relates to a method for designing a quick channel of semi-custom back-end design of an integrated circuit.
Background
Currently, in the field of design automation EDA technology in the integrated circuit design industry, semi-custom backend designs are classified into a flat design method and a hierarchical design method. With the increasing scale of integrated circuits, higher requirements are placed on the existing design technology, especially on semi-custom back-end designs.
When the chip design scale is too large, the conventional flat back-end design approach takes an intolerable time cost and may not result or result poorly. Therefore, for large-scale chip design projects, a hierarchical back-end design flow must be used by the industry in view of the endurance and runtime of EDA design tools.
Compared with the flattening process, the hierarchical design can enable more key design links to be synchronously and parallelly designed. However, in the hierarchical design process, the design links between the front-end design and the back-end design require sequential design. Meanwhile, due to the characteristic of long back-end design process, a later key design link in the back-end design needs to wait for a previous design data result in the current conventional design process, so that a large amount of waiting time is wasted. Because the hierarchical design flow has a lot of additional work to be done, the design flow period and the design complexity are obviously increased, how to synchronously carry out the later key design and the front end design in the hierarchical back end design as much as possible, the chip design period is effectively shortened and the design efficiency is effectively improved, no effective method is available in the conventional semi-customized back end design at present, and the technical problem which needs to be solved urgently in the current situation of the hierarchical back end design is also solved.
Disclosure of Invention
The present invention addresses the above-identified needs in the art by providing a method for designing a fast channel for semi-custom back-end design of an integrated circuit.
The invention adopts the following technical scheme that the method for designing the quick channel of the semi-customized back end design of the integrated circuit comprises the following steps:
step S1: a back-end design tool acquires original data and updated data;
step S2: forming data difference information by comparing the original data and the updated data, and analyzing the data difference information to generate an execution command;
step S3: executing the execution command to synthesize design data for a fast channel design;
step S4: applying the design data to an actual engineering design to record key execution information;
step S5: and analyzing and judging whether the key execution information meets the preset design standard, if so, outputting correct result data, and otherwise, outputting wrong result data and executing the step S2.
According to the above technical solution, in step S1, the original data includes an original SDC file and an original netlist file, and the updated data includes an updated SDC file and an updated netlist file.
According to the above technical solution, in step S2, the execution command includes, but is not limited to, a data strip command, a data processing command, a data composition command, and a data comparison verification command.
According to the above technical solution, in step S2, the data difference information includes the content and type of the data.
According to the above technical solution, in step S2, the back-end design tool analyzes the data difference information, specifically: the content and type of data is defined and validated.
According to the above technical solution, in step S3, the back-end design tool sequentially executes a data stripping command, a data processing command, a data composition command, and a data comparison verification command.
The method for designing the fast channel of the semi-customized back end design of the integrated circuit has the advantages of avoiding the back end design from lagging the front end design, enabling the back end design to be synchronously carried out with the front end design in advance, improving the design efficiency of a back end design link and shortening the design period of the whole chip.
Drawings
Fig. 1 is a block flow diagram of a preferred embodiment of the present invention.
Fig. 2 is a flow chart of the data acquisition part of the preferred embodiment of the present invention.
FIG. 3 is a flow diagram of the execute command portion of the preferred embodiment of the present invention.
FIG. 4 is a flow diagram of processing a portion of synthetic design data in accordance with a preferred embodiment of the present invention.
FIG. 5 is a flow diagram of the verify correctness portion of the preferred embodiment of the present invention.
Detailed Description
The invention discloses a method for designing a fast channel of an integrated circuit semi-custom back end design, and the specific implementation mode of the invention is further described by combining the preferred embodiment.
Referring to fig. 1 of the drawings, fig. 1 shows a specific flow of the integrated circuit semi-custom back-end design fast channel design method. Referring to fig. 2 to 5 of the drawings, preferably, the integrated circuit semi-custom back-end design fast channel design method includes the following steps:
step S1: a back-end design tool acquires original data and updated data;
step S2: forming data difference information by comparing the original data and the updated data, and analyzing the data difference information to generate an execution command;
step S3: executing the execution command to synthesize design data (new data) for a fast channel design;
step S4: applying (importing and executing) the design data to an actual engineering design to record key execution information;
step S5: and analyzing and judging whether the key execution information meets the preset design standard, if so, outputting correct result data, and otherwise, outputting wrong result data and executing the step S2.
In step S1, the original data includes an original SDC file and an original netlist file, and the updated data includes an updated SDC file and an updated netlist file. We define that the original data is the data used in the current stage (including the relevant data returned due to the output of the erroneous result data in step S5), and the updated data is the data that has been completed in the front-end design process but has not been generated by the preceding design step.
In step S2, the execution command includes, but is not limited to, a data strip command, a data processing command, a data composition command, and a data comparison and verification command.
In step S2, the data difference information includes the content and type of the data.
In step S2, the back-end design tool analyzes the data difference information, specifically: the content and type of data is defined and validated.
In step S3, the back-end design tool executes the data stripping command, the data processing command, the data synthesizing command, and the data comparison and verification command in sequence. In a data stripping link, new and old data are defined according to engineering design functions, content attributes, design stage and the like by running a data stripping command, and data stripping is carried out. And in the data processing link, useless parts in the old data are removed, and updated data which needs to be reserved in the new data are extracted. And integrating useful contents retained by new and old data in a data synthesis link to form complete design data. And carrying out integrity and correctness check on the design data in a data comparison and verification link.
In step S4, the correctness process of the final data in the engineering application is completed through this step, so that the data can be guaranteed to correctly operate in the actual engineering design link and obtain a correct and effective design result, and the main links are as follows: new data import, actual engineering application, data operation information recording and key execution data output. In the stage of verifying correctness, firstly, the obtained rapid channel design data is imported into an actual engineering project, then simple and rapid execution is carried out, meanwhile, the recording work of key information is carried out in the execution process, finally, the key execution information is analyzed, if the analysis result meets the design requirement, the passing information is output, otherwise, error result data is output, and the error result data is fed back to the link of executing the command for reprocessing.
It is worth mentioning that after the fast channel design data passes the correctness verification, the fast channel design data can be output to the back end design link for engineering design, so that the subsequent back end design link is updated and synchronized in time, the problem of time waste caused by design pause is avoided, and meanwhile, the latest design parameters are obtained by design in advance and the design strategy conforming to the latest design is determined in advance.
It should be noted that at the end of each of steps S1-S5, the data and/or commands generated in this step are temporarily stored in the designated location for reading and use in the next step.
It will be apparent to those skilled in the art that modifications and equivalents may be made in the embodiments and/or portions thereof without departing from the spirit and scope of the present invention.
Claims (6)
1. A method for designing a fast channel of an integrated circuit semi-custom back end design is characterized by comprising the following steps:
step S1: a back-end design tool acquires original data and updated data;
step S2: forming data difference information by comparing the original data and the updated data, and analyzing the data difference information to generate an execution command;
step S3: executing the execution command to synthesize design data for a fast channel design;
step S4: applying the design data to an actual engineering design to record key execution information;
step S5: and analyzing and judging whether the key execution information meets the preset design standard, if so, outputting correct result data, and otherwise, outputting wrong result data and executing the step S2.
2. The method of claim 1, wherein in step S1, the original data comprises an original SDC file and an original netlist file, and the updated data comprises an updated SDC file and an updated netlist file.
3. The method of claim 1, wherein in step S2, the execution commands include, but are not limited to, a data strip command, a data process command, a data composition command, and a data verification command.
4. The method of claim 3, wherein in step S2, the data difference information includes the content and type of data.
5. The method of claim 4, wherein in step S2, the back-end design tool analyzes the data difference information, specifically: the content and type of data is defined and validated.
6. The method of claim 3, wherein in step S3, the back-end design tool sequentially executes a data strip command, a data process command, a data composition command and a data verification command.
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