CN108022548B - Scanning direction control circuit, grid drive circuit and display device - Google Patents
Scanning direction control circuit, grid drive circuit and display device Download PDFInfo
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- CN108022548B CN108022548B CN201810103391.8A CN201810103391A CN108022548B CN 108022548 B CN108022548 B CN 108022548B CN 201810103391 A CN201810103391 A CN 201810103391A CN 108022548 B CN108022548 B CN 108022548B
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The disclosure provides a scanning direction control circuit, a grid drive circuit and a display device. The method is applied to the technical field of display. The scanning direction control circuit includes: a first switching unit for being turned on under the control of a signal of a first node to input an output signal of the first shift register to the second shift register; a first compensation unit for being turned on under the control of a power supply signal to transmit a first direction selection signal to a first node; the first coupling unit is connected between the second shift register and the first node; a second switching unit for being turned on under the control of a signal of a second node to input an output signal of the third shift register to the second shift register; the second compensation unit is used for conducting under the control of the power supply signal so as to transmit the second direction selection signal to the second node; and the second coupling unit is connected between the second shift register and the second node. The present disclosure can compensate for a signal output from the scan direction control circuit.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a scan direction control circuit, a gate driving circuit and a display device.
Background
With the development of optical and semiconductor technologies, flat panel displays represented by Liquid Crystal Displays (LCDs) and Organic Light Emitting Diodes (OLEDs) have the characteristics of Light and thin profile, low energy consumption, fast response speed, good color purity, high contrast, and the like, and are widely used in various electronic Display products.
At present, display devices mainly implement their display function through a pixel matrix. In the working process of the display device, an input signal is converted into a scanning signal for controlling the on/off of pixels through modules such as a shift register and the like by a gate drive circuit, and then the scanning signal is sequentially applied to scanning grid lines of pixels of each row of the display device so as to gate the pixels of each row.
The scanning mode of the gate driving circuit mainly includes unidirectional scanning and bidirectional scanning. The gate driving circuit having the bidirectional scanning function has a special application in some cases. For example, circuit verification may be implemented, i.e., verifying that a failure of the circuit occurs specifically in row number; in addition, image inversion or the like as shown in fig. 1 can also be realized without changing the data signal transmission order.
When the gate driving circuit realizes the bidirectional scanning function, a scanning direction control circuit is often required to be arranged. However, the scan direction control circuit in the prior art still has to be improved, for example, the output signal waveform of the scan direction control circuit has delay and large deformation.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a scan direction control circuit, a scan direction control method, and a display device, which overcome the problems of delay and large deformation of an output signal waveform of the scan direction control circuit caused by the limitations and disadvantages of the related art at least to a certain extent.
According to an aspect of the present disclosure, there is provided a scan direction control circuit including:
a first switching unit for being turned on under control of a signal of a first node to input an output signal of a first shift register to a second shift register adjacent to the first shift register;
a first compensation unit for being turned on under the control of a power supply signal to transmit a first direction selection signal to the first node;
the first coupling unit is connected between the second shift register and the first node;
a second switching unit for being turned on under control of a signal of a second node to input an output signal of a third shift register to the second shift register adjacent to the third shift register;
a second compensation unit for conducting under the control of the power signal to transmit a second direction selection signal to the second node;
and the second coupling unit is connected between the second shift register and the second node.
In an exemplary embodiment of the present disclosure, the first switching unit includes a first transistor, the first compensation unit includes a second transistor, the second switching unit includes a third transistor, the second compensation unit includes a fourth transistor, the first coupling unit includes a first capacitor, and the second coupling unit includes a second capacitor.
In an exemplary embodiment of the present disclosure, wherein:
the control end of the first transistor is connected with the first node, the first end of the first transistor is connected with the output end of the first shift register, and the second end of the first transistor is connected with the input end of the second shift register;
a control end of the second transistor receives the power supply signal, a first end of the second transistor receives the first direction selection signal, and a second end of the second transistor is connected with the first node;
the first end of the first capacitor is connected with the input end of the second shift register, and the second end of the first capacitor is connected with the first node;
a control end of the third transistor is connected with the second node, a first end of the third transistor is connected with an output end of the third shift register, and a second end of the third transistor is connected with an input end of the second shift register;
a control end of the fourth transistor receives the power supply signal, a first end of the fourth transistor receives the second direction selection signal, and a second end of the fourth transistor is connected with the second node;
and the first end of the second capacitor is connected with the input end of the second shift register, and the second end of the second capacitor is connected with the second node.
In an exemplary embodiment of the present disclosure, a characteristic parameter of the first transistor is the same as a characteristic parameter of the second transistor; the characteristic parameter of the third transistor is the same as that of the fourth transistor.
In an exemplary embodiment of the present disclosure, the first to fourth transistors are all P-type thin film transistors, and the power signal is a low level signal.
In an exemplary embodiment of the present disclosure, the first to fourth transistors are all N-type thin film transistors, and the power signal is a high level signal.
In an exemplary embodiment of the present disclosure, the first to fourth transistors are all amorphous silicon thin film transistors, metal oxide thin film transistors, or low temperature polysilicon thin film transistors.
In an exemplary embodiment of the present disclosure, the first direction selection signal is opposite in phase to the second direction selection signal.
According to an aspect of the present disclosure, there is provided a gate driving circuit, including a plurality of the scan direction control circuits described in any one of the above and a plurality of shift registers cascaded; wherein:
the first switch unit in the Mth scanning direction control circuit is connected with the signal output end of the M-1 th stage shift register, the second switch unit is connected with the signal output end of the M +1 th stage shift register, and the output end of the Mth scanning direction control circuit is connected with the input end of the Mth stage shift register.
According to an aspect of the present disclosure, there is provided a display device including the gate driving circuit described in any one of the above.
In a scanning direction control circuit provided by an exemplary embodiment of the present disclosure, by providing a first compensation unit and a first coupling unit, when a first direction selection signal is gated, a threshold voltage of the first compensation unit can be coupled to an output terminal of the scanning direction control circuit through the coupling unit, so that signal delay and signal deformation caused by the threshold voltage of the first switching unit can be compensated; by arranging the second compensation unit and the second coupling unit, the threshold voltage of the second compensation unit can be coupled to the output end of the scanning direction control circuit through the coupling unit when the second direction selection signal is gated, so that signal delay and signal deformation caused by the threshold voltage of the second switching unit can be compensated. Because the output signal of the scanning direction control circuit is compensated, the scanning signal output by the current shift register can be more accurate, and further, a better display effect can be realized.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:
FIG. 1 is a schematic view of an image flip;
FIG. 2 is a schematic diagram of a gate driver according to the related art;
FIG. 3 is a schematic diagram of a scan direction control circuit in the related art;
FIG. 4 is a simulation diagram of the output signals of the scan direction control circuit in FIG. 3;
FIG. 5 is a schematic diagram of a scan direction control circuit according to an exemplary embodiment of the disclosure;
FIG. 6 is a schematic diagram of a scan direction control circuit according to an exemplary embodiment of the disclosure;
fig. 7 is a schematic structural diagram of a gate driver in an exemplary embodiment of the disclosure;
FIG. 8 is a simulation diagram of the output signals of the scan direction control circuit in FIG. 6;
FIG. 9 is a schematic diagram of a scan direction control circuit according to an exemplary embodiment of the disclosure;
fig. 10 is a schematic structural diagram of a display device in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.
In the related art, the scan direction control circuit is easily implemented by a CMOS device, for example, because of an inverter, a transfer gate, and the like in the CMOS device. Referring to fig. 2, a gate driving circuit with bidirectional scanning function mainly includes cascaded shift registers SR 1-SR 5, and a scanning direction control circuit; the scanning direction control circuit is mainly composed of transmission gates. For example, the transmission gates TG2, TG3, TG6 and TG7 are controlled to be turned on by the first to fourth direction selection signals SEL1 to SEL4, so that the forward scanning of the gate driving circuit can be realized, i.e., the scanning direction is from the shift register SR1 to the shift register SR 5; the transmission gates TG8, TG5, TG4 and TG1 are controlled to be turned on by the first to fourth direction selection signals SEL1 to SEL4, so that the gate driving circuit can scan in the reverse direction from the shift register SR5 to the shift register SR 1.
However, in current flat panel display technologies, the CMOS devices are used less frequently, and only PMOS devices or only NMOS devices are used. As shown in fig. 3, a scan direction control circuit GC, which is constructed using only PMOS devices in the related art, mainly includes a first transistor M1 and a third transistor M3; fig. 4 is a simulation result of an output signal of the scanning direction control circuit GC. It can be seen that the signal output from the shift register SR3 passes through the first transistor M1 or the signal output from the shift register SR5 passes through the third transistor M3, and then delay and signal distortion occur, which cannot reach the lowest value of the initial signal. This problem is caused by the threshold voltages Vth of the first transistor M1 and the third transistor M3, which cannot be eliminated by optimizing the sizes of the first transistor M1 and the third transistor M3.
In view of the above problem, the present exemplary embodiment first provides a scanning direction control circuit. Referring to fig. 5, the scan direction control circuit may include: the circuit comprises a first switch unit, a first compensation unit, a first coupling unit, a second switch unit, a second compensation unit and a second coupling unit. Wherein the first switching unit may be configured to be turned on under control of a signal of a first node N1 to input an output signal of a first shift register to a second shift register adjacent to the first shift register; the first compensation unit may be configured to be turned on under the control of a power signal to transmit a first direction selection signal SEL1 to the first node N1; the first coupling unit is connected between the second shift register and the first node N1; the second switching unit may be configured to be turned on under control of a signal of a second node N2 to input an output signal of a third shift register to the second shift register adjacent to the third shift register; the second compensation unit may be configured to be turned on under the control of the power signal to transmit a second direction selection signal SEL2 to the second node N2; and a second coupling unit connected between the second shift register and the second node N2.
In the scanning direction control circuit of the present exemplary embodiment, by providing the first compensation unit and the first coupling unit, the threshold voltage of the first compensation unit can be coupled to the output terminal of the scanning direction control circuit through the coupling unit when the first direction selection signal SEL1 is gated, and thus the signal delay and the signal deformation due to the threshold voltage of the first switching unit can be compensated; by providing the second compensation unit and the second coupling unit, the threshold voltage of the second compensation unit can be coupled to the output terminal of the scan direction control circuit through the coupling unit when the second direction selection signal SEL2 is gated, and thus, signal delay and signal distortion due to the threshold voltage of the second switching unit can be compensated. Because the output signal of the scanning direction control circuit is compensated, the scanning signal output by the current shift register can be more accurate, and further, a better display effect can be realized.
Next, each part of the scanning direction control circuit in the present exemplary embodiment will be described in more detail.
Referring to fig. 6, in this example embodiment, the first switching unit may include a first transistor M1, the first compensation unit may include a second transistor M2, the second switching unit may include a third transistor M3, the second compensation unit may include a fourth transistor M4, the first coupling unit may include a first capacitor C1, and the second coupling unit may include a second capacitor C2. For example, the first transistor M1 to the fourth transistor M4 may be all amorphous silicon (a-Si) thin film transistors, or all Low Temperature Polysilicon (LTPS) thin film transistors, or all metal Oxide (Oxide) thin film transistors, and the like; the types of the first capacitor C1 and the second capacitor C2 may be selected according to requirements, for example, the capacitors may be MOS capacitors, metal capacitors, double poly capacitors, or the like, which is not limited in this exemplary embodiment. Of course, in other exemplary embodiments of the present disclosure, the scan direction control circuit may be formed by other types of switching devices or capacitive devices, which also falls within the scope of the present disclosure.
With continued reference to fig. 6, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 each have a control terminal, a first terminal and a second terminal. Wherein a control terminal of the first transistor M1 is connected to the first node N1, a first terminal (i.e., a first input terminal IN1) of the first transistor M1 is connected to the output terminal of the first shift register, and a second terminal (i.e., an output terminal OUT) of the first transistor M1 is connected to the input terminal of the second shift register. A control terminal of the second transistor M2 receives the power signal VGL, a first terminal of the second transistor M2 receives the first direction selection signal SEL1, and a second terminal of the second transistor M2 is connected to the first node N1. A first terminal of the first capacitor C1 is connected to the input terminal of the second shift register, and a second terminal of the first capacitor C1 is connected to the first node N1. A control terminal of the third transistor M3 is coupled to the second node N2, a first terminal (i.e., a second input terminal IN2) of the third transistor M3 is coupled to the output terminal of the third shift register, and a second terminal (i.e., an output terminal OUT) of the third transistor M3 is coupled to the input terminal of the second shift register. A control terminal of the fourth transistor M4 receives the power signal VGL, a first terminal of the fourth transistor M4 receives the second direction selection signal SEL2, and a second terminal of the fourth transistor M4 is connected to the second node N2. A first terminal of the second capacitor C2 is connected to the input terminal of the second shift register, and a second terminal of the second capacitor C2 is connected to the second node N2.
In this example embodiment, the first terminal of each of the transistors may be a source of the transistor, the second terminal of each of the transistors may be a drain of the transistor, and the control terminal of each of the transistors is a gate of the transistor. Of course, in other exemplary embodiments, the first end of each transistor may also be a drain of the transistor, and the second end of each transistor may also be a source of the transistor, which is not particularly limited in this disclosure.
Further, in order to ensure that accurate compensation is achieved, in the present exemplary embodiment, the characteristic parameters of the second transistor M2 are preferably the same as the characteristic parameters of the first transistor M1; the characteristic parameters of the fourth transistor M4 are preferably the same as those of the third transistor M3. For example, the first transistor M1 and the second transistor M2 may be made of the same material by the same process, and the first transistor M1 and the second transistor M2 have the same size (e.g., the same aspect ratio). Similarly, the third transistor M3 and the fourth transistor M4 may be made of the same material and by the same process, and the third transistor M3 and the fourth transistor M4 have the same size (e.g., the same aspect ratio).
Further, a gate driving circuit is also provided in the present exemplary embodiment. As described with reference to fig. 7, the gate driving circuit includes N shift registers (the rest of the shift registers are not shown) such as the first shift register SR1, the second shift register SR2, the third shift register SR3, the fourth shift register SR4, and the fifth shift register SR5, and N scanning direction control circuits (the rest of the scanning direction control circuits are not shown) such as the scanning direction control circuits GC1 to GC 5; each scanning direction control circuit is the scanning direction control circuit described above in this exemplary embodiment.
In the gate driving circuit, the first switch unit in the mth scanning direction control circuit is connected to the signal output terminal of the M-1 th stage shift register, the second switch unit is connected to the signal output terminal of the M +1 th stage shift register, and the output terminal of the mth scanning direction control circuit is connected to the input terminal of the mth stage shift register; wherein 1< M < N.
For example, taking the scan direction control circuit GC3 as the 3 rd example, as can be seen from fig. 6, the first terminal of the first transistor M1 of the scan direction control circuit GC3 is the first input terminal IN1, the first terminal of the second transistor M2 of the scan direction control circuit GC3 is the second input terminal IN1, and the second terminals of the first transistor M1 and the second transistor M2 of the scan direction control circuit GC3 are the output terminals OUT; the first input terminal IN1 of the scan direction control circuit GC3 is connected to the signal output terminal OUT of the 2 nd stage shift register SR2, the second input terminal IN2 of the scan direction control circuit GC3 is connected to the signal input terminal OUT of the 4 th stage shift register SR4, and the output terminal OUT of the scan direction control circuit GC3 is connected to the input terminal IN of the 3 rd stage shift register. Similarly, the first input terminal IN1 of the scan direction control circuit GC4 is connected to the signal output terminal OUT of the shift register SR3 of the 3 rd stage, the second input terminal IN2 of the scan direction control circuit GC4 is connected to the signal input terminal OUT of the shift register SR5 of the 5 th stage, and the output terminal OUT of the scan direction control circuit GC4 is connected to the input terminal IN of the shift register of the 4 th stage.
In the present exemplary embodiment, the first direction selection signal SEL1 is opposite in phase to the second direction selection signal SEL 2; the first direction selection signal SEL1 may be a forward direction selection signal, and the second direction selection signal SEL2 may be a reverse direction selection signal; of course, the first direction selection signal SEL1 may be a reverse direction selection signal, and the second direction selection signal SEL2 may be a forward direction selection signal. Taking the first to fourth transistors M4 in the scan direction control circuit GC3 as P-type thin film transistors, the power signal is a low level signal VGL as an example:
when the first direction selection signal SEL1 is at a low level, the second direction selection signal SEL2 is at a high level; the second transistor M2 and the fourth transistor M4 are turned on, and the first direction selection signal SEL1 is input to the first node N1 through the second transistor M2, thereby turning on the first transistor M1; the second direction selection signal SEL2 is input to the second node N2 through the fourth transistor M4, turning off the third transistor M3. After the first transistor M1 is turned on, the output signal of the 2 nd stage shift register SR2 is transmitted to the output terminal OUT of the scan direction control circuit GC3, and further transmitted to the 3 rd stage shift register SR 3; meanwhile, the threshold voltage Vth of the second transistor M2 is coupled to the output terminal OUT of the scan direction control circuit through the first capacitor C1, so that the signal at the output terminal OUT of the scan direction control circuit can be further pulled low, the compensation of the signal at the output terminal OUT of the scan direction control circuit is realized, and the 3 rd-stage shift register SR3 is ensured to receive an accurate input signal. Similarly, the output signal of the 3 rd stage shift register SR3 will be transmitted to the 4 th stage shift register SR4, the output signal of the 4 th stage shift register SR4 will be transmitted to the 5 th stage shift register SR5, and so on, to realize the forward scan.
When the second direction selection signal SEL2 is at a low level, the first direction selection signal SEL1 is at a high level; the second transistor M2 and the fourth transistor M4 are turned on, and the first direction selection signal SEL1 is input to the first node N1 through the second transistor M2, so that the first transistor M1 is turned off; the second direction selection signal SEL2 is input to the second node N2 through the fourth transistor M4, turning on the third transistor M3. After the third transistor M3 is turned on, the output signal of the 4 th stage shift register SR4 is transmitted to the output terminal OUT of the scan direction control circuit GC3, and further transmitted to the 3 rd stage shift register SR 3; meanwhile, the threshold voltage Vth of the fourth transistor M4 is coupled to the output terminal OUT of the scan direction control circuit through the second capacitor C2, so that the signal at the output terminal OUT of the scan direction control circuit can be further pulled low, the compensation of the signal at the output terminal OUT of the scan direction control circuit is realized, and the 3 rd-stage shift register SR3 is ensured to receive an accurate input signal. Similarly, the output signal of the 3 rd stage shift register SR3 is transmitted to the 2 nd stage shift register SR2, the output signal of the 2 nd stage shift register SR2 is transmitted to the 1 st stage shift register SR1, and so on, to realize the reverse scan.
Further, referring to fig. 8, a simulation result of an output signal of the scanning direction control circuit in the present exemplary embodiment is shown; as can be seen from comparison with fig. 4, the delay and waveform of the output signal of the scanning direction control circuit in the present exemplary embodiment are significantly improved.
In the above-described exemplary embodiment, the description has been given taking as an example that the first to fourth transistors M4 are all P-type thin film transistors; however, referring to fig. 9, in other exemplary embodiments of the disclosure, the first transistor M1 to the fourth transistor M4 may be all N-type thin film transistors, and accordingly, the power signal is a high level signal VGH. Those skilled in the art will readily understand that the level signals input by the respective signal terminals and their timing states may vary accordingly for different types of transistors.
The present exemplary embodiment further provides a display device, and referring to fig. 10, the display device 1000 may include a display panel 1001 and the gate driving circuit 1002. Since the scanning signal output by the included gate driving circuit 1002 is more accurate, the display device can achieve a better display effect, and user experience can be further improved.
Further, the Display device in the present exemplary embodiment may be a variety of flat Panel Display devices such as a liquid crystal Display device, an OLED (Organic Light Emitting Diode) Display device, a PLED (Polymer Light Emitting Diode) Display device, and a PDP (Plasma Display Panel) Display device, and the application of the Display device is not particularly limited herein.
It should be noted that: the specific details of each module unit in the display device have been described in detail in the corresponding scan direction control circuit, and therefore are not described herein again.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A scan direction control circuit, comprising:
a first switching unit for being turned on under control of a signal of a first node to input an output signal of a first shift register to a second shift register adjacent to the first shift register;
a first compensation unit for being turned on under the control of a power supply signal to transmit a first direction selection signal to the first node;
the first coupling unit is connected between the input end of the second shift register and the first node;
a second switching unit for being turned on under control of a signal of a second node to input an output signal of a third shift register to the second shift register adjacent to the third shift register;
a second compensation unit for conducting under the control of the power signal to transmit a second direction selection signal to the second node;
and the second coupling unit is connected between the input end of the second shift register and the second node.
2. The scan direction control circuit according to claim 1, wherein the first switching unit includes a first transistor, the first compensation unit includes a second transistor, the second switching unit includes a third transistor, the second compensation unit includes a fourth transistor, the first coupling unit includes a first capacitor, and the second coupling unit includes a second capacitor.
3. The scan direction control circuit according to claim 2, wherein:
the control end of the first transistor is connected with the first node, the first end of the first transistor is connected with the output end of the first shift register, and the second end of the first transistor is connected with the input end of the second shift register;
a control end of the second transistor receives the power supply signal, a first end of the second transistor receives the first direction selection signal, and a second end of the second transistor is connected with the first node;
the first end of the first capacitor is connected with the input end of the second shift register, and the second end of the first capacitor is connected with the first node;
a control end of the third transistor is connected with the second node, a first end of the third transistor is connected with an output end of the third shift register, and a second end of the third transistor is connected with an input end of the second shift register;
a control end of the fourth transistor receives the power supply signal, a first end of the fourth transistor receives the second direction selection signal, and a second end of the fourth transistor is connected with the second node;
and the first end of the second capacitor is connected with the input end of the second shift register, and the second end of the second capacitor is connected with the second node.
4. The scan direction control circuit according to claim 2 or 3, wherein a characteristic parameter of the first transistor is the same as a characteristic parameter of the second transistor; the characteristic parameter of the third transistor is the same as that of the fourth transistor.
5. The scan direction control circuit of claim 4, wherein the first to fourth transistors are all P-type thin film transistors, and the power signal is a low level signal.
6. The scan direction control circuit of claim 4, wherein the first to fourth transistors are all N-type thin film transistors, and the power signal is a high level signal.
7. The scan direction control circuit according to claim 4, wherein the first to fourth transistors are all amorphous silicon thin film transistors, metal oxide thin film transistors, or low temperature polysilicon thin film transistors.
8. The scan direction control circuit according to any one of claims 1 to 3 or 5 to 7, wherein the first direction selection signal and the second direction selection signal have opposite phases.
9. A gate drive circuit comprising a plurality of scan direction control circuits according to any one of claims 1 to 8 and a plurality of shift registers in cascade; wherein:
the first switch unit in the Mth scanning direction control circuit is connected with the signal output end of the M-1 th stage shift register, the second switch unit is connected with the signal output end of the M +1 th stage shift register, and the output end of the Mth scanning direction control circuit is connected with the input end of the Mth stage shift register.
10. A display device comprising the gate driver circuit according to claim 9.
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| CN104821159B (en) * | 2015-05-07 | 2017-04-12 | 京东方科技集团股份有限公司 | Gate driving circuit, display panel and touch display device |
| CN106328074B (en) * | 2015-06-25 | 2019-06-25 | 群创光电股份有限公司 | Image display system and gate driving circuit |
| CN104933990B (en) * | 2015-06-30 | 2017-03-22 | 上海天马有机发光显示技术有限公司 | A shift register unit, a driving method and a grid electrode drive circuit |
| CN106057131B (en) * | 2016-05-27 | 2018-11-23 | 武汉华星光电技术有限公司 | Scan drive circuit and flat display apparatus with the circuit |
| CN106356019B (en) * | 2016-11-28 | 2019-05-17 | 京东方科技集团股份有限公司 | Select connection unit, shift register and display panel |
| CN107610637B (en) * | 2017-11-03 | 2020-11-20 | 武汉天马微电子有限公司 | Display panel, display method thereof and electronic equipment |
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2018
- 2018-02-01 CN CN201810103391.8A patent/CN108022548B/en active Active
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| CN108022548A (en) | 2018-05-11 |
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