CN108011683B - Large-scale synthesis sensing system multistage distributes time-frequency unified approach - Google Patents
Large-scale synthesis sensing system multistage distributes time-frequency unified approach Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
Abstract
A kind of large-scale synthesis sensing system multistage disclosed by the invention distributes time-frequency unified approach, it is desirable to provide a kind of time-frequency is unified reliable, enough the multistage distribution time-frequency unified approach of reduction resource overhead.The technical scheme is that: reference time frequency generation module distributes fiducial time and reference frequency to time trunk module by point-to-point discrete lines, frequency terminal and frequency terminal when 2 class when time trunk module continues to distribute fiducial time to 1 class, frequency network controller will be transferred on network fiducial time, 1 class, frequency terminal is synchronous with externally input fiducial time in real time when 2 class, wherein frequency terminal is kept time in sync interval using the reference frequency of frequency trunk module input when 1 class, frequency terminal is kept time using own frequency source when 2 class, frequency terminal is synchronized using real-time with the received time data packet of network when 3 class, and it is kept time using time chip come the time-frequency unified shader of multistage distribution.
Description
Technical field
The present invention relates to a kind of avionics industrial circles, are mainly used in comprehensive sensor system, provide one kind
Based on classifying towards time-frequency index demand to time-frequency application terminal, different designs are carried out for different classifications, take multistage
Distributed architecture design is cascaded, Lai Tigao time-frequency unifies performance and reduces the time-frequency unified approach of resource overhead.
Background technique
Hardware synthesis, software synthesis, informix and function synthesized avionics system become increasingly complex, degree of integration
It is higher and higher.Synthesis is advanced to data processing from display, and is advanced to sensing system.In such a system, with more
The shared resource module of kind realizes various functions, can not divide the boundary line of traditional each subsystem again.In avionics system
Introduce the concept of comprehensive sensor system (ISS).Large-scale synthesis sensing system sensor type is numerous, and system composition is multiple
Miscellaneous, equipment isomery, distribution wide area, the time-frequency application terminal type multi-quantity of sensor is big, and the index request unified to time-frequency has
Height has low.Not only there is the time-frequency in platform between function sensor to unify demand, and this platform feature sensor also need with
Time-frequency in system between other platforms unifies demand.But it is different that these time-frequencies unify demand parameter, there is precise synchronization
Demand also has the time synchronization demand of low precision, there is the accuracy to reference frequency source, stability and all kinds of indexs such as mutually make an uproar
Different brackets demand.Large-scale synthesis sensing system time-frequency function of unity not only needs to generate and distribute reference time information, base
Quasi- frequency signal will also distribute the sampling pulse signal with reference time information second leading edge synchronization, it is also necessary to guarantee that each time-frequency is answered
With terminal to synchronous holding.Generally for the time-frequency unified metric for meeting a large amount of time-frequency application terminals, require from time-frequency base
Quasi-mode block obtains reference frequency and fiducial time does not have defeated firstly, time and frequency standards module is limited by internal resource and interface
The ability of big quantity reference time frequency out, secondly, the crosslinking cable between time and frequency standards module and time-frequency application terminal can be very more
And disorderly, it is unfavorable for engineering joint-trial and troubleshooting.Finally, when time-frequency application terminal performance requirement has height to have low, if according to most
High target carries out identical design, equally will increase the resource overhead of time and frequency standards module and the distribution expense of reference time frequency, and
And because time-frequency application terminal resource composition and interface are different in system, some time-frequency application terminals have FPGA resource, can connect
It receives the split-second precision transmitted by discrete lines with the light velocity and receives reference frequency, some time-frequency application terminals, which are only capable of receiving, to be passed through
The split-second precision that discrete lines are transmitted with the light velocity, but do not support to receive reference frequency, also some time-frequency application terminals only have CPU money
The module in source, can only receiving network data packet time service, this kind of time-frequency application terminal, which cannot be received, is transmitted by discrete lines with the light velocity
Split-second precision.So large-scale synthesis sensing system time-frequency Uniting should carry out classification to each time-frequency application terminal and examine
Consider, take multi-stage cascade distributed architecture, various performance requirements is met with the smallest resource overhead, to ensure that various sensors are equal
The time synchronization information for meeting index request can be obtained.
Summary of the invention
The purpose of the present invention is big, interface and resource types for large-scale synthesis sensing system time-frequency application terminal quantity
Different and different index request features, provides that a kind of time-frequency is unified reliable, and time-frequency unifies performance height, while can reduce money again
The large-scale synthesis sensing system multistage of source expense distributes time-frequency unified approach.
The present invention solves scheme used by prior art problem: when a kind of large-scale synthesis sensing system multistage is distributed
Frequency unified approach, it is characterised in that include the following steps: for the reference time frequency generation module for belonging to system public module to be deployed in
In rack where system resource, selection is located at the interface processing module in rack/cabinet and carries out time-frequency relay process；When benchmark
Frequency terminal, 2 when time-frequency application terminal is divided into 1 class according to time-frequency index demand, interface type and resource type by frequency generation module
Frequency terminal and frequency terminal when 3 class when class；Then different distributed architectures is set up for different classes of time-frequency application terminal；Benchmark
Time-frequency generation module distributes fiducial time and reference frequency to time trunk module, time trunk module by point-to-point discrete lines
Frequency terminal and frequency terminal when 2 class, frequency network controller will be transferred to network fiducial time when continuing to distribute fiducial time to 1 class
On, frequency terminal is real-time synchronous with externally input fiducial time when 1 class, 2 class, wherein frequency terminal is adopted in sync interval when 1 class
It is kept time with the reference frequency that frequency trunk module inputs, frequency terminal is kept time using own frequency source when 2 class, when 3 class
Frequency terminal is synchronized using real-time with the received time data packet of network, and is kept time using time chip come multistage distribution
Time-frequency unified shader.
The present invention has the following beneficial effects: compared with the prior art
Improve the reliability of time-frequency function of unity: the present invention is directed to the application terminal of big quantity, takes cascade multistage
Distribute time-frequency unified shader, traditional time-frequency Uniting resource centralized processing is improved to decentralized processing, time-frequency system can be reduced
The design pressure of one centralized processing reduces the failure rate of processing module work under high loads, base of the present invention in time-frequency Unified Set
Punctual frequency module only generates a small amount of reference time frequency signal, carries out time-frequency relaying in conjunction with the interface processing module in rack/cabinet
Processing, it is clear to the connection cables quantity reduction of multiple time-frequency trunk modules, connection relationship not only to generate in this way from reference time frequency,
And the connection relationship of time-frequency application terminal is also clear succinct out of time-frequency trunk module to this subdomain, be conducive to system integration test and
Fault Isolation improves the reliability of time-frequency function of unity.
It is high that reference time frequency distributes precision.The present invention is based on classifying towards time-frequency index demand to time-frequency application terminal,
Different designs are carried out for different classifications, multi-stage cascade distributed architecture is taken to design.First, frequency trunk module of the present invention receives
Externally input reference frequency exports after distinguishing amplification, ensure that the channelized frequencies of output and the reference frequency phase of input
Ginseng, at the same also ensure the channelized frequencies of output have with input reference frequency have it is identical mutually make an uproar, accuracy and stability etc.
Performance level.Second, time trunk module of the invention uses externally input reference frequency, firstly, with externally input benchmark
Time synchronizing error will be a stationary value in known section, and section is greater than 0 less than 1 system clock, secondly
When carrying out the compensation of second level distribution path, compensation error also can be a stationary value, finally, inputting interval in external fiducial time
It is interior, it is punctual by reference frequency inside time trunk module, time keeping error will not be generated.If time trunk module is using included
Independent clock frequency, then synchronous error, time keeping error and distribution error all can be a changing values, since steady state error more holds
Easily reduce and eliminate by calibration or estimation, thus when improving 1,2 class frequency terminal distribution precision.Third, the present invention from
The fiducial time distribution frequency of reference time frequency to network controller is greater than 10Hz, and frequency terminal is real using net distribution when because of third class
Existing time synchronization, when the input of outside reference time, time chip time on network controller with regard to it is outer synchronize it is primary, realize and
The precise synchronization of fiducial time relies on network controller temporal chip maintenance time, frequent distribution within synchronizing cycle
Synchronizing cycle can be greatly reduced, to reduce time keeping error, to improve the distribution precision of frequency terminal when 3 class.
Time-frequency terminal time net synchronization capability is high.First, frequency terminal is using external input benchmark frequency when 1 class in the present invention
Rate, within input interval external fiducial time, first kind time-frequency terminal inner is punctual by the reference frequency of input, because of first
Frequency terminal is exactly to generate and safeguard the reference frequency of fiducial time in input interval fiducial time punctual clock frequency when class,
So time keeping error will not be generated, so that frequency terminal has the time synchronization performance of highest level when the first kind.Second, of the invention
In 2 class when frequency terminal do not use external input reference frequency, using included clock frequency source come timing in clock synchronization interval,
Because there are accuracy differences for included frequency source and reference frequency, this results in time keeping errors, and the clock synchronization moment can also generate one
A time step, the present invention is by the corresponding time scale of real-time count value, to eliminate time keeping error, to further disappear
Except time step, the time synchronization performance of frequency terminal when improving the second class.Third, frequency terminal uses net when 3 class in the present invention
Time synchronization is realized in network distribution, and network controller is by network high-frequency degree (such as 50Hz) the broadcast reference time, and time-frequency application is eventually
End often receives the time difference that a packet reference time data just calculates input time numerical value and temporal chip time, and to time difference value
It is filtered, carries out time synchronization in conjunction with filtered time difference value and temporal chip time.Frequency terminal is because right when 3 class
When frequency improve, clock synchronization interval becomes smaller, is reduced by here every interior time keeping error, thus when reaching frequency terminal when improving 3 class
Between net synchronization capability effect.
Time-frequency function of unity resource overhead is small.The present invention is based on divide towards time-frequency index demand time-frequency application terminal
Class carries out different designs for different classifications, takes multi-stage cascade distributed architecture to design, to meet all time-frequency applications in system
Demand of the terminal to time-frequency is target, by classifying to time-frequency application terminal, according to time-frequency application terminal performance requirement
Just, different classifications take different design cost, guarantee to reduce the resource in system design while meeting performance
Expense, interface overhead and connection line expense etc..
Present invention is mainly used for the time synchronizations of large-scale synthesis sensing system.
Detailed description of the invention
This patent is further illustrated with reference to the accompanying drawings and examples.
Fig. 1 is that functional block diagram is uniformly processed in large-scale synthesis sensing system multistage distribution time-frequency of the present invention.
Fig. 2 is the multi-stage cascade distributed architecture functional block diagram to first kind time-frequency application terminal distributed architecture in Fig. 1.
Specific embodiment
Refering to fig. 1.In large-scale rf integration electronic system, index master of all the sensors to reference frequency in system
To include high accuracy, long-term stability, short-term stability, mutually make an uproar, the indexs such as spuious and harmonic wave；Reference time frequency generation module category
In system public module, it generates fiducial time and reference frequency, is deployed in the rack where system resource.Reference frequency
Generate using atomic clock combination constant-temperature crystal oscillator design, the generation of fiducial time can be used high-precision time service type defend lead receiver obtain
The high-precision UTC time arrived can also be used the high accuracy data chain collaboration time of two-way time transfer comparison technology acquisition, may be used also
Using in system the inertial navigation time or RTC clock chip time etc..Fiducial time can be planned according to system task and be selected, and use
To realize the time synchronization between platform with all the sensors time-frequency application terminal in this plateform system.
According to the present invention, a kind of large-scale synthesis sensing system multistage distributes time-frequency unified approach, it is characterised in that including
Following steps: the reference time frequency generation module for belonging to system public module being deployed in the rack where system resource, selection
Interface processing module in rack/cabinet carries out time-frequency relay process；Reference time frequency generation module is needed according to time-frequency index
It asks, frequency terminal and frequency terminal when 3 class when frequency terminal, 2 class when time-frequency application terminal is divided into 1 class by interface type and resource type；
Then different distributed architectures is set up for different classes of time-frequency application terminal；Reference time frequency generation module by it is point-to-point from
When loose wire distribution fiducial time and reference frequency continue to distribute fiducial time to 1 class to time trunk module, time trunk module
Frequency terminal when frequency terminal and 2 class, frequency network controller will be transferred on network fiducial time, when 1 class, 2 class frequency terminal in real time and
Externally input fiducial time is synchronous, wherein frequency terminal is in sync interval using the benchmark of frequency trunk module input when 1 class
Frequency is kept time, and frequency terminal is kept time using own frequency source when 2 class, and frequency terminal is using in real time and network reception when 3 class
Time data packet synchronize, and kept time using time chip come the time-frequency unified shader of multistage distribution.
After time trunk module pre-compensates for distribution transmission path delay, by the fiducial time after output compensating approach
Frequency terminal and 2 class time-frequencies of external input reference frequency are not received when multistage is distributed to 1 class for receiving external input reference frequency
Terminal, 3 class time-frequency application terminals often receive a packet network time data and just carry out a time synchronization and use temporal core
Piece is kept time.
Classify according to time-frequency index demand, interface type and resource type to time-frequency application terminal, the first kind is frequency
Rate coherent precise synchronization application terminal, the second class are precise synchronization application terminal of keeping time alone, and third class is
Time calibration in network time synchronization application terminal.
The first kind is that frequency coherent precise synchronization application terminal needs to constitute multi-stage cascade by dedicated discrete line
Distributed architecture distributes fiducial time and reference frequency, and time-frequency application terminal high-precise synchronization is on the time of input, between synchronization
It keeps time every the interior reference frequency using input.
Punctual precise synchronization application terminal only constitutes multi-stage cascade by dedicated discrete line to it to second class alone
Distributed architecture is distributed fiducial time, and time-frequency application terminal is synchronous on the time of input, passes through internal clocking in sync interval
It is counted, is synchronized in conjunction with count value and sync interval punctual in interval.
Third class time calibration in network time synchronization application terminal only passes through network to its broadcast reference time, time-frequency application terminal
Often receive the time difference that a packet reference time data just calculates input time numerical value and temporal chip time, and to time difference value into
Row filtering processing carries out time synchronization in conjunction with filtered time difference value and temporal chip time.
Frequency terminal 2 when frequency terminal 1,1 class when the one the second class time-frequency application terminals contain 1 class ... frequency terminal N when 1 class,
Frequency terminal 1 when 2 class, frequency terminal 2 ... contains 3 classes of connected network in frequency terminal N, third class time-frequency application terminal when 2 class when 2 class
When frequency terminal 1,3 class when frequency terminal 2 ... frequency terminal N when 3 class.
After carrying out three kinds of classification by above-mentioned time-frequency application terminal, then it is directed to the different distributed architecture of different classes of progress and sets
Meter and time synchronization design finally to meet in system all time-frequency application terminals to the index demand of time-frequency.For 1 class and 2 classes
Time-frequency application terminal, fiducial time use IRIG-B code agreement, and distribution content includes temporal information and time synchronization pulse.For
3 class time-frequency application terminals, it only includes temporal information that fiducial time, which distributes content,.
In setting up different distributed architectures, the comprising modules of time-frequency function of unity are set up, comprising modules specifically include that base
Punctual frequency generation module, time trunk module, frequency trunk module, network controller and time-frequency application terminal, wherein time-frequency is answered
It is usually the digital generic module of various kinds of sensors with terminal.Reference time frequency generation module passes through dedicated point-to-point discrete lines connection tool
Time trunk module, frequency trunk module and the network controller of having time relay function, time trunk module and frequency relaying
Module can be by point-to-point fixed connection time-frequency application terminal, and the interface mould being deployed in terminal or rack and cabinet
In block.Reference time frequency generation module exports the fiducial time after compensating approach after pre-compensating for distribution transmission path delay,
Time trunk module receives the fiducial time and externally input reference frequency that reference time frequency generation module exports, and realization and base
Synchronization between punctual is kept time, to distribution within input interval external fiducial time by externally input reference frequency
Transmission path delay exports the fiducial time after compensating approach after being pre-compensated for.
Time-frequency application terminal receives externally input fiducial time, realizes synchronous with fiducial time, wherein 1 class time-frequency
Terminal receives externally input reference frequency, punctual by internal reference frequency within input interval external fiducial time, and 2
It is punctual by internal clock frequency when class in frequency terminal input interval portion's fiducial time outside.
Reference time frequency module complete fiducial time and reference frequency generation, and carry out from reference time frequency module to it is multiple when
Between trunk module latency path compensation, then by multichannel point-to-point discrete lines, the benchmark that each road pre-compensated for is transmitted with the light velocity
Time is to corresponding time trunk module, using the fiducial time distribution formats of IRIG-B code agreement, transmission time information and time
Synchronous pulse per second (PPS), the multiple time trunk modules of high-precise synchronization, each time trunk module completion is synchronous with the input reference time,
Keeping time in interval is synchronized by externally input reference frequency, while being carried out multiple from time trunk module to this subdomain
The time-delay precompensation of time-frequency application terminal, then when transmitting the benchmark that each road pre-compensated for by multichannel point-to-point discrete lines with the light velocity
Between arrive corresponding time-frequency application terminal, the multiple time-frequency application terminals of this subdomain of high-precise synchronization, each subdomain time-frequency application terminal complete
It is punctual in synchronous and sync interval with the input reference time, to realize all time-frequencies application of each subdomain in system eventually
The time synchronization at end.
The fiducial time that reference time frequency module generates transmits fiducial time to network by road point-to-point discrete lines, with the light velocity
Controller, network controller complete punctual in sync interval, completion and input reference within synchronizing cycle by time chip
The synchronization of time, then by Web broadcast fiducial time, time-frequency application terminal often receive a packet reference time data just calculate it is defeated
The time difference of angle of incidence numerical value and temporal chip time, and time difference value is filtered, in conjunction with filtered time difference value
Time synchronization is carried out with temporal chip time, to realize the time synchronization of all 3 class time-frequency application terminals in system.
It is related according to the accuracy of frequency terminal clock frequency when pervious time keeping error and 2 class.When in order to eliminate 2 class
The time keeping error of frequency terminal, the present embodiment eliminate time keeping error by the corresponding time scale of real-time count value, when
It being counted in interval time T using system work clock, count value N is latched and is reset when reaching by+1 external input time of kth,
This N value is the numerical value of a real-time update, updates numerical value of N according to formula k+1 punctual intervalsk+1=(1- α) × Nk+α×N
It calculates to update and obtains Nk+1, wherein k indicates serial number, and α is the decimal between 0 to 1, then each counting in kth+1 punctual interval
Being worth corresponding time scale isSo as to basisIt is corresponding that kth+1 punctual interval count value i is calculated
Time T(k+1,i),When realizing 2 class in frequency terminal input interval portion's fiducial time outside
Auto time determination.Thus count value carries out in real time, greatly reducing the input of adjacent external fiducial time in conjunction with time scale is calculated
Time keeping error in interval.
In third class time-frequency application terminal, reference time frequency generation module connects network control by dedicated point-to-point discrete lines
Device processed does not have the logical resource similar with fpga chip yet and is used to handle timing because network controller does not receive reference frequency
And counting, so included real-time clock RTC chip can only be used to keep time in fiducial time input interval, because of its time standard
Exactness is lower, frequency terminal time keeping error when in order to reduce 3 class, reference time frequency generation module with not less than 10Hz frequency by from
Loose wire distributes fiducial time to network controller, and network controller often receives the fiducial time once inputted, just realizes RTC time
It is synchronous with the input reference time；Then, network controller is continued by network to 3 class time-frequency terminal broadcast fiducial times；Together
Frequency terminal can only use included real-time clock RTC chip keep time when sample is because of 3 class, equally because of real-time clock RTC accuracy
It is horizontal lower, and accuracy when 3 class between frequency terminal is widely different, time synchronization when in order to improve 3 class between frequency terminal
Precision, network controller are calculated, acquisition is less than with the frequency broadcast reference time of 50Hz with frequency terminal accuracy 10ppm when 3 class
The time keeping error of 0.2 μ s.Finally, frequency terminal is primary defeated according to the fiducial time calculating for often receiving network controller broadcast when 3 class
Enter fiducial time TinWith clock chip RTC time TrtcTime difference Δ=Tin-Trtc, and smothing filtering is carried out to time difference value
Processing, the time difference value Δ after obtaining smothing filteringk+1, Δk+1=(1- α) × Δk+ α × Δ, wherein α is small between 0 to 1
Number, ΔkFor the time difference value before updating, frequency terminal is according to formula T when 3 classk=Δk+1+TrtcIt calculates in real time, acquisition and fiducial time
Synchronous local zone time Tk。
Refering to Fig. 2.Fig. 2 has done more detailed logical partitioning to the first kind time-frequency application terminal distributed architecture in Fig. 1.?
After large-scale synthesis sensing system completes installation, the level-one time delay on the road M is estimated or demarcated respectively, by what is estimated or demarcate
1 value of level-one time delay, 2 value of level-one time delay ... level-one time delay M value is written in the nonvolatile storage of reference time frequency module, together
Sample carries out budget or directly calibration to the second level time delay on the road N in subdomain respectively, by 1 value of second level time delay of estimation or calibration, second level
2 value of time delay ... second level time delay N value is written in the nonvolatile storage of the corresponding time trunk module of this subdomain.Reference time frequency
Generation module is completed reference time frequency and is generated, and generates level-one time-delay precompensation according to reference time frequency: respectively corresponding son according to storage
Domain 1, subdomain 2 ... subdomain M M level-one time delay value carry out level-one delay compensation, and by the compensated road M fiducial time correspondence give
To M time trunk module, each time trunk module completes benchmark frequency synchronous with the outside reference time, and passing through input
Rate synchronizes keeping time in interval, respectively corresponds progress second level delay compensation according still further to N number of second level time delay value of storage, and will
The compensated road N fiducial time is corresponding give first kind time-frequency application terminal when frequency terminal 1, when frequency terminal 2 ... when frequency terminal
N, each 1 class time-frequency application terminal is completed and outside reference time synchronization, and between being synchronized by the reference frequency of input
It keeps time every interior, to realize the precise synchronization in system between all first kind time-frequencies application terminal.
Claims (9)
1. a kind of large-scale synthesis sensing system multistage distributes time-frequency unified approach, it is characterised in that include the following steps: to belong to
It is deployed in the rack where system resource in the reference time frequency generation module of system public module, selection is located at rack/cabinet
In interface processing module carry out time-frequency relay process；Reference time frequency generation module according to time-frequency index demand, interface type and
Frequency terminal and frequency terminal when 3 class when frequency terminal, 2 class when time-frequency application terminal is divided into 1 class by resource type；Then it is directed to inhomogeneity
Set up different distributed architectures in other time-frequency application terminal；When reference time frequency generation module distributes benchmark by point-to-point discrete lines
Between and reference frequency frequency terminal and 2 class time-frequencies when continuing to distribute fiducial time to 1 class to time trunk module, time trunk module
Terminal, network controller will be transferred on network fiducial time, frequency terminal real-time and externally input fiducial time when 1 class, 2 class
It is synchronous, wherein frequency terminal is kept time in sync interval using the reference frequency of frequency trunk module input when 1 class, when 2 class
Frequency terminal is kept time using own frequency source, and frequency terminal with the received time data packet of network using carrying out together in real time when 3 class
Step, and kept time using time chip come the time-frequency unified shader of multistage distribution；When reference time frequency generation module completes benchmark
Frequency generates, and generates level-one time-delay precompensation according to reference time frequency: according to the M for respectively corresponding subdomain 1, subdomain 2 ... subdomain M of storage
A level-one time delay value carries out level-one delay compensation, and gives the compensated road M fiducial time correspondence to M time trunk module,
Each time trunk module completion is synchronous with the outside reference time, and is synchronized in interval by the reference frequency of input
It is punctual, progress second level delay compensation is respectively corresponded according still further to N number of second level time delay value of storage, and compensated N roadbed is punctual
Between it is corresponding give first kind time-frequency application terminal when frequency terminal 1, when frequency terminal 2 ... when frequency terminal N, each 1 class time-frequency application
Terminal is completed and outside reference time synchronization, and synchronizes keeping time in interval by the reference frequency of input, thus real
Precise synchronization in existing system between all first kind time-frequencies application terminal.
2. large-scale synthesis sensing system multistage as described in claim 1 distributes time-frequency unified approach, it is characterised in that: the time
After trunk module pre-compensates for distribution transmission path delay, the fiducial time multistage after output compensating approach is distributed to and is connect
Frequency terminal and frequency terminal when not receiving 2 class of external input reference frequency, 3 class time-frequencies when receiving 1 class of external input reference frequency
Application terminal is often received a packet network time data and just carries out a time synchronization and kept time using temporal chip.
3. large-scale synthesis sensing system multistage as described in claim 1 distributes time-frequency unified approach, it is characterised in that: first
Frequency terminal 2 when frequency terminal 1,1 class when second class time-frequency application terminal contains 1 class ... frequency terminal N when 1 class, frequency terminal when 2 class
Frequency terminal N when 2 class of frequency terminal 2 ... when 1,2 class, frequency terminal 1,3 when third class time-frequency application terminal contains 3 class of connected network
Frequency terminal 2 when class ... frequency terminal N when 3 class；For 1 class and 2 class time-frequency application terminals, fiducial time uses IRIG-B code agreement,
Distributing content includes temporal information and time synchronization pulse, and for 3 class time-frequency application terminals, fiducial time distribution content only includes
Temporal information.
4. large-scale synthesis sensing system multistage as described in claim 1 distributes time-frequency unified approach, it is characterised in that: in group
It builds in different distributed architectures, sets up the comprising modules of time-frequency function of unity, comprising modules specifically include that reference time frequency generates mould
Block, time trunk module, frequency trunk module, network controller and time-frequency application terminal, wherein time-frequency application terminal is all kinds of
The digital generic module of sensor.
5. large-scale synthesis sensing system multistage as described in claim 1 distributes time-frequency unified approach, reference time frequency generates mould
Block has time trunk module, frequency trunk module and the network-control of time relay function by the connection of point-to-point discrete lines
Device, time trunk module and frequency trunk module are deployed in terminal by point-to-point fixed connection time-frequency application terminal
Or in the interface module in rack and cabinet.
6. large-scale synthesis sensing system multistage as described in claim 1 distributes time-frequency unified approach, it is characterised in that: benchmark
Time-frequency generation module exports the fiducial time after compensating approach after pre-compensating for distribution transmission path delay, the time relays mould
Block receives the fiducial time and externally input reference frequency that reference time frequency generation module exports, and realizes same with fiducial time
Step is kept time within input interval external fiducial time by externally input reference frequency, when to distribution transmission path
Prolong and exports the fiducial time after compensating approach after being pre-compensated for.
7. large-scale synthesis sensing system multistage as described in claim 1 distributes time-frequency unified approach, it is characterised in that: benchmark
When frequency module complete fiducial time and reference frequency generation, and carry out from reference time frequency module to multiple time trunk modules
Latency path compensation, then by multichannel point-to-point discrete lines, with the light velocity transmit fiducial time that each road pre-compensated for it is corresponding when
Between trunk module, using the fiducial time distribution formats of IRIG-B code agreement, transmission time information and time synchronization pulse per second (PPS) are high
The multiple time trunk modules of accurate synchronization, each time trunk module completion is synchronous with the input reference time, passes through external input
Reference frequency synchronize punctual in interval, while carrying out from time trunk module to the multiple time-frequency application terminals of this subdomain
Time-delay precompensation, then fiducial time that each road pre-compensated for is transmitted to corresponding time-frequency with the light velocity by multichannel point-to-point discrete lines
Application terminal, the multiple time-frequency application terminals of this subdomain of high-precise synchronization, when each subdomain time-frequency application terminal is completed with input reference
Between synchronization and sync interval in it is punctual, to realize that the time of all time-frequency application terminals of each subdomain in system is same
Step.
8. large-scale synthesis sensing system multistage as claimed in claim 3 distributes time-frequency unified approach, it is characterised in that: benchmark
When fiducial time for generating of frequency module by road point-to-point discrete lines, fiducial time is transmitted to network controller, network with the light velocity
Controller completes keeping time in sync interval by time chip within synchronizing cycle, and completion is synchronous with the input reference time,
Again by Web broadcast fiducial time, time-frequency application terminal often receive a packet reference time data just calculate input time numerical value and
The time difference of temporal chip time, and time difference value is filtered, in conjunction with filtered time difference value and temporal core
The piece time carries out time synchronization, to realize the time synchronization of all 3 class time-frequency application terminals in system.
9. large-scale synthesis sensing system multistage as described in claim 1 distributes time-frequency unified approach, it is characterised in that: benchmark
Time-frequency generation module distributes fiducial time to network controller by discrete lines with the frequency not less than 10Hz, and network controller is every
The fiducial time once inputted is received, realizes that RTC time is synchronous with the input reference time；Then, network controller passes through net
Network continued to 3 class time-frequency terminal broadcast fiducial times；Network controller is with the frequency broadcast reference time of 50Hz, with 3 class time-frequencies
Terminal accuracy 10ppm is calculated, and obtains the time keeping error less than 0.2 μ s；Finally, frequency terminal is according to often receiving network control when 3 class
The fiducial time of device broadcast processed calculates an input reference time TinWith clock chip RTC time TrtcTime difference Δ=
Tin-Trtc, and the disposal of gentle filter is carried out to time difference value, the time difference value Δ after obtaining smothing filteringk+1, Δk+1=(1- α) × Δk
+ α × Δ, wherein α is the decimal between 0 to 1, ΔkFor the time difference value before updating, frequency terminal is according to formula T when 3 classk=Δk+1+
TrtcIt calculates in real time, obtains the local zone time T synchronous with fiducial timek。
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