CN108009978B - Non-blocking parallel triangular rasterization unit structure - Google Patents
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Abstract
The invention provides a non-blocking parallel triangular rasterization unit structure which consists of 7 functional pipeline levels and sequentially comprises a triangular vertex receiving unit, a triangular scanning parameter establishing unit, an edge function method Tile scanning unit, a boundary Tile pixel position relation judging unit, a boundary Tile pixel anti-aliasing unit, a Tile attribute interpolation request arbitration unit and a Tile attribute interpolation unit from front to back. The invention has the capability of non-blocking parallel triangular block scanning and processing, divides the pixels Tile covered by the triangle into two types of completely inner Tile and partially inner Tile, and respectively sets two parallel processing channels, can realize the non-blocking parallel scanning of the two types of Tile on the premise of keeping the output sequence of the triangle Tile, improves the resource utilization rate, the triangle processing capability and the pixel generation capability, and is more effective for larger triangle primitives in particular.
Description
Technical Field
The invention belongs to the technical field of computer hardware, and relates to a non-blocking parallel triangular rasterization unit structure.
Background
With the increasing of graphics applications, it is difficult for early solutions of graphics rendering by CPU alone to meet the graphics Processing requirements of performance and technology growth, and Graphics Processing Units (GPUs) have come into play. From 1999, the first GPU product released by Nvidia to date, the development of GPU technology mainly goes through the fixed function pipeline stage, the separation stainer architecture stage, and the unified stainer architecture stage, the graphics processing capability of the GPU technology is continuously improved, and the application field is gradually expanded from the initial graphics drawing to the general computing field. The GPU pipeline has high speed, parallel characteristics and flexible programmability, and provides a good running platform for graphic processing and general parallel computing.
At present, no GPU based on a unified dyeing framework exists in China, and a large number of foreign imported commercial GPU chips are adopted in display control systems in various fields. Particularly, in the military field, the foreign imported commercial GPU chip has the defects of poor temperature and environmental adaptability, incapability of ensuring that the circuit or supporting software has no back door, contains a large number of redundant functional units which are not needed in the military field, incapability of meeting the requirements on power consumption indexes, quick update of the commercial GPU chip, difficulty in meeting the continuous guarantee of weaponry and the like, and has great hidden dangers in the aspects of safety, reliability, guarantee and the like. Moreover, for political, military, economic reasons and the like, technology blocking and product monopoly are carried out in China abroad, and bottom technical data of the GPU chip, such as register data, detailed internal micro-architecture, core software source codes and the like, are difficult to obtain, so that the functions and the performances of the GPU cannot be fully exerted, and the portability is poor; the problems seriously restrict the independent development and autonomous development of the display system in China.
The structural design of the GPU triangle rasterization unit is a key technology for improving and enhancing the triangle processing performance of a GPU graphic processor. The key technology of the structural design of the triangular rasterization unit of the high-performance GPU is broken through, and the development of a high-performance graphics processor chip is urgent.
Disclosure of Invention
The purpose of the invention is: the non-blocking parallel triangle rasterization unit structure not only can ensure the primitive scanning sequence, but also can realize continuous and parallel processing of triangle primitives, can reduce the scanning of invalid pixels, and better realizes the balance of processing performance, design scale, resource utilization rate and power consumption.
The technical scheme of the invention is as follows:
a non-blocking parallel triangular rasterization unit structure is composed of 7 functional pipeline levels, wherein the 7 functional pipeline levels sequentially comprise a triangular vertex receiving unit, a triangular scanning parameter establishing unit, an edge function method Tile scanning unit, a boundary Tile pixel position relation judging unit, a boundary Tile pixel anti-aliasing unit, a Tile attribute interpolation request arbitration unit and a Tile attribute interpolation unit from front to back according to the sequence from front to back, and the data output of the previous pipeline level is used as the data input of the next pipeline level;
the triangle vertex receiving unit receives a vertex attribute transmission command sent from the exterior of the rasterization unit, extracts vertex attribute data in the command, stores the vertex attribute data in a vertex attribute data buffer in the triangle vertex receiving unit, and then sends the vertex attribute data to the triangle scanning parameter establishing unit under the condition that the vertex attribute data buffer is not empty;
the triangle scanning parameter establishing unit receives the output data of the triangle vertex receiving unit, calculates all parameters used in the scanning and attribute interpolation process of the triangle in a pipelining manner, and sends the calculation result to the edge function method Tile scanning unit;
the edge function method Tile scanning unit receives the triangle primitive parameters sent by the triangle scanning parameter establishing unit, scans and calculates a triangle based on a pixel Tile by adopting an edge function discrimination algorithm in a pipelining mode, and obtains all pixels Tile covered by the triangle primitive according to the calculated position relationship between the vertex of the four corners of the pixel Tile and the triangle; further dividing the pixels Tile covered by the triangle into two types of pixels Tile which are completely in the triangle and pixels Tile which are partially in the triangle; wherein, the pixels Tile completely in the triangle directly send attribute interpolation requests to the Tile attribute interpolation request arbitration unit, and after being responded, the pixel Tile attribute data completely in the triangle are sent to the Tile attribute interpolation unit for attribute interpolation calculation of all pixels contained in the Tile; part of the pixels Tile in the triangle are sent to the boundary Tile pixel position relation determining unit for processing;
the boundary Tile pixel position relation judging unit receives partial pixel Tile data in a triangle from a side function Tile scanning unit, calculates the position relation between each pixel in the received pixel Tile and three sides of the triangle by using the recursion parameters calculated by the triangle scanning parameter establishing unit in a pipelining manner, and marks whether each pixel is in the triangle; according to whether a primitive anti-aliasing function is started or not, a processing result is sent to a boundary Tile pixel anti-aliasing unit or a Tile attribute interpolation request arbitration unit;
the boundary Tile pixel anti-aliasing unit judges the position relation between the received boundary Tile data and a triangle at a sub-pixel level under the condition of starting a primitive anti-aliasing function; according to the pixel Tile address, the boundary Tile pixel anti-aliasing unit can simply calculate the coordinate address of each pixel, and then according to the pixel coordinate address and the corresponding relation between the anti-aliasing grade and the sub-pixel address offset, the coordinate addresses of all sub-pixels in one pixel can be calculated; then finishing the position relation judgment of the sub-pixels and the triangle according to the coordinate addresses of all the sub-pixels; finally, according to the position relation between the sub-pixel contained in each pixel in the boundary pixel Tile and the triangle, determining the Alpha value weight of each pixel, and sending the result to a Tile attribute interpolation request arbitration unit;
the Tile attribute interpolation request arbitration unit simultaneously receives all pixels Tile in a triangle from an edge function method Tile scanning unit and processed pixels Tile in the triangle from a boundary Tile pixel anti-aliasing unit, selects one path of pixels Tile after arbitration and sends the pixels Tile to an attribute interpolation unit for attribute interpolation calculation; the arbitration strategy is that the pixels Tile partially in the triangle take precedence; another function of the Tile attribute interpolation request arbitration unit is rasterization sorting of triangle primitives, which identifies the condition that the rendering sequence of the triangle primitives is error, and ensures that the Tile attribute interpolation unit performs attribute interpolation on pixels Tile covered by the triangle primitives according to the sequence of the triangle primitives entering the rasterization unit;
the Tile attribute interpolation unit receives pixel Tile data from the Tile attribute interpolation request arbitration unit, performs pixel-by-pixel attribute interpolation calculation on the received pixel Tile in a pipeline mode based on a multi-path parallel attribute interpolation circuit, and the control circuit performs attribute interpolation according to the actual attribute quantity carried by each pixel and also needs perspective correction during attribute interpolation in a perspective scene.
The invention has the beneficial effects that:
the invention judges the position relation of tiles and triangle primitives in a parallel or pipelining mode by taking pixel blocks (tiles) with various sizes as units at different stages of a rasterization assembly line, thereby reducing the scanning of invalid pixels and better realizing the balance of processing performance, design scale, resource utilization rate and power consumption;
secondly, two parallel data channels are arranged for tiles on the triangle boundary and tiles completely in the triangle on the three-level pipeline path of the edge function method Tile scanning unit, the boundary Tile pixel position relation judging unit and the boundary Tile pixel anti-aliasing unit between the triangle parameter establishing level and the Tile attribute interpolation request arbitration unit: the boundary Tile channel and the completely inner Tile channel can perform parallel scanning output on the triangular boundary Tile channel and the completely inner Tile channel, realize non-blocking parallel scanning of the Tile on the premise of keeping the output sequence of the triangular Tile, improve the triangular processing capability and the pixel generation capability, and particularly for triangular primitives with a large proportion of the completely inner Tile and the boundary Tile, the scanning performance is improved more obviously;
in the scheme provided by the invention, the Tile attribute interpolation request arbitration unit has the capability of synchronizing and sequencing different triangle primitives. If the triangle boundaries Tile being processed in the boundary Tile processing unit all belong to the same triangle, then if the Tile scan unit outputs a full inner Tile, the Tile scan output unit sends an attribute interpolation request to the Tile attribute interpolation request arbitration unit to be responded. The processing of the boundary Tile and the completely inner Tile is parallel at this time, so that the full utilization of the computing resource of the attribute interpolation unit can be realized in most of the time.
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FIG. 1 is a schematic diagram of a non-blocking parallel triangular rasterization unit architecture of the present invention.
Detailed Description
The invention relates to a non-blocking parallel triangular rasterization unit structure which consists of 7 functional pipeline levels, wherein the 7 functional pipeline levels sequentially comprise a triangular vertex receiving unit, a triangular scanning parameter establishing unit, an edge function method Tile scanning unit, a boundary Tile pixel position relation judging unit, a boundary Tile pixel anti-aliasing unit, a Tile attribute interpolation request arbitration unit and a Tile attribute interpolation unit from front to back according to the sequence from front to back, and the data output of the previous pipeline level is used as the data input of the next pipeline level.
The triangle vertex receiving unit receives a vertex attribute transmission command sent from the exterior of the rasterization unit, extracts vertex attribute data in the command, stores the vertex attribute data in a vertex attribute data buffer in the triangle vertex receiving unit, and then sends the vertex attribute data to the triangle scanning parameter establishing unit under the condition that the vertex attribute data buffer is not empty.
The triangle scanning parameter establishing unit receives the output data of the triangle vertex receiving unit, calculates all parameters used in the scanning and attribute interpolation process of the triangle in a pipelining mode, and sends the calculation result to the edge function method Tile scanning unit.
The edge function method Tile scanning unit receives the triangle primitive parameters sent by the triangle scanning parameter establishing unit, scans and calculates a triangle based on a pixel Tile by adopting an edge function discrimination algorithm in a pipelining mode, and obtains all pixels Tile covered by the triangle primitive according to the calculated position relationship between the vertex of the four corners of the pixel Tile and the triangle; further dividing the pixels Tile covered by the triangle into two types of pixels Tile which are completely in the triangle and pixels Tile which are partially in the triangle; wherein, the pixels Tile completely in the triangle directly send attribute interpolation requests to the Tile attribute interpolation request arbitration unit, and after being responded, the pixel Tile attribute data completely in the triangle are sent to the Tile attribute interpolation unit for attribute interpolation calculation of all pixels contained in the Tile; and the pixels Tile partially inside the triangle are sent to the boundary Tile pixel position relation determination unit for processing.
The boundary Tile pixel position relation judging unit receives partial pixel Tile data in a triangle from a side function Tile scanning unit, calculates the position relation between each pixel in the received pixel Tile and three sides of the triangle by using the recursion parameters calculated by the triangle scanning parameter establishing unit in a pipelining manner and marks the position relation; each of the pixels Tile may be outside or inside the triangle. And finally, according to whether the primitive anti-aliasing function is started or not, selecting to send the processing result to a boundary Tile pixel anti-aliasing unit or a Tile attribute interpolation request arbitration unit.
And the boundary Tile pixel anti-aliasing unit judges the position relation between the received boundary Tile data and the triangle at a sub-pixel level under the condition of starting a primitive anti-aliasing function. According to the pixel Tile address, the boundary Tile pixel anti-aliasing unit can simply calculate the coordinate address of each pixel, and then according to the pixel coordinate address and the corresponding relation between the anti-aliasing grade and the sub-pixel address offset, the coordinate addresses of all sub-pixels in one pixel can be calculated; then finishing the position relation judgment of the sub-pixels and the triangle according to the coordinate addresses of all the sub-pixels; and finally, determining the Alpha value weight of each pixel according to the position relationship between the sub-pixel contained in each pixel in the boundary pixel Tile and the triangle, and sending the result to a Tile attribute interpolation request arbitration unit.
The Tile attribute interpolation request arbitration unit simultaneously receives all pixels Tile in the triangle and processed pixels Tile in the triangle from the pixel scanning unit, selects one path of pixels Tile after arbitration and sends the selected path of pixels Tile to the attribute interpolation unit for attribute interpolation calculation. The arbitration policy is that pixels Tile partially within the triangle take precedence. Another important function of the Tile attribute interpolation request arbitration unit is a rasterization sorting function of the triangle primitives, which can identify the condition that the drawing sequence of the triangle primitives is error, and ensure that the Tile attribute interpolation unit performs attribute interpolation on pixels Tile covered by the triangle according to the sequence of the triangle primitives entering the rasterization unit.
The Tile attribute interpolation unit receives pixel Tile data from the Tile attribute interpolation request arbitration unit, performs pixel-by-pixel attribute interpolation calculation on the received pixel Tile (completely or partially in-pixel Tile) in a pipeline mode based on a multi-path parallel attribute interpolation circuit, and the control circuit performs attribute interpolation according to the actual attribute quantity carried by each pixel and also needs perspective correction during attribute interpolation in a perspective scene. At this point, all processing of triangle rasterization is completed.
The non-blocking parallel triangular rasterization unit structure is characterized in that: in different stages of a rasterization assembly line, the position relation between tiles and triangle primitives is judged in a parallel or pipelining mode by taking pixel blocks (tiles) with different sizes as units, so that the balance among processing performance, design scale, resource utilization rate and power consumption is better realized.
The non-blocking parallel triangular rasterization unit structure is characterized in that: on three-level pipeline paths of a Tile scanning unit, a boundary Tile pixel position relation judging unit and a boundary Tile pixel anti-aliasing unit between a triangle parameter establishing level and a Tile attribute interpolation request arbitration unit, two parallel data channels are arranged for tiles on a triangle boundary and tiles completely in a triangle: and the boundary Tile channel and the completely inner Tile channel are used for performing parallel scanning output on the triangular boundary Tile channel and the completely inner Tile channel.
The non-blocking parallel triangular rasterization unit structure is characterized in that: the Tile attribute interpolation request arbitration unit has the capability of synchronizing and sequencing different triangle primitives Tile. If the triangle boundaries Tile being processed in the boundary Tile processing unit all belong to the same triangle, then if the Tile scanning unit outputs a complete inside Tile, the Tile scanning output unit sends an attribute interpolation request to the Tile attribute interpolation request arbitration unit to be responded; if the triangle boundary tiles being processed in the boundary Tile processing unit all belong to more than one triangle, at this time, if the Tile scanning unit outputs a complete inner Tile, the Tile scanning output unit sends an attribute interpolation request to the Tile attribute interpolation request arbitration unit, and the attribute interpolation request cannot be responded.
The technical solution of the present invention is explained in detail by a specific example. As shown in FIG. 1, after receiving the attribute data of three vertices of the triangle primitive, the rasterizing unit starts to perform two parallel operations. The first is to calculate parameters used in the scanning and attribute interpolation process, including triangle boundary function parameters, boundary 8 × 8 pixel Tile processing unit and 4 × 4 pixel Tile attribute interpolation unit parameters, triangle directed area, and attribute component difference values (depth, texture coordinates, color, fog factor) of triangle vertex. According to different implementation performances, the parameter establishing unit can be organized into pipelines with different depths; and secondly, sequencing the position relation of the three vertexes of the triangle in the Y-axis direction, determining the vertex positioned at the lowest part of the Y-axis, calculating the coordinate of the scanning start 8 multiplied by 8 pixels Tile according to the coordinate of the vertex at the lowest part, and simultaneously judging whether the current triangle belongs to the same 8 multiplied by 8 pixels Tile.
On the basis, whether the area of the triangle is 0 and whether the triangle belongs to the same 8 × 8 pixel Tile is sequentially judged. If the area is 0, directly carrying out rasterization of the next triangle; if the pixels belong to the same 8 × 8 pixel Tile, 8 × 8 pixel Tile scanning is omitted, and the pixels are directly sent to a boundary pixel Tile unit for processing.
The scan conversion stage includes an 8 x 8 pixel Tile scan and processing of a boundary 8 x 8 pixel Tile. When 8 × 8 pixel Tile is scanned, for a triangle with an area different from 0, 8 × 8 pixel Tile is scanned in sequence from the initial 8 × 8 pixel Tile according to a ZigZag algorithm scanning path, the position relationship between 4 vertexes of a segment block and the triangle is tested based on a boundary function method, and the position relationship between the segment block and the triangle is quickly determined to determine the position relationship between the current 8 × 8 pixel Tile and three side functions of the triangle, which is bound to one of the following three cases: completely outside, partially inside, and completely inside the triangle. For 8 × 8 pixels Tile that are completely outside the triangle, discard directly; directly sending 8 multiplied by 8 pixels Tile completely in the triangle to an attribute interpolation unit for processing; sending the boundary 8 × 8 pixel Tile partially in the triangle to a boundary 8 × 8 pixel Tile processing unit, and then continuing to scan the next 8 × 8 pixel Tile;
the boundary 8 x 8 pixel Tile processing stage receives 8 x 8 pixel tiles from the 8 x 8 pixel Tile scanning stage, the input and output of the module are in 8 x 8 pixel tiles, and the internal processing is in 4 x 4 pixel tiles, balancing performance and hardware complexity. All the 8 multiplied by 8 pixels Tile in the triangle are directly sent to attribute interpolation logic for attribute interpolation through attribute interpolation request arbitration logic without being processed by the module; for the boundary 8 x 8 pixel Tile, the unit accurately judges the position relation between each segment and the triangle, and performs primitive boundary anti-aliasing processing;
the 8 x 8 pixel Tile attribute interpolation stage receives a request from the boundary 8 x 8 pixel Tile processing unit, including 8 x 8 pixel Tile data from the 8 x 8 pixel Tile channel and the boundary 8 x 8 pixel Tile channel, which are entirely within the triangle. And according to the drawing sequence of the graphic elements, performing parallel segment attribute interpolation calculation at the Tile level, and after finishing the calculation of the 8 × 8 pixel Tile attribute, calculating the Zmax and Zmin values of the 8 × 8 pixel Tile so as to perform Early-Z processing. Meanwhile, a perspective correction algorithm based on texture local linear interpolation is adopted, so that the perspective correction effect can be ensured, and the calculated amount is greatly reduced.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (1)
1. A non-blocking parallel triangular rasterization unit structure characterized by: the structure comprises 7 functional pipeline stages, wherein the 7 functional pipeline stages are a triangle vertex receiving unit, a triangle scanning parameter establishing unit, an edge function method Tile scanning unit, a boundary Tile pixel position relation judging unit, a boundary Tile pixel anti-aliasing unit, a Tile attribute interpolation request arbitration unit and a Tile attribute interpolation unit in sequence from front to back, and are connected in sequence from front to back, and the data output of the previous pipeline stage is used as the data input of the next pipeline stage;
the triangle vertex receiving unit receives a vertex attribute transmission command sent from the exterior of the rasterization unit, extracts vertex attribute data in the command, stores the vertex attribute data in a vertex attribute data buffer in the triangle vertex receiving unit, and then sends the vertex attribute data to the triangle scanning parameter establishing unit under the condition that the vertex attribute data buffer is not empty;
the triangle scanning parameter establishing unit receives the output data of the triangle vertex receiving unit, calculates all parameters used in the scanning and attribute interpolation process of the triangle in a pipelining manner, and sends the calculation result to the edge function method Tile scanning unit;
the edge function method Tile scanning unit receives the triangle primitive parameters sent by the triangle scanning parameter establishing unit, scans and calculates a triangle based on a pixel Tile by adopting an edge function discrimination algorithm in a pipelining mode, and obtains all pixels Tile covered by the triangle primitive according to the calculated position relationship between the vertex of the four corners of the pixel Tile and the triangle; further dividing the pixels Tile covered by the triangle into two types of pixels Tile which are completely in the triangle and pixels Tile which are partially in the triangle; wherein, the pixels Tile completely in the triangle directly send attribute interpolation requests to the Tile attribute interpolation request arbitration unit, and after being responded, the pixel Tile attribute data completely in the triangle are sent to the Tile attribute interpolation unit for attribute interpolation calculation of all pixels contained in the Tile; part of the pixels Tile in the triangle are sent to the boundary Tile pixel position relation determining unit for processing;
the boundary Tile pixel position relation judging unit receives partial pixel Tile data in a triangle from a side function Tile scanning unit, calculates the position relation between each pixel in the received pixel Tile and three sides of the triangle by using the recursion parameters calculated by the triangle scanning parameter establishing unit in a pipelining manner, and marks whether each pixel is in the triangle; according to whether a primitive anti-aliasing function is started or not, a processing result is sent to a boundary Tile pixel anti-aliasing unit or a Tile attribute interpolation request arbitration unit;
the boundary Tile pixel anti-aliasing unit judges the position relation between the received boundary Tile data and a triangle at a sub-pixel level under the condition of starting a primitive anti-aliasing function; according to the pixel Tile address, the boundary Tile pixel anti-aliasing unit can simply calculate the coordinate address of each pixel, and then according to the pixel coordinate address and the corresponding relation between the anti-aliasing grade and the sub-pixel address offset, the coordinate addresses of all sub-pixels in one pixel can be calculated; then finishing the position relation judgment of the sub-pixels and the triangle according to the coordinate addresses of all the sub-pixels; finally, according to the position relation between the sub-pixel contained in each pixel in the boundary pixel Tile and the triangle, determining the Alpha value weight of each pixel, and sending the result to a Tile attribute interpolation request arbitration unit;
the Tile attribute interpolation request arbitration unit simultaneously receives all pixels Tile in a triangle from an edge function method Tile scanning unit and processed pixels Tile in the triangle from a boundary Tile pixel anti-aliasing unit, selects one path of pixels Tile after arbitration and sends the pixels Tile to an attribute interpolation unit for attribute interpolation calculation; the arbitration strategy is that the pixels Tile partially in the triangle take precedence; another function of the Tile attribute interpolation request arbitration unit is rasterization sorting of triangle primitives, which identifies the condition that the rendering sequence of the triangle primitives is error, and ensures that the Tile attribute interpolation unit performs attribute interpolation on pixels Tile covered by the triangle primitives according to the sequence of the triangle primitives entering the rasterization unit;
the Tile attribute interpolation unit receives pixel Tile data from the Tile attribute interpolation request arbitration unit, performs pixel-by-pixel attribute interpolation calculation on the received pixel Tile in a pipeline mode based on a multi-path parallel attribute interpolation circuit, and the control circuit performs attribute interpolation according to the actual attribute quantity carried by each pixel and also needs perspective correction during attribute interpolation in a perspective scene.
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| CN109584334B (en) * | 2018-11-14 | 2023-04-07 | 西安翔腾微电子科技有限公司 | Triangular rasterization scanning structure and rasterization scanning method based on UML |
| CN109658324B (en) * | 2018-11-14 | 2023-04-07 | 西安翔腾微电子科技有限公司 | Triangular raster scanning method |
| CN109346028B (en) * | 2018-11-14 | 2021-03-23 | 西安翔腾微电子科技有限公司 | TLM-based triangular raster scanning structure |
| CN109598669B (en) * | 2018-11-14 | 2023-04-07 | 西安翔腾微电子科技有限公司 | GPU-oriented triangular rasterization scanning system |
| CN109636751B (en) * | 2018-12-07 | 2020-11-27 | 厦门天马微电子有限公司 | Edge processing method of special-shaped display panel, display panel and display device |
| CN109741433B (en) * | 2019-01-08 | 2023-05-05 | 西安邮电大学 | Triangle multidirectional parallel scanning method and structure based on Tile |
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