CN107992635B - FPGA (field programmable Gate array) boxing method and device - Google Patents
FPGA (field programmable Gate array) boxing method and device Download PDFInfo
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Abstract
Provided are a packing method and equipment of an FPGA. The method comprises the following steps: when receiving a netlist file, modifying the netlist file according to a design rule of a physical unit; according to a first packing rule, packing each logic unit in the modified netlist file to obtain a plurality of physical units; the following operations are repeatedly performed until a group satisfying a preset condition is obtained as a final physical unit: analyzing whether the circuits formed by all the current groups meet all preset constraint conditions or not, and combining all the constraint conditions which are not met by the circuits formed by all the current groups to carry out merging operation on the current groups, wherein the constraint conditions comprise more than two. By applying the method, the boxing process of the FPGA can be optimized, and a better boxing result is obtained.
Description
Technical Field
The invention relates to the technical field of FPGA, in particular to a boxing method and equipment of FPGA.
Background
A Field-Programmable Gate Array (FPGA) is developed based on Programmable devices such as Programmable Logic Array (PAL) and general Logic Array (GAL). The FPGA is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the gate circuit quantity of the original programmable device is limited.
In the design process of the FPGA, the following steps are generally included in sequence: logic synthesis, boxing, physical design and the like. The logic synthesis is to compile, optimize, convert and synthesize a software text for describing functions implemented by the FPGA according to a given hardware structure to obtain a netlist file including a plurality of logic units. So-called binning, which is to pack each logic cell in the netlist file into a physical cell (PB) according to the design rule of the physical cell and various constraints. In the physical design, layout and wiring are performed based on each physical cell obtained after binning to obtain a final FPGA.
Therefore, the boxing is an important step in FPGA design, and the quality of the boxing result has great influence on the quality of subsequent physical design.
However, when each logic unit in the netlist file is boxed by using the existing boxing method, the finally obtained PB usually only meets one or some constraint conditions of all the constraint conditions, and the boxing result is poor.
Disclosure of Invention
The invention solves the technical problem of how to optimize the boxing process of the FPGA so as to obtain a better boxing result.
In order to solve the technical problem, an embodiment of the present invention provides a method for boxing an FPGA, where the method includes: when receiving a netlist file, modifying the netlist file according to a design rule of a physical unit; according to a first packing rule, packing each logic unit in the modified netlist file to obtain a plurality of physical units; taking each physical unit as a group, and repeatedly executing the following operations until a group satisfying preset conditions is obtained as a final physical unit: analyzing whether the circuits formed by all the current groups meet all preset constraint conditions or not, and combining all the constraint conditions which are not met by the circuits formed by all the current groups to carry out merging operation on the current groups, wherein the constraint conditions comprise more than two.
Optionally, the boxing each logic unit in the modified netlist file according to the first boxing rule includes: respectively installing the sets of the logic units with fixed connection relations in the modified netlist file into different physical units; and respectively installing each logic unit which does not have a fixed connection relation in the modified netlist file into different physical units.
Optionally, the merging operation performed on the current group in combination with each constraint condition that is not satisfied by the circuit composed of all the current groups includes: when the circuits formed by all the current groups do not meet all the preset constraint conditions, searching whether improvable constraint conditions exist in the constraint conditions which are not met by the circuits formed by all the current groups; selecting the constraint condition with the highest priority from all the searched improvable constraint conditions; and combining all current groups according to the selected constraint condition with the highest priority and the improvement degree of other conditions in all searched improved constraint conditions.
Optionally, analyzing the circuit composed of the current group according to the selected constraint condition with the highest priority, and determining a target group suitable for merging; and in all the multiple pairs of target groups suitable for merging, merging operation is carried out on the pair of target groups with the maximum other condition improvement in all the found improvable constraints.
Optionally, after obtaining the group satisfying the preset condition, obtaining the final physical unit by: and adjusting the groups where the logic units in the groups are located after the merging operation by using the constraint conditions, and taking the groups obtained after the adjustment as the final physical units.
The embodiment of the invention also provides a boxing device of the FPGA, which comprises: the modification unit is suitable for modifying the netlist file according to the design rule of the physical unit when the netlist file is received; the first packing unit is suitable for packing each logic unit in the modified netlist file according to a first packing rule to obtain a plurality of physical units; a second packing unit adapted to repeatedly perform the following operations with each physical unit as a group until a group satisfying a preset condition is obtained as a final physical unit: analyzing whether the circuits formed by all the current groups meet all preset constraint conditions or not, combining the constraint conditions to meet all the constraint conditions which are not met by the circuits formed by all the current groups, and merging the current groups, wherein the constraint conditions comprise more than two.
Optionally, the first packing unit comprises: the first packing sub-unit is suitable for respectively packing the set of the logic units with fixed connection relation in the modified netlist file into different physical units; and the second packing sub-units are suitable for respectively packing the logic units which do not have the fixed connection relation in the modified netlist file into different physical units.
Optionally, the second packing unit comprises: the searching subunit is suitable for searching whether improvable constraint conditions exist in the constraint conditions which are not met by the circuits formed by all the current groups when the circuits formed by all the current groups do not meet all the preset constraint conditions; the selecting subunit is suitable for selecting the constraint condition with the highest priority from all the searched improved constraint conditions; and the merging subunit is suitable for merging all current groups according to the selected constraint condition with the highest priority and by combining the improvement degrees of other conditions in all searched improved constraint conditions.
Optionally, the merging subunit is adapted to analyze a circuit composed of the current group according to the selected constraint condition with the highest priority, determine a target group suitable for merging, and perform a merging operation on one target group with the highest improvement degree of other conditions among all the found improvable constraint conditions, among all the multiple pairs of target groups suitable for merging.
Optionally, the apparatus further comprises: and the adjusting unit is suitable for adjusting the groups where the logic units in the groups after the merging operation are located by using the constraint conditions after the groups meeting the preset conditions are obtained, and taking each group obtained after the adjustment as the final physical unit.
Compared with the prior art, the embodiment of the invention has the advantages that:
by adopting the scheme, after each logic unit in the modified netlist file is boxed to obtain a plurality of physical units, each physical unit is used as one group, and when the current group is combined, various constraint conditions which are not met by a circuit formed by all the current groups are combined, so that various constraint conditions can be considered, and a boxing result is better.
And respectively loading the set of the logic units with the fixed connection relation and the logic units without the fixed connection relation in the modified netlist file into different physical units, so that the number of the physical units can be reduced before the combination operation is executed by using a packing algorithm, and the final number of the physical units can be reduced to optimize the area of the FPGA chip.
After the merging operation is performed on each group, the group where the logical unit in each group after the merging operation is located is adjusted by using the constraint condition, and each group obtained after the adjustment is used as the final physical unit, so that a better boxing result can be obtained.
Drawings
FIG. 1 is a schematic diagram of a physical unit in the prior art;
FIG. 2 is a flow chart of a packing method of an FPGA according to an embodiment of the present invention;
FIG. 3 is a flow chart of another method for binning FPGAs in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of a packing process of an FPGA in an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a packaging device of an FPGA in the embodiment of the present invention.
Detailed Description
Currently, each logic unit in the netlist file is boxed, and a boxing algorithm for one or several constraint conditions is usually adopted to perform a boxing operation. Specifically, by using the binning algorithm, a certain logical unit is selected as a seed to generate a physical unit, then the attraction factors of other logical units are calculated according to the constraint conditions targeted by the algorithm, and the logical unit with the largest attraction factor is absorbed into the generated physical unit. The above process is then repeated until the physical unit cannot absorb other logical units. Then, a new physical unit is generated by selecting the next seed, and the new physical unit is filled according to the steps until all the logic units are loaded into different physical units.
As the circuit design scale is larger and larger, the timing constraint of the user is more and more complicated, and the structure of the physical unit itself of the FPGA is more and more complicated, for example, referring to fig. 1, a part of the physical unit can be loaded with 4 look-up tables LUT, 8 registers FF and a 4-bit adder 10. Therefore, it is difficult to design a binning algorithm that can satisfy all the constraints while satisfying the design rules of the physical units, and therefore the binning result is often poor.
In view of the above problems, embodiments of the present invention provide a method for boxing an FPGA, where after boxing each logic unit in a modified netlist file to obtain a plurality of physical units, each physical unit can be used as a group, and a current group is merged according to each constraint condition that a circuit formed by all the groups does not satisfy, so that multiple constraint conditions can be considered, and a boxing result is better.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, an embodiment of the present invention provides a method for boxing an FPGA, where the method may include the following steps:
and 21, when the netlist file is received, modifying the netlist file according to the design rule of the physical unit.
In a particular implementation, upon receiving the netlist file, the netlist file is modified to conform to the design rules of the physical unit.
For example, in the design rule of a physical unit, both inputs of the multiplexer MUX must be look-up tables. Thus, if a first terminal of multiplexer MUX1 is connected to lookup table LUT1 and a second terminal is connected to register FF1 in the netlist file, a lookup table LUT2 needs to be inserted between the second terminal of multiplexer MUX1 and register FF1 so that both input terminals of multiplexer MUX1 are connected to the lookup table.
And step 22, according to the first packing rule, packing each logic unit in the modified netlist file to obtain a plurality of physical units.
In a specific implementation, the first boxing rule may be set by a person skilled in the art according to practical situations, and is not particularly limited as long as a plurality of physical units are available. The first packing rule may specifically include only one rule, or may include a plurality of rules.
In an embodiment of the present invention, each logic unit in the modified netlist file may be boxed according to the following first boxing rule:
firstly, selecting logic units with fixed connection relation from the modified netlist file to be used as a set, and respectively installing each set into different physical units.
For example, in a circuit design, an adder may include a plurality of units, each of which may include: a look-up table, a multiplexer and an exclusive or gate, wherein the look-up table, the multiplexer and the exclusive or gate comprised by a unit can be loaded into a physical unit according to the first packing rule.
For another example, when a multiplexer cannot be implemented by using a look-up table, the multiplexer can be implemented by using the look-up table and the multi-layer multiplexer MUX, and the connection relationship of the implementation is fixed, and then the look-up table and the multiplexer MUX included in the multiplexer are loaded into a physical unit according to the first packing rule.
Secondly, the remaining logic units without fixed connection relation in the modified netlist file are respectively installed in different physical units, for example, each lookup table without fixed connection relation or each register is individually installed in one physical unit.
And step 23, regarding each physical unit as a group, and analyzing whether the circuit formed by all the current groups meets all preset constraint conditions.
In a specific implementation, the constraint condition may include a plurality of conditions such as timing, area, power consumption and a traffic distribution rate. In the embodiment of the present invention, the number of the constraint conditions is two or more, and it should be understood that the number of the constraint conditions is not limited to the specific number.
And when the circuits formed by all the groups meet all the constraint conditions, ending the whole boxing process, otherwise, continuing to execute the step 24.
And 24, combining the current groups according to each constraint condition which is not met by the circuits formed by all the current groups.
In order to make the current circuit satisfy the corresponding constraint condition, the corresponding merging operation can be executed on the current group according to different constraint conditions, and other unsatisfied constraint conditions are considered at the same time. For example, when the constraint condition is a timing condition, two groups between two adjacent nodes on the critical path may be merged to reduce the delay of the critical path. When the constraint condition is a routing rate condition, two groups with common external connection can be merged, thereby reducing the routing difficulty of the router. When the constraint condition is an area condition, two groups which have little influence on the overall packing quality can be combined to reduce the packed area. Regardless of the constraint conditions under which the merge operation is performed, after each merge operation, the group obtained after the merge operation may be selected to be retained or cancelled according to the degree of improvement of the circuit composed of the groups obtained after the merge operation in other unsatisfied constraint conditions.
And 25, judging whether the group obtained after the merging operation meets a preset condition.
In a specific implementation, when the circuits composed of the current groups satisfy all the constraint conditions, a merging operation may be performed on the current groups, so that the circuits composed of the groups obtained after merging satisfy preset conditions. The preset condition may be set by a person skilled in the art according to an actual situation, for example, the preset condition may be that the current circuit is within a constraint threshold interval corresponding to part or all of the constraint conditions, or that the number of times of repeatedly performing steps 23 and 24 reaches a preset number of times.
And when the group after the merging operation meets the preset condition, taking the group after the merging operation as a final physical unit, and ending the whole boxing process, otherwise, repeatedly executing the step 23 until the group meeting the preset condition is obtained.
FIG. 3 is a flowchart of another set of FPGAs packing method according to an embodiment of the present invention. Referring to fig. 3, the method may include the steps of:
and step 31, when the netlist file is received, modifying the netlist file according to the design rule of the physical unit.
And step 32, according to the first packing rule, packing each logic unit in the modified netlist file to obtain a plurality of physical units.
For the steps 31 and 32, reference may be made to the above description of the steps 21 and 22, and details are not repeated here.
And step 33, analyzing whether the circuits formed by all the current groups meet all preset constraint conditions.
And when the circuits formed by all the groups meet all the preset constraint conditions, ending the whole boxing process, otherwise, executing the step 34.
For example, when the circuits formed by all the groups do not satisfy the timing condition, the critical paths of the circuits formed by all the groups can be analyzed, and whether the timing of the circuit obtained after combination can be improved after any two combinations on the critical paths are combined can be judged.
If there is an improvable constraint in the constraints that are not satisfied by the circuits composed of all the groups, step 35 is executed, otherwise, the whole boxing process is ended.
And step 35, selecting the constraint condition with the highest priority from all the searched improvable constraint conditions.
In specific implementation, the restriction conditions may be ranked in advance, for example, the restriction conditions may be ranked according to importance of the restriction conditions, or may be ranked according to a request of a user, and the ranking is not limited specifically, so that the restriction condition with the highest priority may be selected from all found improvable restriction conditions.
And step 36, combining all current groups according to the selected constraint condition with the highest priority and the improvement degree of other conditions in all found improvable constraint conditions.
In a specific implementation, the circuit composed of the current group may be analyzed according to the selected constraint condition with the highest priority, a target group suitable for merging is determined, and then, in all pairs of target groups suitable for merging, a pair of target groups with the highest improvement degree of other conditions among all the found improvable constraint conditions is merged.
And step 37, judging whether the combined group meets a preset condition.
And when the combined group meets the preset condition, ending the whole boxing process, otherwise, continuing to execute the step 33.
Referring to fig. 4, the partial group obtained at step 32 includes: the above-mentioned packing process will be described in detail by taking G0, G1, G2, G3, G4 and G5 as examples:
firstly, the circuits composed of G0, G1, G2, G3, G4 and G5 are analyzed to judge whether the current circuit meets all the constraint conditions. All the constraint conditions are sorted in the order of importance from strong to weak as follows: timing conditions, cloth-through rate conditions, and area conditions.
When the current circuit does not meet the time sequence condition and the call-through rate condition, the circuit formed by the current group is analyzed according to the time sequence condition, and a target group suitable for combination is determined. Specifically, the critical path of the circuit composed by the current group, such as path G0 → G1 → G2 → G3 → G4, may be analyzed to obtain four pairs of target groups (G0, G1), (G1, G2), (G2, G3) and (G3, G4) suitable for merging.
The four pairs of target groups (G0, G1), (G1, G2), (G2, G3) and (G3, G4) obtained were analyzed to determine a pair of target groups that improved the maximum in the layout rate of the combined circuit. For example, if the maximum improvement in the pass rate of the circuit is achieved after merging the target groups G0 and G1, then a merge operation is performed on G0 and G1 to obtain group G01 (not shown).
And judging whether the circuit composed of the groups G01, G2, G3, G4 and G5 meets all constraint conditions or not, and when the current circuit does not meet the time sequence conditions and the circulation rate conditions, repeatedly executing the operations until the group meeting the preset conditions is obtained as a final physical unit.
When the boxing method in the embodiment of the invention is used for boxing, the number of the constraint conditions is not limited, so that users can put forward different constraint conditions more conveniently, and the expandability is better.
In an embodiment of the present invention, after the merging operation is performed on each group, the following operations are adopted to obtain the final physical unit: and adjusting the groups where the logic units in the groups are located after the merging operation by using the constraint conditions, and taking the groups obtained after the adjustment as the final physical units.
For example, after obtaining the group satisfying the preset condition, the delay and the clearing rate of the circuit in which the group satisfying the preset condition is located are both within the corresponding constraint threshold interval, but the delay is relatively large, and therefore, the positions of the logic units in one group can be adjusted to reduce the delay of the current circuit, which may increase the clearing rate and the area, but only if the adjusted clearing rate and the area are still within the corresponding constraint threshold interval. The method can be determined according to the requirements of users.
As can be seen from the above, with the adoption of the packing method of the FPGA in the embodiment of the present invention, since the finally obtained physical unit is obtained by processing the packing algorithm corresponding to the plurality of constraint conditions, a plurality of constraint conditions can be considered, and the packing result is better.
In order to make those skilled in the art better understand and implement the present invention, the following describes the apparatus corresponding to the above-mentioned packing method of FPGA in detail.
Referring to fig. 5, an embodiment of the present invention provides a box loading apparatus 50 for an FPGA, where the apparatus 50 may include: a modification unit 51, a first packing unit 52, and a second packing unit 53. Wherein:
the modifying unit 51 is adapted to modify the netlist file according to the design rule of the physical unit when the netlist file is received;
the first packing unit 52 is adapted to pack each logic unit in the modified netlist file according to a first packing rule to obtain a plurality of physical units;
the second packing unit 53 is adapted to use each physical unit as a group, and sequentially perform a combination operation on each group by using a packing algorithm corresponding to a constraint condition of a preset level, so as to obtain a final physical unit, where the constraint condition includes more than two.
In an embodiment of the present invention, the first packing unit 52 may include: a first packing subunit 521 and a second packing subunit 522. Wherein:
the first packing subunit 521 is adapted to separately pack the sets of logic units with fixed connection relationships in the modified netlist file into different physical units;
the second packing subunit 522 is adapted to separately pack each logic unit that does not have a fixed connection relationship in the modified netlist file into a different physical unit.
In a specific implementation, the second packing unit 53 includes: find subunit 531, select subunit 532, and merge subunit 533. Wherein:
the searching subunit 531 is adapted to search whether there is an improvable constraint condition from the constraint conditions that are not satisfied by the circuits that are currently composed of all the groups when the circuits that are currently composed of all the groups do not satisfy all the preset constraint conditions;
the selecting subunit 532 is adapted to select a constraint condition with the highest priority from all the found improvable constraint conditions;
the merging subunit 533 is adapted to merge all current groups according to the selected constraint condition with the highest priority and by combining the improvement degrees of other conditions in all found improvable constraint conditions.
In a specific implementation, the merging subunit 533 is adapted to analyze the circuit formed by the current group according to the selected constraint condition with the highest priority, determine a target group suitable for merging, and perform a merging operation on one target group with the greatest improvement degree of other conditions among all the found pairs of target groups suitable for merging.
In an embodiment of the present invention, the boxing apparatus 50 may further include: an adjusting unit 54. The adjusting unit 54 is adapted to, after the merging operation is performed on each group, adjust the group where the logical unit in each group after the merging operation is located by using the constraint condition, and use each group obtained after the adjustment as the final physical unit.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, and the like.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A packing method of an FPGA is characterized by comprising the following steps:
when receiving a netlist file, modifying the netlist file according to a design rule of a physical unit so as to accord with the design rule of the physical unit;
according to a first packing rule, packing each logic unit in the modified netlist file to obtain a plurality of physical units;
taking each physical unit as a group, and repeatedly executing the following operations until a group satisfying preset conditions is obtained as a final physical unit: analyzing whether the circuits formed by all the current groups meet all preset constraint conditions or not, and combining all the constraint conditions which are not met by the circuits formed by all the current groups to carry out merging operation on the current groups, wherein the constraint conditions comprise more than two;
according to the first packing rule, each logic unit in the modified netlist file is packed, and the method comprises the following steps: respectively installing the sets of the logic units with fixed connection relations in the modified netlist file into different physical units; and respectively installing each logic unit which does not have a fixed connection relation in the modified netlist file into different physical units.
2. The method of claim 1, wherein said combining the current set of circuits in combination with each constraint not satisfied by the current set of circuits comprises:
when the circuits formed by all the current groups do not meet all the preset constraint conditions, searching whether improvable constraint conditions exist in the constraint conditions which are not met by the circuits formed by all the current groups;
selecting the constraint condition with the highest priority from all the searched improvable constraint conditions;
and combining all current groups according to the selected constraint condition with the highest priority and the improvement degree of other conditions in all searched improved constraint conditions.
3. The method for boxing of FPGA of claim 2, wherein said merging all current groups according to the constraint condition with the highest priority selected in combination with the improvement degree of other conditions in all found improvable constraint conditions comprises:
analyzing the circuit formed by the current group according to the selected constraint condition with the highest priority, and determining a target group suitable for merging;
and in all the multiple pairs of target groups suitable for merging, merging operation is carried out on the pair of target groups with the maximum other condition improvement in all the found improvable constraints.
4. The method of encasement by FPGA of claim 1, wherein after obtaining the set of satisfying preset conditions, the final physical unit is obtained by:
and adjusting the groups where the logic units in the groups are located after the merging operation by using the constraint conditions, and taking the groups obtained after the adjustment as the final physical units.
5. The FPGA boxing apparatus is characterized by comprising:
the modification unit is suitable for modifying the netlist file according to the design rule of the physical unit so as to accord with the design rule of the physical unit when the netlist file is received;
the first packing unit is suitable for packing each logic unit in the modified netlist file according to a first packing rule to obtain a plurality of physical units;
a second packing unit adapted to repeatedly perform the following operations with each physical unit as a group until a group satisfying a preset condition is obtained as a final physical unit: analyzing whether the circuits formed by all the current groups meet all preset constraint conditions or not, combining the circuits to meet all the constraint conditions which are not met by the circuits formed by all the current groups, and merging the current groups, wherein the constraint conditions comprise more than two;
the first packing unit includes:
the first packing sub-unit is suitable for respectively packing the set of the logic units with fixed connection relation in the modified netlist file into different physical units;
and the second packing sub-units are suitable for respectively packing the logic units which do not have the fixed connection relation in the modified netlist file into different physical units.
6. The FPGA encasement apparatus of claim 5, wherein said second encasement unit comprises:
the searching subunit is suitable for searching whether improvable constraint conditions exist in the constraint conditions which are not met by the circuits formed by all the current groups when the circuits formed by all the current groups do not meet all the preset constraint conditions;
the selecting subunit is suitable for selecting the constraint condition with the highest priority from all the searched improved constraint conditions;
and the merging subunit is suitable for merging all current groups according to the selected constraint condition with the highest priority and by combining the improvement degrees of other conditions in all searched improved constraint conditions.
7. The apparatus for binning an FPGA of claim 6, wherein the merging subunit is adapted to analyze the circuit formed by the current group according to the selected constraint condition with the highest priority, determine the target groups suitable for merging, and perform merging on the pair of target groups with the greatest improvement in other conditions among all the found feasible improved constraint conditions, among all the pairs of target groups suitable for merging.
8. The apparatus for encasement by FPGA of claim 6, further comprising:
and the adjusting unit is suitable for adjusting the groups where the logic units in the groups after the merging operation are located by using the constraint conditions after the groups meeting the preset conditions are obtained, and taking each group obtained after the adjustment as the final physical unit.
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