CN107968094A - A kind of ledge structure forming technology for 3D nand flash memories - Google Patents
A kind of ledge structure forming technology for 3D nand flash memories Download PDFInfo
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- CN107968094A CN107968094A CN201711166879.7A CN201711166879A CN107968094A CN 107968094 A CN107968094 A CN 107968094A CN 201711166879 A CN201711166879 A CN 201711166879A CN 107968094 A CN107968094 A CN 107968094A
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- mask layer
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of ledge structure forming technology for 3D nand flash memories, the technique includes the following steps：Deposit to form the first mask layer in substrate stacked structure, mask pattern is formed by photoetching process；Etching forms the 1st grade of step straight down, and deposition forms the second mask layer, and second mask layer includes being formed at the side wall mask on the outside of the 1st grade of step；The second mask layer is etched straight down, until expose the remaining stack layer upper surface, and the thickness of the side wall mask is equal to the width of every grade of step surface of design；Etching forms the 2nd grade of step straight down, and repeated deposition forms the second mask layer, etches the second mask layer straight down and etches the step of forming the 2nd grade of step straight down, forms the 3rd to N grades steps.More ledge structures can be formed in the method for the present invention under the conditions of one of photoetching process, the lithographic process steps in 3D NAND manufactures is advantageously reduced, reduces process costs.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of shaping of 3D nand flash memories core space ledge structure
Technique.
Background technology
In order to improve the density of memory device, industry is directed to the memory cell that research and development reduce two-dimensional arrangement extensively
Size method.With the memory cell dimensions continual reductions of two-dimentional (2D) memory device, signal conflict and interference can be shown
Increase is write, so that being difficult to carry out multi-level-cell (MLC) operation.In order to overcome the limitation of 2D memory devices, there is three-dimensional
The research that memory device this year of (3D) structure comes gradually heats up, by by memory cell be three-dimensionally disposed in substrate come
Improve integration density.
3D nand memories are a kind of three-dimensional stacked flush memory devices of storage unit, predominantly set water outside vertical-channel
Flat laminated metal grid layer.Metal gate layer stacked horizontally is in hierarchic structure in the prior art, can make each layer of metal gate with this
A vertical metal line can be individually connected on step surface, is finally connected with wordline (Word line), to realize each layer of metal
Grid layer corresponds to the addressing operation of storage unit.
Disclosed document (H.Tanaka et al., Bit cost scalable technology with punch
and plug process for ultra high density flash memory,in VLSI Symposium
Technical Digest (2007)) in ladder Structure formation method be：With reference to shown in figure 1a-e：
S1：With reference to figure 1a, etch mask is formed in passing through one of photoetching process (passing through photoresist mask 2) on stack layer 1
Pattern；
S2：With reference to figure 1b, level-one ledge structure is etched straight down；
S3：With reference to figure 1c, 2 size of finishing photoresist mask, exposes one fixed width and stacks layer surface；
S4：With reference to figure 1d, continue etching downwards, form two-stage step structure；
S5：With reference to figure 1e, repeat step S3 and S4, ultimately form multi-stage stairs structure 3.
However, when above-mentioned technique there are following defects, repairs mask dimensions and exposes one fixed width and stack layer surface each time,
The thickness of mask is also trimmed reduction at the same time, when mask is depleted, need to carry out down one of photoetching process and re-form certain thickness
The mask pattern of degree, can just continue etching technics and form new ledge structure；When needing number of steps to be formed to increase, phase
In requisition for increase photoetching process road number, and process costs are caused to increase；And direct photoetching process formation has adequate thickness
Mask pattern usually there is very big technical difficulty.
The content of the invention
For drawbacks described above of the prior art, it is an object of the invention to provide a kind of platform for 3D nand flash memories
Stage structure forming technology, the technique can form more step series by using one of photoetching process, therefore, be conducive to
The lithographic process steps in 3D NAND manufactures are reduced, reduce process costs.
To achieve these goals, the technical solution adopted by the present invention is as follows：
A kind of ledge structure forming technology for 3D nand flash memories, the technique include the following steps：
One substrate stacked structure is provided；
Deposition forms the first mask layer, and mask pattern is formed by photoetching process；
Etching forms the 1st grade of step straight down,
Deposition forms the second mask layer, and second mask layer includes three parts, Part I above the first mask layer,
Remaining stack layer upper surface of the Part II after the 1st grade of step is etched away, Part III are connection Part I and second
Divide and be formed at the side wall mask on the outside of the 1st grade of step；
The second mask layer is etched straight down, until expose the remaining stack layer upper surface, and the side wall mask
Thickness is equal to the width of every grade of step surface of design；
Etching forms the 2nd grade of step straight down,
Repeated deposition forms the second mask layer, etches the second mask layer straight down and etches the 2nd grade of formation straight down
The step of step, form the 3rd to N grades steps.
Further, the material of first mask layer is agraphitic carbon.
Further, the material of second mask layer is agraphitic carbon.
Further, the material of second mask layer is silica.
Further, the substrate stacked structure is the stacks of thin films knot that silica and silicon nitride are staggeredly stacked on substrate
Structure.
Further, the step includes one layer of silicon oxide layer and adjacent silicon nitride layer per level-one.
Compared with prior art, the beneficial effects are mainly as follows：
The present invention proposes a kind of forming method of hierarchic structure in 3D nand memories, subtracts compared to the finishing of existing mask
Process that is thin, shortening cooperation etching, our rule form new mask using thin film deposition, make former mask dimensions increase,
So as to change etching position every time, so as to form multi-stage stairs structure.In existing hierarchic structure forming method repair mask and
Mask layer can be thinned when thinned mask layer can be consumed when etching every grade of step, and step is only etched in the method for the present invention, together
More ledge structures can be formed under the conditions of photoetching process, the lithographic process steps in 3D NAND manufactures is advantageously reduced, reduces work
Skill cost.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Attached drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole attached drawing, identical component is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-1e, for the flow chart of ledge structure forming technology in the prior art；
Fig. 2 a-2h, are the flow chart of the ledge structure forming technology of embodiment of the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
A-2h is please referred to Fig.2, in the present embodiment, it is proposed that a kind of ledge structure for 3D nand flash memories shapes work
Skill, the technique include the following steps：
S100, with reference to figure 2a, there is provided a substrate stacked structure；The substrate stacked structure is to aoxidize on the substrate 100
The thin film stack that silicon 200 and silicon nitride 300 are staggeredly stacked
S200, with reference to figure 2b, deposition forms the first mask layer 400, mask pattern is formed by photoetching process；Described first
The material of mask layer is agraphitic carbon
S300, straight down etching form the 1st grade of step 500, the step includes one layer of silicon oxide layer 200 and adjacent
Silicon nitride layer 300；
S400, with reference to figure 2c, deposition forms the second mask layer 600, and the material of second mask layer is silica, described
Second mask layer includes three parts, and for Part I 601 above the first mask layer, Part II 602 is etching away the 1st grade of step
Remaining stack layer upper surface afterwards, Part III are formed on the outside of the 1st grade of step for connection Part I and Part II
Side wall mask 603；
S500, with reference to figure 2d, etches the second mask layer 600 straight down, until expose the remaining stack layer upper surface,
And the side wall cover 603 thickness be equal to design every grade of step surface width；
S600, with reference to figure 2e, the 2nd grade of step 700 of etching formation straight down；
S700, the second mask layer is formed with reference to figure 2f and Fig. 2 g, repeat step S400 to step S600, i.e. repeated deposition
600th, the step of etching the second mask layer 600 and straight down the 2nd grade of step of etching formation straight down forms 3rd level step
800；
S800, is repeated several times step S400 to step S600, until forming N grades of steps 900
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (6)
1. a kind of ledge structure forming technology for 3D nand flash memories, it is characterised in that the technique includes the following steps：
One substrate stacked structure is provided；
Deposition forms the first mask layer, and mask pattern is formed by photoetching process；
Etching forms the 1st grade of step straight down,
Deposition forms the second mask layer, and second mask layer includes three parts, and Part I is above the first mask layer, and second
Remaining stack layer upper surface of the part after the 1st grade of step is etched away, Part III for connection Part I and Part II and
The side wall mask being formed on the outside of the 1st grade of step；
The second mask layer is etched straight down, until expose the remaining stack layer upper surface, and the thickness of the side wall mask
Equal to the width of every grade of step surface of design；
Etching forms the 2nd grade of step straight down,
Repeated deposition forms the second mask layer, etches the second mask layer straight down and etches the 2nd grade of step of formation straight down
The step of, form the 3rd to N grades steps.
2. ledge structure forming technology as claimed in claim 1, it is characterised in that the material of first mask layer is without fixed
Type carbon.
3. ledge structure forming technology as claimed in claim 1, it is characterised in that the material of second mask layer is without fixed
Type carbon.
4. the ledge structure forming technology as described in claim 1-3 any one, it is characterised in that second mask layer
Material is silica.
5. the ledge structure forming technology as described in claim 1-3 any one, it is characterised in that the substrate stacked structure
The thin film stack being staggeredly stacked for silica on substrate and silicon nitride.
6. ledge structure forming technology as claimed in claim 5, it is characterised in that the step includes one layer of oxidation per level-one
Silicon layer and adjacent silicon nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711166879.7A CN107968094A (en) | 2017-11-21 | 2017-11-21 | A kind of ledge structure forming technology for 3D nand flash memories |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711166879.7A CN107968094A (en) | 2017-11-21 | 2017-11-21 | A kind of ledge structure forming technology for 3D nand flash memories |
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| Publication Number | Publication Date |
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| CN107968094A true CN107968094A (en) | 2018-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201711166879.7A Pending CN107968094A (en) | 2017-11-21 | 2017-11-21 | A kind of ledge structure forming technology for 3D nand flash memories |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493192A (en) * | 2018-06-04 | 2018-09-04 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
| CN109411474A (en) * | 2018-11-07 | 2019-03-01 | 长江存储科技有限责任公司 | The forming method of three-dimensional storage step structure |
| CN110707089A (en) * | 2019-09-06 | 2020-01-17 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
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| CN101320224A (en) * | 2007-03-21 | 2008-12-10 | 应用材料公司 | Halogen-free amorphous carbon mask etch having high selectivity to photoresist |
| US20110244666A1 (en) * | 2010-04-05 | 2011-10-06 | Samsung Electronics Co., Ltd. | Methods Of Manufacturing Stair-Type Structures And Methods Of Manufacturing Nonvolatile Memory Devices Using The Same |
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| CN108493192A (en) * | 2018-06-04 | 2018-09-04 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
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Application publication date: 20180427 |