CN107967874B - 像素结构 - Google Patents

像素结构 Download PDF

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CN107967874B
CN107967874B CN201610907122.8A CN201610907122A CN107967874B CN 107967874 B CN107967874 B CN 107967874B CN 201610907122 A CN201610907122 A CN 201610907122A CN 107967874 B CN107967874 B CN 107967874B
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李及元
伊恩法兰契
林胜隆
梁广恒
蔡淑芬
陈家弘
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E Ink Holdings Inc
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Abstract

本发明公开了一种像素结构，包含像素电极、至少一个数据选择线与至少一个隔离线。至少一个隔离线沿像素电极排列。像素电极用以储存像素电压。至少一个数据选择线用以传递至少一个数据信号。至少一个隔离线用以降低至少一个数据信号的电场对像素电极的像素电压的影响。至少一个隔离线的投影区域与像素电极的投影区域重叠。本发明可通过耦接固定电压(例如接地端)的隔离线来降低数据信号的电场对像素电极(尤其是第二电极)的影响。因此，可降低亮度不均(Mura)的现象，有效地提升像素结构的显示质量。

Description

像素结构
技术领域
本发明涉及一种像素技术，且特别涉及一种像素结构。
背景技术
在大型面板中，为了缩减边框的宽度而增加数据选择线的数目，导致像素之间的间距过大。通过桥接方式使像素电极的面积增加以降低像素之间的间距，却也因此导致数据选择线的电场影响像素电极，因此降低像素的显示质量。
发明
本发明的目的是提供一种像素结构，可降低亮度不均(Mura)的现象，有效地提升画素像素结构的显示质量。
根据本发明提供的一种像素结构，其包含像素电极、至少一个数据选择线与至少一个隔离线。至少一个隔离线沿像素电极排列。像素电极用以储存像素电压。至少一个数据选择线用以传递至少一个数据信号。至少一个隔离线用以降低至少一个数据信号的电场对像素电极的像素电压的影响。至少一个隔离线的投影区域与像素电极的投影区域重叠。
在本发明的一实施例中，像素电极包含第一电极与第二电极。第二电极电性耦接第一电极。至少一个隔离线的投影区域与第二电极的投影区域重叠。
的本发明内容的一实施例中，至少一个隔离线与至少一个数据选择线设置于相同层。
在本发明内容的一实施例中，至少一个隔离线设置于像素电极与至少一个数据选择线之间。
在本发明内容的一实施例中，至少一个隔离线与像素电极间隔第一距离。第一距离不大于像素电极与至少一个数据选择线的距离。
在本发明内容的一实施例中，第一距离介于3微米(μm)至7微米的范围。
在本发明内容的一实施例中，至少一个隔离线与至少一个数据选择线间隔第二距离。第二距离小于像素电极与至少一个数据选择线的距离。
在本发明内容的一实施例中，第二距离介于3微米(μm)至7微米的范围。
在本发明内容的一实施例中，至少一个隔离线电性耦接至固定电压。
在本发明内容的一实施例中，至少一个隔离线电性耦接至接地端。
综上所述，本发明可通过耦接固定电压(例如接地端)的隔离线来降低数据信号的电场对像素电极(尤其是第二电极)的影响。因此，可降低亮度不均(Mura)的现象，有效地提升像素结构的显示质量。
以下将以实施方式对上述的说明作详细的描述，并对本发明内容的技术方案提供更进一步的解释。
附图说明
为了让本发明的上述和其它目的、特征、优点与实施例更明显易懂，所附图示之说明如下：
图1是说明本发明一实施例的像素结构的俯视示意图；
图2是说明本发明一实施例的像素结构的截面示意图；以及
图3是说明本发明一实施例的像素结构的截面示意图。
具体实施方式
为了使本发明内容的叙述更加详尽与完备，可参照附图及以下所述的各种实施例。但所提供的实施例并非用以限制本发明所涵盖的范围；步骤的描述也非用以限制其执行的顺序，任何由重新组合，所产生具有均等功效的装置，皆为本发明所涵盖的范围。
在实施方式与权利要求中，除非内文中对于冠词有所特别限定，否则“一”与“该”可泛指单一个或多个。将进一步理解的是，本文中所使用的“包含”、“包括”、“具有”及相似词汇，指明其所记载的特征、区域、整数、步骤、操作、组件与/或组件，但不排除其所述或额外的其一个或多个其它特征、区域、整数、步骤、操作、组件、组件，与/或其中的群组。
关于本文中所使用的“约”、“大约”或“大致约”一般通常是指数值的误差或范围约百分之二十以内，优选地是约百分之十以内，而更佳地则是约百分之五以内。文中若无明确说明，其所提及的数值皆视作为近似值，即如“约”、“大约”或“大致约”所表示的误差或范围。
另外，关于本文中所使用的“耦接”及“连接”，均可指二个或多个组件相互直接作实体接触或电性接触，相互间接作实体接触或电性接触，或是通过无线连接，而“耦接”还可指二个或多个组件相互操作或动作。
请参考图1。图1是说明本发明一实施例的像素结构100的俯视示意图。像素结构100包含像素电极110、至少一个数据选择线120与至少一个隔离线130。隔离线130沿该像素电极110排列，并且隔离线130的投影区域与像素电极110的投影区域重叠。数据选择线120用以传递数据信号以供像素显示。
具体而言，像素电极110包含电极111、112，并且电极112电性耦接电极111。在一实施例中，电极112通过桥接方式电性耦接电极111。在本实施例中，传递数据信号的数据选择线120数目为三个，为了减少像素结构100与邻近像素结构之间的距离，因而设置电极112以增加像素电极110的整体面积。然而，数据选择线120上传递的数据信号所形成的电场可能对电极112造成影响，导致像素显示质量降低(例如产生亮度不均(Mura))。
针对上述问题，隔离线130(例如金属数据选择线)用以降低数据选择线120上数据信号的电场对像素电极110的影响。具体而言，隔离线130可电性耦接至固定电位(例如接地端)，因此可有效地降低像素电极110(尤其是电极112)所受到的数据选择线120上数据信号的电场影响。
为了进一步说明隔离线130在像素结构100内的位置，请参考图2、图3。图2、图3是说明本发明一些实施例的像素结构200、300的截面示意图。
在一实施例中，如图2所示，隔离线230与数据选择线220、共同电极240设置于相同层(例如第一金属层)。像素电极210(包含电极211、212)设置于第三金属层，并且半导体层250、260设置于像素电极210与数据选择线220(与隔离线230)之间。由于设置隔离线230，数据选择线220传递数据信号时产生的电场E对电极211、212的影响因而有效地降低。
或者，在另一实施例中，如图3所示，数据选择线220、共同电极240设置于第一金属层。隔离线330设置于第二金属层，并且半导体层250设置于隔离线330与数据选择线220之间。像素电极210(包含电极211、212)设置于第三金属层，并且半导体层260设置于像素电极210与隔离线330之间。换言之，隔离线330设置于数据选择线220与像素电极210之间。类似地，由于设置隔离线330，数据选择线220传递数据信号时产生的电场E对电极211、212的影响因而有效地降低。
为了说明隔离线130、230、330的设置改善显示质量的效果，请参考表一。在不同灰阶与温度的条件下，含有隔离线130、230、330的像素结构100、200、300均具有较低的光学数值L*。须说明的是，光学数值L*为像素与邻近像素的对比度比值，并且光学数值L*越小则表示像素的显示质量越佳。因此，含有隔离线130、230、330的像素结构100、200、300可有效地改善亮度不均(Mura)的问题。
表一
Figure BDA0001133567400000051
须说明的是，为了有效地隔离数据选择线220上数据信号对像素电极210的影响，隔离线230、330可沿着像素电极210设置。具体而言，由于数据选择线220对电极212的影响较大，因此隔离线230可沿电极212设置以减低数据选择线220上数据信号的电场E的影响。
在进一步的实施例中，隔离线230(或隔离线330)与数据选择线220间隔的第二距离d2(例如介于3微米(μm)至7微米的范围)小于像素电极210与数据选择线220的距离d。此外，隔离线230(或隔离线330)与像素电极210间隔的第一距离d1(例如介于3微米至7微米的范围)不大于像素电极210与数据选择线220的距离d。此外，隔离线230(或隔离线330)的宽度与数目可依实际情况调整，以达到良好的电场隔离效果。
实际应用上，隔离线130、230、330与数据选择线120、220可以是金属导线，然而本发明不以此为限。
综上所述，本发明可通过耦接固定电压(例如接地端)的隔离线130、230、330来降低数据选择线120、220上数据信号的电场E对像素电极110、210(尤其是电极112、212)的影响。因此，可降低亮度不均(Mura)的现象，有效地提升像素结构100、200、300的显示质量。
虽然本发明已以实施方式公开如上，然其并非用以限定本发明，任何所属领域中的一般技术人员，在不脱离本发明内容的精神和范围内，当可作各种的变动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (10)

1.一种像素结构，其特征在于，包含：
像素电极，用以储存像素电压，所述像素电极包含：
第一电极；以及
第二电极，其中所述第一电极与所述第二电极间具有缝隙，所述第二电极以桥接方式电性耦接所述第一电极以增加所述像素电极面积；
至少一个数据选择线，用以传递至少一个数据信号；以及
至少一个隔离线，沿所述像素电极排列并用以降低所述至少一个数据信号的电场对所述像素电极的所述像素电压的影响，其中所述至少一个隔离线的投影区域与所述像素电极的投影区域重叠。
2.如权利要求1所述的像素结构，其特征在于，所述至少一个隔离线的投影区域与所述第二电极的投影区域重叠。
3.如权利要求1所述的像素结构，其特征在于，所述至少一个隔离线与所述至少一个数据选择线设置于相同层。
4.如权利要求1所述的像素结构，其特征在于，所述至少一个隔离线设置于所述像素电极与所述至少一个数据选择线之间。
5.如权利要求1所述的像素结构，其特征在于，所述至少一个隔离线与所述像素电极间隔第一距离，所述第一距离不大于所述像素电极与所述至少一个数据选择线的距离。
6.如权利要求5所述的像素结构，其特征在于，所述第一距离介于3微米至7微米的范围。
7.如权利要求1所述的像素结构，其特征在于，所述至少一个隔离线与所述至少一个数据选择线间隔第二距离，所述第二距离小于所述像素电极与所述至少一个数据选择线的距离。
8.如权利要求7所述的像素结构，其特征在于，所述第二距离介于3微米至7微米的范围。
9.如权利要求1所述的像素结构，其特征在于，所述至少一个隔离线电性耦接至固定电压。
10.如权利要求1所述的像素结构，其特征在于，所述至少一个隔离线电性耦接至接地端。
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KR102317719B1 (ko) 2015-02-23 2021-10-26 삼성디스플레이 주식회사 액정 표시 장치
KR102509891B1 (ko) * 2016-01-06 2023-03-14 티씨엘 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 액정표시장치
CN105467696A (zh) * 2016-01-18 2016-04-06 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN205450519U (zh) * 2016-03-31 2016-08-10 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
KR20170115133A (ko) * 2016-04-04 2017-10-17 삼성디스플레이 주식회사 액정 표시 장치

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