CN107958910B - Active switch array substrate and manufacturing method thereof - Google Patents
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- CN107958910B CN107958910B CN201711391944.6A CN201711391944A CN107958910B CN 107958910 B CN107958910 B CN 107958910B CN 201711391944 A CN201711391944 A CN 201711391944A CN 107958910 B CN107958910 B CN 107958910B
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- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000002184 metal Substances 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 40
- 230000008569 process Effects 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000007769 metal material Substances 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 10
- 239000010409 thin film Substances 0.000 description 9
- 230000007704 transition Effects 0.000 description 6
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The embodiment of the invention discloses an active switch array substrate and a manufacturing method thereof. The scanning line is provided with a hollow area, and the first pixel electrode is arranged at the intersection of the data line and the scanning line; the first path end of the first active switch element is connected with the data line, the second path end of the first active switch element is connected with the first pixel electrode, the control end of the first active switch element is connected with the scanning line, and the joint of the second path end of the first active switch element and the first pixel electrode is positioned in the hollow area. According to the active switch array substrate provided by the embodiment of the invention, the hollow-out area is arranged on the scanning line in the pixel unit structure, and the joint of the active switch element and the pixel electrode is arranged in the hollow-out area, so that the non-light-transmitting area of the active switch array substrate is reduced, and the pixel aperture ratio is effectively improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an active switch array substrate and a manufacturing method thereof.
Background
With the development of liquid crystal display technology, liquid crystal display panels are increasingly improved towards the trend of high definition, high image quality and wide color gamut. However, the large-sized lcd panel still has the problems of low aperture ratio and poor light efficiency of the active switching array substrate, and is one of the issues to be improved urgently.
Disclosure of Invention
Embodiments of the present invention provide an active switch array substrate and a method for manufacturing the same, so as to achieve the technical effects of increasing an aperture ratio and improving a light efficiency.
An active switch array substrate provided by an embodiment of the present invention includes:
a substrate;
the scanning line is arranged on the substrate and provided with a hollow area;
the data line is arranged on the substrate and is crossed with the scanning line;
the first pixel electrode is arranged on the substrate and is arranged at the intersection of the scanning line and the data line;
the first active switch element is arranged on the substrate, a first path end of the first active switch element is connected with the data line, a second path end of the first active switch element is connected with the first pixel electrode, a control end of the first active switch element is connected with the scanning line, and a joint of the second path end and the first pixel electrode is positioned in the hollow area.
In an embodiment of the invention, the active switch array substrate further includes a common electrode wiring, the common electrode wiring and the scan line are located in the same layer and include a plurality of conductive line segments, the plurality of conductive line segments are respectively disposed at two sides of the scan line, and a part of the plurality of conductive line segments extends into a groove at one side of the scan line.
In an embodiment of the present invention, the active switch array substrate further includes:
the second pixel electrode is arranged on the substrate and is arranged at the intersection of the scanning line and the data line, and the second pixel electrode is arranged on the other side of the scanning line relative to the first pixel electrode;
a first path end of the second active switching element is connected with the data line, a second path end of the second active switching element is connected with the second pixel electrode, a control end of the second active switching element is connected with the scanning line, and a connection position of the second path end and the second pixel electrode is located in the hollow area;
a third active switching element, a first path end of the third active switching element being capacitively coupled to the common electrode wiring, a second path end of the third active switching element being connected to a second path end of the second active switching element.
In an embodiment of the invention, the second via end of the first active switching element is connected to the first pixel electrode through a first transition hole located in the hollow area.
In an embodiment of the invention, the second via end of the second active switching element is connected to the second pixel electrode through a second switching layer hole located in the hollow area.
In an embodiment of the invention, the first via end of the third active switching element is connected to a transparent conductive layer through a third layer-switching hole, the transparent conductive layer and the first pixel electrode are located in the same layer, and the third layer-switching hole is located in a groove on one side of the scan line.
In addition, a method for manufacturing an active switch array substrate according to an embodiment of the present invention includes:
forming a metal material layer on a substrate and patterning the metal material layer to form a first metal layer with a first hollow area;
forming a semiconductor layer and a second metal layer on the first metal layer, wherein the semiconductor layer is positioned between the first metal layer and the second metal layer;
forming an insulating layer on the second metal layer and forming a layer-switching hole at a position of the insulating layer corresponding to the first hollow-out region;
and forming a pixel electrode layer on the insulating layer and connecting the pixel electrode layer with the second metal layer through the transfer layer hole.
In an embodiment of the invention, the semiconductor layer and the second metal layer are respectively manufactured by two photo-masking processes, and the semiconductor layer has a second hollow area corresponding to the first hollow area.
In one embodiment of the present invention, the semiconductor layer and the second metal layer are formed by a same photolithography process.
In one embodiment of the present invention, the first metal layer includes a scan line, a common electrode wiring, and a gate electrode of an active switching element, and the second metal layer includes a data line and source and drain electrodes of the active switching element.
The technical scheme has the following advantages or beneficial effects: according to the active switch array substrate, the hollow-out area is arranged on the scanning line in the pixel unit structure, and the connecting part of the active switch element and the pixel electrode is arranged in the hollow-out area, so that the non-light-transmitting area of the active switch array substrate is reduced, and the pixel aperture opening ratio is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an active switch array substrate according to an embodiment of the invention;
fig. 2 is a schematic diagram of a first step of a method for manufacturing an active switch array substrate according to another embodiment of the invention;
FIG. 3 is a schematic diagram of a second step of a method for manufacturing an active switch array substrate according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a third step of a method for manufacturing an active switch array substrate according to another embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a fourth step of a method for manufacturing an active switch array substrate according to another embodiment of the invention;
fig. 6 is a schematic diagram illustrating a fifth step of a method for manufacturing an active switch array substrate according to another embodiment of the invention;
FIG. 7 is a schematic diagram of a first step of a method for manufacturing an active switch array substrate according to yet another embodiment of the present invention;
FIG. 8 is a schematic diagram of a second step of a method for manufacturing an active switch array substrate according to yet another embodiment of the present invention;
FIG. 9 is a schematic diagram of a third step of a method for manufacturing an active switch array substrate according to yet another embodiment of the present invention;
fig. 10 is a schematic diagram illustrating a fourth step of a method for manufacturing an active switch array substrate according to yet another embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an active switch array substrate 100 according to a first embodiment of the present invention,
in this embodiment, the active switch array substrate 100 includes a substrate 110, a scan line 120 disposed on the substrate 110, a data line 130, a first pixel electrode 141, and a first active switch element 161. The scan line 120 has a hollow area 121, and the first pixel electrode 141 is disposed at the intersection of the data line 130 and the scan line 120; the first path 1611 of the first active switching element 161 is connected to the data line 130, the second path 1612 of the first active switching element 161 is connected to the first pixel electrode 141, the control end 1613 of the first active switching element 161 is connected to the scan line 120, and the connection between the second path 1612 and the first pixel electrode 141 is located in the hollow area 121.
As shown in fig. 1, the active switch array substrate 100 further includes a common electrode wire 170, the common electrode wire 170 and the scan line 120 are located on the same layer and include a plurality of wire segments, the plurality of wire segments are respectively disposed on two sides of the scan line 120, and a portion of the wire segments 171 of the plurality of wire segments extends into the groove 122 on one side of the scan line 120.
In addition, the active switch array substrate 100 further includes: a second pixel electrode 142, a second active switching element 162, and a third active switching element 163, wherein,
the second pixel electrode 142 is disposed on the substrate 110 and at the intersection of the scan line 120 and the data line 130, the second pixel electrode 142 is disposed at the other side of the scan line 120 opposite to the first pixel electrode 141, that is, the second pixel electrode 142 and the first pixel electrode 141 are symmetrically disposed opposite to the scan line 120; a first path end 1621 of the second active switch element 162 is connected to the data line 130, a second path end 1622 of the second active switch element 162 is connected to the second pixel electrode 142, a control end 1623 of the second active switch element 162 is connected to the scan line 120, and a connection point between the second path end 1622 and the second pixel electrode 142 is located in the hollow area 121; the first path terminal 1631 of the third active switching element 163 is capacitively coupled to the common electrode line 170, and the second path terminal 1632 of the third active switching element 163 is connected to the second path terminal 1622 of the second active switching element 162.
Specifically, as shown in fig. 1, the second via 1612 of the first active switch element 161 is connected to the first pixel electrode 141 through the first transition hole 1211 located in the hollow area 121; the second via end 1622 of the second active switch element 162 is connected to the second pixel electrode 142 through the second transition hole 1212 in the hollow area 121; the first via 1631 of the third active switching element 163 is connected to a transparent conductive layer 150 through a third layer-switching hole 1213, the transparent conductive layer 150 and the first pixel electrode 141 are located at the same layer, and the third layer-switching hole 1213 is located in the groove 122 at one side of the scan line 120.
It should be noted that, the active switching element in this embodiment may be a thin film transistor, a first path end of the active switching element is a source of the thin film transistor, a second path end of the active switching element is a drain of the thin film transistor, and a control end of the active switching element is a gate of the thin film transistor; of course, the first path end of the active switching element may be a drain of the thin film transistor, the second path end thereof may be a source of the thin film transistor, and the control end thereof may be a gate of the thin film transistor. In addition, it is worth mentioning that the thin film transistor may be an NMOS transistor, or may be a PMOS transistor; of course, the thin film transistor can be replaced by other three-terminal active devices. Further, the transparent conductive layer and the pixel electrode are typically transparent electrodes such as ITO (Indium Tin Oxide) electrodes.
In summary, in the active switch array substrate 100 provided in the embodiment, the hollow area 121 is disposed on the scan line 120 in the pixel unit structure, and the connection point between the active switch element and the pixel electrode is disposed in the hollow area 121, so that the non-light-transmitting area of the active switch array substrate 100 is reduced, and the pixel aperture ratio is effectively improved.
As shown in fig. 2 and fig. 6, a method for manufacturing an active switch array substrate according to another embodiment of the present invention mainly includes the following steps:
first, as shown in fig. 2, a metal material layer is formed on the substrate 210 and patterned to form a first metal layer 281 having a first hollow area 221, where the first metal layer 281 includes the scan line 220, the common electrode wire 270, and a gate electrode (not labeled in the figure, which is a part of the scan line 220) of the active switching element 261;
second, as shown in fig. 3, a semiconductor layer 282 is formed on the first metal layer 281, wherein the semiconductor layer 282 has a second hollow area 222 corresponding to the first hollow area 221;
third, as shown in fig. 4, a second metal layer 283 is formed on the semiconductor layer 282, wherein the second metal layer 283 includes the data line 230 and the source 2611 and the drain 2612 of the active switching element 261;
a fourth step, as shown in fig. 5, forming an insulating layer (not shown) on the second metal layer 283 and forming a layer-turning hole 2211 at a position of the insulating layer corresponding to the first hollow-out region 221;
in the fifth step, as shown in fig. 6, a pixel electrode layer 284 is formed on the insulating layer, and the pixel electrode layer 284 is connected to the second metal layer 283 through the transfer layer hole 2211.
In the manufacturing method of the present embodiment, the semiconductor layer 282 and the second metal layer 283 are formed by two photo-masking processes, that is, the semiconductor layer 282 is formed on the first metal layer 281 formed by the first photo-masking process by the second photo-masking process, in order to correspond to the first hollow-out region 221 of the first metal layer 281, the semiconductor layer 282 also has a second hollow-out region 222, and the area of the second hollow-out region 222 is slightly larger than that of the first hollow-out region 221.
The manufacturing method provided by this embodiment is suitable for five mask processes of the active switch array substrate, that is, the first mask process forms the scan line 220, the common electrode wiring 270 and the gate 2613 of the active switch device 261, the second mask process forms the semiconductor layer 282 of the pixel structure, the third mask process forms the data line of the pixel structure and the source 2611 and the drain 2612 of the active switch device 261, the fourth mask process forms the insulating layer with the transition hole 2211, and the fifth mask process forms the pixel electrode layer 284 and connects the pixel electrode layer 284 with the drain 2612 of the active switch device 261 through the transition hole 2211. The finally formed active switch array substrate is the active switch array substrate described in the foregoing embodiments, and details thereof are not repeated herein.
Further, as shown in fig. 7 and 10, a method for manufacturing an active switch array substrate according to another embodiment of the present invention mainly includes the following steps:
first, as shown in fig. 7, a metal material layer is formed on the substrate 310 and patterned to form a first metal layer 381 having a first hollow area 321, where the first metal layer 381 includes the scan lines 320, the common electrode lines 370, and the gates (not shown) of the active switching elements 361;
a second step of, as shown in fig. 8, forming a semiconductor layer 382 and a second metal layer 383 on the first metal layer 381, the semiconductor layer 382 being located between the first metal layer 381 and the second metal layer 383, the second metal layer 383 including the data line 330 and a source 3611 (which may be regarded as a part of the data line 330) and a drain 3612 of the active switching element 361;
third, as shown in fig. 9, an insulating layer (not shown) is formed on the second metal layer 383, and a transition layer hole 3211 is formed at a position of the insulating layer corresponding to the first hollow area 321;
in a fourth step, as shown in fig. 10, a pixel electrode layer 384 is formed on the insulating layer, and the pixel electrode layer 384 is connected to the second metal layer 383 through the transfer hole 3211.
The manufacturing method provided in this embodiment is different from the previous embodiment in that the semiconductor layer 382 and the second metal layer 383 are manufactured by using the same photo-masking process, and the manufacturing method provided in this embodiment is suitable for four photo-masking processes of the active switch array substrate, that is, the first photo-masking process forms the scan line 320, the common electrode wiring 370 and the gate of the active switch element 361 of the pixel structure, the second photo-masking process forms the semiconductor layer 382 of the pixel structure, the data line of the pixel structure and the source 3611 and the drain 3612 of the active switch element 361, the third photo-masking process forms the insulating layer with the transfer hole 3211, and the fourth photo-masking process forms the pixel electrode layer 384 and connects the pixel electrode layer 384 with the drain 3612 of the active switch element 361 through the transfer hole 3211. The four photo-mask processes provided in this embodiment can simplify the process and improve the production efficiency compared to the five photo-mask processes provided in the previous embodiment, and the finally formed active switch array substrate is the active switch array substrate described in the previous embodiment, which is not repeated herein.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. An active switch array substrate, comprising:
a substrate;
the scanning line is arranged on the substrate and provided with a hollow area;
the data line is arranged on the substrate and is crossed with the scanning line;
the first pixel electrode is arranged on the substrate and is arranged at the intersection of the scanning line and the data line;
the first active switching element is arranged on the substrate, a first path end of the first active switching element is connected with the data line, a second path end of the first active switching element is connected with the first pixel electrode, a control end of the first active switching element is connected with the scanning line, and a connection position of the second path end and the first pixel electrode is positioned in the hollow area;
the active switch array substrate further comprises a common electrode wiring, the common electrode wiring and the scanning line are located on the same layer and comprise a plurality of lead segments, the lead segments are respectively arranged on two sides of the scanning line, and part of the lead segments extend into the groove on one side of the scanning line.
2. The active switch array substrate of claim 1, further comprising:
the second pixel electrode is arranged on the substrate and is arranged at the intersection of the scanning line and the data line, and the second pixel electrode is arranged on the other side of the scanning line relative to the first pixel electrode;
a first path end of the second active switching element is connected with the data line, a second path end of the second active switching element is connected with the second pixel electrode, a control end of the second active switching element is connected with the scanning line, and a connection position of the second path end and the second pixel electrode is located in the hollow area;
a third active switching element, a first path end of the third active switching element being capacitively coupled to the common electrode wiring, a second path end of the third active switching element being connected to a second path end of the second active switching element.
3. The active switch array substrate of claim 1, wherein the second via of the first active switch element is connected to the first pixel electrode through a first via hole located in the hollow area.
4. The active switch array substrate of claim 2, wherein the second via of the second active switch element is connected to the second pixel electrode through a second via hole located in the hollow area.
5. The active switch array substrate of claim 2 or 4, wherein the first via terminal of the third active switch element is connected to a transparent conductive layer through a third via hole, the transparent conductive layer and the first pixel electrode are located on the same layer, and the third via hole is located in a groove on one side of the scan line.
6. A method for manufacturing an active switch array substrate is characterized by comprising the following steps:
forming a metal material layer on a substrate and patterning the metal material layer to form a first metal layer with a first hollow area;
forming a semiconductor layer and a second metal layer on the first metal layer, wherein the semiconductor layer is located between the first metal layer and the second metal layer;
forming an insulating layer on the second metal layer and forming a layer-switching hole at a position of the insulating layer corresponding to the first hollow-out region;
forming a pixel electrode layer on the insulating layer and connecting the pixel electrode layer with the second metal layer through the transfer layer hole;
the first metal layer comprises a scanning line and a common electrode wiring, the common electrode wiring comprises a plurality of lead segments, the lead segments are respectively arranged on two sides of the scanning line, and part of the lead segments extend into a groove on one side of the scanning line.
7. The method as claimed in claim 6, wherein the semiconductor layer and the second metal layer are formed by two mask processes, and the semiconductor layer has a second hollow area corresponding to the first hollow area.
8. The method as claimed in claim 6, wherein the semiconductor layer and the second metal layer are formed by a same mask process.
9. The method as claimed in claim 6, wherein the first metal layer further comprises a gate of an active switching device, and the second metal layer comprises a data line and a source and a drain of the active switching device.
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| CN109343284B (en) * | 2018-10-22 | 2020-10-30 | 深圳市华星光电技术有限公司 | Pixel structure, array substrate and display device |
| CN209000914U (en) * | 2018-11-21 | 2019-06-18 | 惠科股份有限公司 | A kind of array substrate and display panel |
| CN111312780B (en) * | 2020-02-27 | 2022-12-23 | 深圳市华星光电半导体显示技术有限公司 | Display panel with high aperture opening ratio, manufacturing method thereof and display device |
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