CN107924939A - Semiconductor structure with wall - Google Patents
Semiconductor structure with wall Download PDFInfo
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- CN107924939A CN107924939A CN201680048524.5A CN201680048524A CN107924939A CN 107924939 A CN107924939 A CN 107924939A CN 201680048524 A CN201680048524 A CN 201680048524A CN 107924939 A CN107924939 A CN 107924939A
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- layer
- sublayer
- semiconductor structure
- wall
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 153
- 238000000034 method Methods 0.000 claims abstract description 156
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- 239000011435 rock Substances 0.000 claims abstract description 43
- 230000008569 process Effects 0.000 claims description 54
- 238000001039 wet etching Methods 0.000 claims description 25
- 229910002704 AlGaN Inorganic materials 0.000 claims description 17
- 239000000203 mixture Substances 0.000 claims description 17
- 239000003989 dielectric material Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 24
- 150000004767 nitrides Chemical class 0.000 abstract description 15
- 238000013461 design Methods 0.000 abstract description 5
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- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 22
- 239000002019 doping agent Substances 0.000 description 22
- 229910017083 AlN Inorganic materials 0.000 description 21
- 238000001312 dry etching Methods 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
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- 239000010931 gold Substances 0.000 description 8
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- 238000010276 construction Methods 0.000 description 7
- 229910052731 fluorine Inorganic materials 0.000 description 7
- 239000011737 fluorine Substances 0.000 description 7
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- 239000000126 substance Substances 0.000 description 7
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- 229910052733 gallium Inorganic materials 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
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- 239000000460 chlorine Substances 0.000 description 2
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- KLZUFWVZNOTSEM-UHFFFAOYSA-K Aluminium flouride Chemical compound F[Al](F)F KLZUFWVZNOTSEM-UHFFFAOYSA-K 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 229910000952 Be alloy Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
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- QEMXHQIAXOOASZ-UHFFFAOYSA-N tetramethylammonium Chemical compound C[N+](C)(C)C QEMXHQIAXOOASZ-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
- H01L29/155—Comprising only semiconductor materials
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Disclose a kind of multilayer semiconductor structure being used in Group III nitride semiconductor device, the wall with deflection layer, with than the band gap narrower with deflection layer including channel layer, with band gap more broader than the channel layer, and include the cap rock of at least two sublayers.Each sublayer can be etched selectively to relative to adjacent above and below sublayer, and each sublayer includes III N materials As lxInyGazN, wherein 0≤x≤1,0≤y≤1 and 0≤z≤1, at least one sublayer has non-zero Ga contents, and has band gap more broader than the wall close to the top sublayer of the wall.The method for manufacturing this semiconductor structure is also described, wherein being recessed by optionally removing adjacent layer or sublayer to form grid and/or ohm.The performance of obtained device is improved, while provides design flexibility, and plate suqare is accounted for reduce production cost and circuit.
Description
Citation of related applications
This application claims entitled " the Novel III-Nitride Structure submitted for 11st in August in 2015
The United States serial 62/203,438 of with Spacer Layer " and submitted on April 8th, 2016 entitled
“Semiconductor Structure and Etch Technique for Monolithic Integration of
The priority of the United States serial 15/094,985 of III-N Transistors ".
Technical field
This document describes semiconductor structure and the technique for forming semiconductor structure.Describe for shape in the semiconductor structure
It is recessed into concave etching technique, such as gate recess and/or ohm, it is brilliant with single-chip integration group III-nitride on a common substrate
Body pipe.This structure and technology can be used for production for various uses high-performance transistor, such as be used for power electronic device,
In power amplifier and digital electron device.
Background technology
Statement in this section can understand the present invention and its background of application and purposes as help, but may not form existing
There is technology.
Compared with the Conventional power devices made of silicon, group III-nitride (III-N) semiconductor has many excellent electricity
Sub- performance so that manufacture is used for various application modern power electronic devices and structure is possibly realized.The limited critical electric field of silicon and
Of a relatively high resistance makes that currently available commercial power device, circuit and system are bulky and hulking, and working frequency is further subject to
Limitation.On the other hand, the critical electric field of the higher of III-N materials and the electron density of higher and mobility can obtain improved
High current, high voltage, high power and/or the high-frequency performance of power transistor, this improved power transistor are exactly advanced
Transportation system, efficiency power generation and converting system and energy transmission network there is an urgent need for.This system relies on efficient converter
Drop voltage is risen or walks to walk, and use can block big voltage and/or carry the power transistor of high current.For example, mixing
The direct current from battery is converted into alternating current using power transistor of the blocking voltage more than 500V in power car.Power
Other exemplary applications of transistor include power supply, automotive electronics device, automatic factory's equipment, motor control, traction electric machine
Driver, high voltage direct current (HVDC) electronic device, lamp ballasts, telecommunication circuit and display driver.
Although have for the III-N semiconductor device for producing the efficient power electronic device such as power amplifier and converter
Huge potentiality, but necessary to the control circuit based on silicon is still the IC design of power electronic device.In order to increase
The practicality of strong III-N devices, active demand have the single-chip integration of the III-N transistors of different threshold voltages, especially increase
The transistor of strong mode (E patterns) and depletion-mode (D mode).For example, integrated E/D pattern GaN logic circuits can substitute
Individually routine silicon logic chip.The single-chip integration of this III-N transistors with different threshold voltages can allow to public affairs
Simulation and mixed signal parts addition numeral or control function on common substrate, so as to improve the performance of gained integrated circuit, together
When additionally provide design flexibility, account for plate suqare to reduce production cost and circuit.Accurately and neatly control in common substrate
The threshold voltages of different III-N transistors be also in demand.In order to realize these targets in terms of realizing and being integrated, need
Careful technological development is wanted to determine optimal semi-conducting material composition, device architecture and manufacturing process.
For example, manufacture is gate recess for the normal important technology for closing E mode field effect transistors of power switch application.
Usually using gate recess is formed in AlGaN/GaN devices based on the dry plasma etch of chlorine, because GaN and AlGaN
All it is very inert to wet chemical etch agent.However, dry plasma etch is easy to cause damage caused by plasma
Wound and the process deviation based on etching.Plasma damage produces highdensity defect state in sunk area and reduces raceway groove
Mobility.The change of plasma etch rates makes it difficult to accurately control cup depth by timed-etch, this causes crystalline substance
Body pipe parameter, such as mutual conductance and the change of threshold voltage.Etch-rate may be further to different transistor gate lengths
And/or aspect ratio and it is different.Therefore, the gate recess technical deficiency based on dry plasma etch will be will have difference
The different types of transistor of target threshold voltage integrates on the same substrate.
Therefore, in view of above-mentioned practicality and difficulty, to by the III-N transistor single-chip integrations with different threshold voltages
Demand on a common substrate is not yet resolved.Various embodiments of the present invention are exactly developed in this background.
The content of the invention
The present invention provides partly leading for III-nitride transistor of the manufacture with different threshold voltages on a common substrate
Body structures and methods.
In one aspect, one embodiment of the present of invention is a kind of is used in group III-nitride (III-N) semiconductor devices
Multilayer semiconductor structure, including channel layer, band deflection layer, wall and cap rock.Channel layer includes being used to provide the of conduction
One III-N materials.Band deflection layer is arranged on channel layer, including the 2nd III-N materials, and has band more broader than channel layer
Gap.Wall is arranged on band deflection layer, including the 3rd III-N materials, and with than with the narrower band gap of deflection layer.Cap rock
It is arranged on wall, and including at least two sublayers, wherein each sublayer is can be relative to adjacent above and below
Etch, wherein each sublayer includes III-N materials As l layer-selectivexInyGazN, wherein 0≤x≤1,0≤y≤1 and 0≤z
≤ 1, wherein at least one sublayer has non-zero Ga contents, wherein 0<Z≤1, and wherein close to the top sublayer tool of wall
There is band gap more broader than wall.
In some embodiments of the invention, multilayer semiconductor structure further includes Ga polar surfaces.In certain embodiments,
The thickness of wall is less than or equal to 20 nanometers (nm), and is greater than or equal to 0.2nm.In certain embodiments, wall is n
Type doping.In addition, close to wall top sublayer can be using wet etching process on the upside of wall selectivity
Ground etching.Top sublayer close to wall can be etched with the speed high more than wall three times.Cap rock it is adjacent
Sublayer can have less than 50% (0≤x≤0.5) and more than 50% (0.5<X≤1) between alternate A1 contents.
In certain embodiments, the wall comprising the 3rd III-N materials has zero Al content.In certain embodiments,
Band deflection layer comprising the 2nd III-N materials has non-zero Al content.In certain embodiments, the 2nd III-N materials are
AlxGazN, wherein x+z=1,0.05<X≤0.4 and 0.6≤z<0.95.In certain embodiments, the first III-N materials are GaN,
2nd III-N materials are AlxInyGazN, wherein x+y+z=1,0<X≤1,0≤y≤1 and 0≤z≤1, and the 3rd III-N materials
Material is GaN.In certain embodiments, first, second, and third III-N materials be selected from by GaN, AlN, AlGaN, InAlN and
The group of AlInGaN compositions.
In some embodiments of the invention, multilayer semiconductor structure further comprises be arranged on channel layer at least one
Carrier donor layer above point, to provide carrier to channel layer.Carrier donor layer can have at least thickness of 0.2nm
And at least 1016cm-3Doping concentration.
In some embodiments of the invention, semiconductor structure further comprises：At least one including being arranged on channel layer
The gate regions of the grid dielectric material of upper, and it is arranged on a pair of of ohm contact outside gate regions.Semiconductor structure
It can also include the gate recess in gate regions, wherein grid dielectric material is arranged on the upside of gate recess, and gate recess
Bottom within the layer selected from the group being made of channel layer, the sublayer with deflection layer, wall and cap rock or on.
In some embodiments, semiconductor structure further comprises being arranged on above gate recess and covering the concave gate contacts of grid,
And it is arranged on the upside of grid dielectric material, the gate field extension board outside gate recess.In certain embodiments, this is to ohm
Each bottom of contact the layer selected from the group being made of channel layer, the sublayer with deflection layer, wall and cap rock it
It is interior or on.
In some embodiments of the invention, multilayer semiconductor structure further comprises：Including being arranged on the channel layer
At least a portion above anode dielectric material anode region, and be arranged on the ohmic cathode electrode outside gate regions.Europe
The bottom of nurse cathode electrode can be located to be selected from the group being made of channel layer, the sublayer with deflection layer, wall and cap rock
Within the layer selected or on.
Other aspects of the present invention are included comprising semiconductor structure the step of being described herein, technique and method, and also
Technique and operator scheme including device described herein.The detailed description of the present invention, of the invention other are read in conjunction with the figure
Aspect and embodiment will become obvious.
General introduction above provides by way of illustration, and nonrestrictive.
Brief description of the drawings
The embodiment of invention described herein is exemplary, and nonrestrictive.Referring now to attached drawing by showing
Example describes embodiment.In the drawings, each identical or nearly identical component shown in various figures is by identical
Reference numeral represent.For the sake of clarity, it is not that each component marks in each figure.Attached drawing is painted not necessarily to scale
System, but focus on the various aspects of explanation technique described herein and equipment.
Figure 1A, Figure 1B, Fig. 1 C and Fig. 1 D show according to an embodiment of the invention there is double-deck barrier structure
Semiconductor structure and concave etch process is formed in the semiconductor structure.
Fig. 2A, Fig. 2 B, Fig. 2 C and Fig. 2 D show according to an embodiment of the invention with carrier donor layer
Semiconductor structure and concave etch process is formed in the semiconductor structure.
Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D show according to an embodiment of the invention there is partly leading with deflection layer
Body structure and concave etch process is formed in the semiconductor structure.
Fig. 4 shows the semiconductor structure according to an embodiment of the invention with multiple double-deck barrier structures.
Fig. 5 shows the structure of exemplary crystal pipe according to an embodiment of the invention.
Fig. 6 A show the cap rock according to an embodiment of the invention for having and including multiple selectively etchable sublayers
Semiconductor structure.
Fig. 6 B show the semiconductor structure according to an embodiment of the invention with wall.
Fig. 7 shows the exemplary knot according to an embodiment of the invention with recessed gate transistor peace gate transistor
Structure.
Fig. 8 shows the example arrangement with two recessed gate transistors according to an embodiment of the invention.
Fig. 9 shows the example according to an embodiment of the invention for including two recessed gate transistors with doping sublayer
Property structure.
Figure 10 shows two recessed grid crystal according to an embodiment of the invention for including and having recessed ohm contact
The example arrangement of pipe.
Figure 11 is shown according to an embodiment of the invention forms concave technique on semiconductor structure.
Figure 12 shows according to an embodiment of the invention for being formed comprising two kinds of recessed gate transistor
The technique of structure.
Figure 13 shows according to an embodiment of the invention there is D mode and the illustrative of E mode transistors to be made
Device and corresponding ID-VGSCharacteristic.
Figure 14 shows the I of integrated D mode according to an embodiment of the invention and E mode transistorsD-VGSCharacteristic
Curve.
Figure 15 shows the I of integrated D mode according to an embodiment of the invention and E mode transistorsD-VDSCharacteristic
Curve.
Figure 16 shows the semiconductor junction with wall according to an embodiment of the invention using shown in Fig. 6 B
The exemplary flat grate transistor of structure.
Figure 17 shows the semiconductor junction with wall according to an embodiment of the invention using shown in Fig. 6 B
The exemplary recessed gate transistor with grid field plate of structure.
Figure 18 is the conduction band of the exemplary semiconductor structure according to an embodiment of the invention for showing to have wall
With the energy band diagram of valence band.
Figure 19 shows that according to an embodiment of the invention include has partly leading for wall using shown in Fig. 6 B
The flat grate transistor of body structure and the example arrangement of recessed gate transistor.
Figure 20 shows the semiconductor junction with wall according to an embodiment of the invention using shown in Fig. 6 B
The exemplary diode of structure.
Embodiment
In the following description, for illustrative purposes, numerous specific details are set forth in order to provide to the thorough of the present invention
Understand.It will be apparent, however, to one skilled in the art that can be real in the case of these no details
Trample the present invention.In other cases, structure, equipment, activity and method are shown using schematic diagram, use-case and/or flow chart, with
Avoid the fuzzy present invention.Although it is described below for illustrative purposes comprising many details, any person skilled in the art
It will be understood that many changes of details to being proposed and/or change are within.Similarly, although this hair
Bright many features are described in a manner of referring to or being bonded to each other each other, it will be apparent, however, to one skilled in the art, that these are special
Many features in sign can be provided independently of other features.Therefore, this description of the invention is not losing the one of the present invention
As provide in the case of property, and limitation is not applied to the present invention.
Put it briefly, the embodiment of the present invention be related to multilayer semiconductor structure with one or more gate recess and
The method for manufacturing this structure.Such sandwich construction can promote the group III-nitride (III-N) with different threshold voltages
The single-chip integration of transistor.The threshold voltage of transistor is that transistor becomes an OFF state passed through grid electricity from conducting state
Pressure, vice versa.This multilayer semiconductor structure utilizes selectively etchable layer or the sublayer set on a common substrate, wherein
Selectively etchable property makes it possible to form gate recess and/or ohm depression with controllable depth, thus produce it is desired or
The threshold voltage of target.Different types of transistor, the especially single-chip integration of E patterns and D mode transistor can be by permitting
Perhaps further this device is greatly enhanced to the simulation in common substrate and mixed signal parts addition numeral or control function
Practicality, so as to improve the performance of obtained integrated circuit, while additionally provide design flexibility to reduce production cost
Plate suqare is accounted for circuit.
Gate recess is important technology for certain form of transistor, including the crystal based on nitride-based semiconductor
Pipe, such as AlGaN/GaN high electron mobility transistor (HEMT).In radio frequency AlGaN/GaN HEMT, using gate recess
To reduce short-channel effect and improve current gain cutoff frequencies.In power switch application, manufactured using gate recess
Field-effect transistor is often closed, such as AlGaN/GaN HEMT.Since very big inertia is presented to wet chemical etchants in GaN and AlGaN,
Usually using based on the dry plasma etch of chlorine gate recess is formed in AlGaN/GaN devices.However, dry method etc. from
Daughter be etched with two it is main the shortcomings that：1) plasma damage may be caused, highdensity defect is produced in sunk area
State simultaneously reduces channel mobility；With 2) due to the change of plasma etch rates, it may be difficult to by timed-etch come smart
Cup depth really is controlled, this causes such as mutual conductance (gm) and threshold voltage (VT) etc transistor parameter deviation.When with
When the device of different grid lengths undergoes identical gate recess etch technique, the control of device deviation becomes more challenge,
Because for different transistor gate length and/or aspect ratio, etch-rate may be different.
This document describes the technique of semiconductor structure and this semiconductor structure of formation, while reduce or eliminate plasma
Caused damage and the process deviation based on etching.Recess etch manufacturing technology is described, it is deep that it can accurately control etching
Spend and the defects of extremely low density is being produced on sunk surface.In certain embodiments, semiconductor structure described herein can be by
Compound semiconductor materials, such as one or more III-V group semi-conductor materials, particularly group III-nitride (III-N) are partly led
Body material is formed.Using this technology, high-performance transistor can be manufactured, such as RF III-N and/or normal pass III-N power crystals
Pipe.
It is described further herein multiple transistors with different threshold voltages to be integrated on a common substrate
Multilayer semiconductor structure, and the technique for forming this semiconductor structure.There is provided to the accurate of single etch depth
Control and while the defects of extremely low density is produced in concave surface, multilayer semiconductor structure as described herein and depression are lost
Carve manufacturing technology can also realize with different gate recess depth and/or ohm cup depth thus cause different threshold value electricity
The flexible of multiple transistor devices of pressure integrates side by side.
Technique described herein can utilize different semi-conducting materials, such as the etching between different III-N semi-conducting materials
Selectivity.It is, for example, possible to use dry etch technique is in such as AlN, AlGaN, InAlN and AlInGaN with high Al content
Material on be etched selectively to GaN.In certain embodiments, selective dry etch step, subsequent wet method erosion can be used
Carve step and the accurate of cup depth is controlled and produce the surface with low-density defect state to realize.If perform wet method
Etching step, then can be selective or non-selective.If wet etch step is selective, can use wet
Method etching technique is etched selectively to have on the material of such as GaN, AlGaN, InGaN and AlInGaN with low al content
There are AlN, AlGaN, InAlN and AlInGaN of high Al content.However, technique described herein is not limited to wet etch step.
Refer to the attached drawing, will now be described in more detail the embodiment of the present invention.
Figure 1A shows the semiconductor structure 1 that can perform etching technique as described herein thereon.Semiconductor structure 1 can
With including substrate 2, cushion 4, channel layer 6 and barrier layer 8.Each layer can have the thickness of at least 0.2 nanometer (nm), and
Channel layer 6 can have the thickness between 1nm and 10,000nm or 10 μm.Barrier layer 8 includes upper barrier layer 10 and lower barrierlayer
12.In certain embodiments, upper barrier layer 10 by the material that the first etching technique etches by can be formed, such as dry etching,
Lower barrierlayer 12 by the material that the second etching technique etches by can be formed, such as wet etching.In the present embodiment, lower potential barrier
Layer 12 is not used for the first etching technique etching for etching barrier layer 10 substantially, so as to form etching stopping layer.Now will
Description can form the example of the material of semiconductor structure 1.
In certain embodiments, side formation there can be the lattice constant different from the lattice constant of substrate 2 on the substrate 2
Semi-conducting material.In certain embodiments, cushion 4 can be included between substrate 2 and the semi-conducting material of covering with suitable
Answer the difference of lattice constant.Substrate 2 can include IV, III-V or Group II-VI semiconductor material, such as silicon, germanium or ZnO.Other
Typical substrate includes SiC, sapphire, Si and bulk GaN.Chemical combination can be included by being formed in the semi-conducting material of the upside of substrate 2
Thing semi-conducting material, such as III-V semi-conducting materials (for example, III-N materials).One of ordinary skill in the art will appreciate that make
The appropriate technology with the lattice mismatch between the substrate 2 of different lattice constants and semi-conducting material is adapted to cushion 4,
This is no longer described in detail.In certain embodiments, can use with the suitable crystalline substance for being used for the compound semiconductor materials for forming covering
The substrate 2 of lattice constant, and can be omitted cushion 4.For example, substrate 2 can be GaN substrate, ZnO substrates or with being similar to
By another substrate of the material of the lattice constant for the compound semiconductor materials being formed on.Technique described herein is unlimited
In substrate 2 or cushion 4.Although in addition, it is not explicitly depicted in figure ia, in certain embodiments, in substrate 2 and cushion
Nucleating layer is set between 4；In some other embodiments, cushion 4 is including nucleating layer or nucleation with the interface of substrate 2
Area.
Substrate 2 and the semiconductor material layer formed thereon can be monocrystalline, and can have any suitable crystal
Orientation.If included in substrate 2 or cap rock, compound semiconductor materials can have any at the face of semi-conducting material
Suitable composition.If comprising III-N materials, which may have N faces composition or III group face composition.For example, GaN can
With with N faces/N poles, Ga faces/Ga poles or nonpolar oriented growth.
Channel layer 6 can be by forming suitable for forming the semi-conducting material of raceway groove wherein.In certain embodiments, channel layer
6 can include III-V semi-conducting materials, such as III-N semi-conducting materials.In certain embodiments, channel layer 6 can include nitrogen
Change gallium (GaN).In certain embodiments, nitride semi-conductor material, such as B can be usedwAlxInyGazN, wherein w, x, y and
Z each has the desired value between 0 and 1 between (including 0 and 1), and w+x+y+z=1.
In certain embodiments, semiconductor heterostructure can be formed in semiconductor structure 1.For example, in some implementations
In example, it can be formed comprising Bw1Alx1Iny1Gaz1The barrier layer 8 of N and include Bw2Alx2Iny2Gaz2The channel layer 6 of N, wherein potential barrier
The semi-conducting material of layer 8 has the band gap and/or polarization than 6 bigger of channel layer.However, technique described herein is not limited to be formed
Heterojunction structure.
As implicitly implied that above, in certain embodiments, each layer that side is formed on the substrate 2, including cushion
4th, channel layer 6 and barrier layer 8, can include more than one material, including III-N materials.For example, cushion 4 can include
AlN/GaN superlattices.In certain embodiments, a part or one or more areas for cushion 4 or raceway groove 6 can be GaN.This
The region of sample can be located at bed boundary, or be located relative to the position that desired grid or ohm contact region is particularly limited to
Place.For example, foregoing nucleating layer can be included in the interface with substrate 2 as a part for cushion 4.Other
In other embodiment, one or more layers that side is formed on the substrate 2 can be adulterated with suitable dopant.
As described above, in certain embodiments, it can be formed with two or more layers or the barrier layer of sublayer 8.Example
Such as, barrier layer 8 can include " bilayer " barrier structure, which, which has, can be used what the first etching technique etched
The upper barrier layer 10 of first semi-conducting material and can be used the second etching technique etch the second semi-conducting material lower barrierlayer
12.In certain embodiments, upper barrier layer 10 can include can in dry method etch technology selective etch semi-conducting material,
Such as GaN, or another nitride semi-conductor material, such as BwAlxInyGazN, wherein w, x, y and z each have between 0 and 1
Between desired value between (including 0 and 1), and w+x+y+z=1, and forming so that dry method etch technology selection can be used
Etch nitride semi-conductor material to property.For example, upper barrier layer 10 can include such as BwAlxInyGazThe semi-conducting material of N,
Wherein x is less than 0.25.
Upper barrier layer 10 can be doped or undoped.The doping of upper barrier layer 10 can be downwards channel layer 6 supply carry
Stream.After grid is recessed, it can be formed outside gate recess, between grid and source electrode and/or between grid and drain electrode
One or more doped regions.Doped region can be polarization doping, or can include such as n-type dopant or p-type dopant
Etc dopant.Doped region can have any suitable doping concentration and distribution.For example, can be under upper barrier layer 10
Surface, upper barrier layer 10 upper surface and/or another location provide dopant.Dopant profiles can be uniform or uneven
's.Doping concentration can be at least 1016cm-3.In certain embodiments, increment dopant profiles can be used.If upper barrier layer
10 are doped, then can use any suitable doping techniques, such as inject or spread.In certain embodiments, upper barrier layer
10 can the doping during its formation (such as growth).In certain embodiments, the doping type of upper barrier layer 10 can be with ditch
The type of carrier is identical in road area.For example, the doping type in upper barrier layer 10 can be N-shaped for n-channel transistor, it is right
In p-channel transistor can be p-type.In certain embodiments, doped region can be high doped.
The semi-conducting material that lower barrierlayer 12 can be etched including usable wet etch technique, such as aluminium nitride (AlN),
Or another material, such as BwAlxInyGazN.Example, wherein w, x, y and z each have the conjunction between 0 and 1 (including 0 and 1)
Just when, and w+x+y+z=1, and form so that wet etching process can be used to etch for nitride semi-conductor material.For example,
Lower barrierlayer 12 can include such as BwAlxInyGazThe semi-conducting material of N, wherein x are more than 0.5.It is in addition it is possible to use any
Suitable doping techniques adulterate lower barrierlayer 12, such as the doping skill that is discussed of optional doping above for upper barrier layer 10
Art.
Herein to BwAlxInyGazN or " BwAlxInyGazThe reference of N materials " refers to nitride and boron, aluminium, indium and gallium
In one or more semi-conducting materials.BwAlxInyGazThe example of N materials includes binary, ternary and quaternary compound, makees
For example, such as GaN, AlN, AlGaN, AlInGaN, InGaN and BAlInGaN.BwAlxInyGazThe example of N materials further includes
Compound with relative percentage, wherein w, x, y and z each have between 0 and 1 desired value (0≤w≤1,0≤x≤1,0
≤ y≤1, and 0≤z≤1), and w+x+y+z=1.BwAlxInyGazN materials can also be included except nitride, boron, aluminium, indium
And/or the other materials outside gallium.For example, BwAlxInyGazN materials can be doped with suitable dopant, such as silicon and germanium.
In addition, in the disclosure, unless specified or limited otherwise, term " BwAlxInyGazN materials " and " III-N materials " is interchangeable makes
To represent nitride-based compound semiconductor material.
It will describe to form crystalline substance in Figure 1A semiconductor structure 1 using two single etching steps with reference to figure 1B to Fig. 1 D
The technique of body pipe.
As shown in Figure 1B, the first etching step can be performed to remove the one of upper barrier layer 10 using the first etching technique
Part.The region to be etched can be limited using suitable mask process.The etching technique used in the first etching step
Can relative to lower barrierlayer 12 material selectivity etch the material of upper barrier layer 10.Used in the first etching step
The selectivity of etch process can be more than 1 so that upper barrier layer 10 is with than the etching of 12 faster speed of lower barrierlayer.In some realities
Apply in example, the selectivity of the etch process used in the first etching step can be more than 3:1 so that with more than the lower potential barrier of etching
The upper barrier layer 10 of speed etching of the three times of the speed of layer 12.
As described above, the first etching technique can include dry etch technique (for example, dry plasma etch, also by
Referred to as reactive ion etching (RIE)).If upper barrier layer includes GaN, such as can use the etch process based on fluorine.Figure
1B shows the semiconductor structure 1 after the region of barrier layer 10 is removed using dry method etch technology.Lower barrierlayer 12 can
For use as etching stopping layer, dry method etch technology is stopped with surface on it.Dry method etch technology may damage lower barrierlayer 12
Upper surface, so as to produce damaged zone 14.However, in certain embodiments, dry method etch technology may not produce any aobvious
The damage of work.In certain embodiments, the damaged zone 14 of barrier layer 12 can be removed in the second etching step damaged zone 14 it
Preceding oxidation.
As shown in Figure 1 C, the second etching step can be performed to remove the one of lower barrierlayer 12 using the second etching technique
Part.However, the second etching step is optional, not necessarily perform.
, can be in the region by removing barrier layer 10 in the first etching step if performing the second etching step
And a part for lower barrierlayer 12 is removed in the window formed.In certain embodiments, the erosion used in the second etching step
Carving technology can come relative to covering lower barrierlayer 12 and the layer that can be contacted with lower barrierlayer 12, such as upper barrier layer 10
Selective etch lower barrierlayer 12.In certain embodiments, the etch process used in the second etching step can be relative to
The layer for the lower section of lower barrierlayer 12 that can be contacted with lower barrierlayer 12, such as channel layer 6 and/or with deflection layer, come optionally
Etch lower barrierlayer 12.Lower barrierlayer 12 can be more than 1 relative to the selectivity of the etching of upper barrier layer 10 and/or channel layer 6,
So that the etch-rate of lower barrierlayer 12 is more than the etch-rate of upper barrier layer 10 and/or channel layer 6.In certain embodiments,
Selectivity can be more than 3:1 so that lower barrierlayer 12 is with more than the etching of the speed of upper barrier layer 10 and/or the three times of channel layer 6.
However, the second etching step be not necessarily it is selective, and in certain embodiments, can not relative to upper barrier layer 10 or
Channel layer 6 is etched selectively to lower barrierlayer 12.
As described above, the etching technique used in the second etching step can be wet etch technique.Fig. 1 C are shown
Semiconductor structure 1 after the region of lower barrierlayer 12 is removed using wet etching process.Wet etching process can remove
Affected area 14, and the gate recess 16 for not having affected area at its lower surface can be formed in.As shown in Figure 1 C, wet method is lost
Carving technology can remove the whole thickness of lower barrierlayer 12, or can remove a part of thickness of lower barrierlayer 12.At some
In embodiment, finely controlling to the depth of gate recess 16 can be provided to etch lower barrierlayer 12 using wet etching process
System, and transistor characteristic caused by technique is reduced or eliminated, the deviation of such as threshold voltage.
As shown in figure iD, gate-dielectric 18 and grid 20 can be formed in gate recess 16.18 He of gate-dielectric
Grid 20 can use any suitable material.Gate-dielectric 18 can be formed by any suitable insulator, such as be aoxidized
Silicon, silicon nitride, Al2O3, AlN or high κ dielectrics, or these combination.Grid 20 can be led by any suitable conductor or partly
Body is formed, such as metal or polysilicon.Source area and drain region S and D can also be formed, as those of ordinary skill in the art manage
Solution.Source area S and/or drain region D can be formed by suitable conductor or semiconductor, and such as metal and/or doping are partly led
Body region.Source area and/or drain region S and D can have ohm contact.
In certain embodiments, can be etched selectively in the upside of lower barrierlayer 12, source area and/or drain region
Barrier layer 10.Wet etching can be carried out to lower barrierlayer 12 in source area and/or drain region so that can be in source area
And/or ohmic metal is formed on the remaining barrier layer in drain region.In certain embodiments, respectively to upper barrier layer 10 and/
Or lower barrierlayer 12 carries out dry method and/or wet etching can be for forming grid to form source area and/or drain region
Perform in identical one or more etch process, or performed in different technique.
In certain embodiments, the part of remaining barrier layer 8 can have less than critical after formation gate recess 16
The thickness of thickness, it is square into two-dimensional electron gas (2DEG) (for example, see Fig. 5) under the gate to prevent, often close crystal so as to be formed
Pipe.However, discussed as will be referred to Fig. 7-10, technique described herein, which is not limited to be formed, often closes transistor, can be used for being formed
Other devices, such as normally on transistors.
The Operation Summary of normally opened and normal pass transistor is as follows.When normal pass or enhancement mode (E patterns) transistor do not apply
To grid voltage when, transistor is off state and substantially non-conductive.When applying suitable voltage to grid, often
It is in the conduction state to close transistor, and carrier can flow between it dominates electric terminal (for example, source electrode and drain electrode).It is brilliant
The threshold voltage of body pipe is that transistor becomes an OFF state passed through grid voltage from conducting state, and vice versa.Often close (E
Pattern) transistor threshold voltage VTIt is typically positive.When normally opened or depletion-mode (D mode) transistor is not applied to grid
Voltage when, transistor is in the conduction state and carrier can be between it dominates electric terminal (for example, source electrode and drain electrode)
Flowing.When normally on transistors has the suitable voltage for being applied to grid, often turn on transistor and be off state and basic
On be not turned on.The threshold voltage V of normally opened (D mode) transistorTUsually negative value.
In certain embodiments, can be by being supplied different from the layer of upper barrier layer 10 or lower barrierlayer 12 to channel layer 6
Carrier.Fig. 2A to Fig. 2 D is shown in which the embodiment for including special carrier donor layer 22 in the semiconductor structure.Scheming
In embodiment shown in 2A to Fig. 2 D, carrier donor layer 22 is formed in the upside of barrier layer 10.However, technique described herein
It is unrestricted in this regard, because carrier donor layer 22 can be formed in the lower section of barrier layer 10 or another position.One
In a little embodiments, carrier donor layer 22 can be formed by the material identical with upper barrier layer 10.
Carrier donor layer 22 can supply carrier to channel layer 6.Removing a part for carrier donor layer 22
After grid is recessed, the remainder of carrier donor layer 22 can by carrier supplied to about under the gate square region it
Outer channel layer 6.If be included in it is semiconductor laminated in, carrier donor layer 22 can use any suitable doping techniques
Doping, the doping techniques that the optional doping as mentioned above for upper barrier layer 10 is discussed., can be in grid after grid is recessed
One or more is formed in carrier donor layer 22 outside depression, between grid and source electrode and/or between grid and drain electrode to mix
Miscellaneous area.Doped region can be polarization doping, or can include the dopant of such as n-type dopant or p-type dopant.Doping
Area can have any suitable doping concentration and distribution.For example, it can be supplied in the lower surface of carrier donor layer 22, carrier
The upper surface of body layer 22 and/or another position provide dopant.Dopant profiles can be uniform or non-uniform.At some
In embodiment, carrier donor layer 22 can have at least thickness of 0.2nm, and at least 1016cm-3Doping concentration.One
In a little embodiments, carrier donor layer 22 can include the sublayer with different levels of doping.In certain embodiments, can make
With increment dopant profiles.It is, for example, possible to use any suitable doping techniques, such as inject or spread.In certain embodiments,
Carrier donor layer 22 can be in its formation or growth period doping.In certain embodiments, the doping of carrier donor layer 22
Type can be identical with the type of carrier in channel region.For example, the doping type in carrier donor layer 22 is brilliant for n-channel
Body pipe can be N-shaped, can be p-type for p-channel transistor.In certain embodiments, doped region can be high doped.
If including carrier donor layer 22, in certain embodiments, upper barrier layer 10 and/or lower barrierlayer 12 can undope.
In certain embodiments, carrier donor layer 22 can be by that can pass through the semi-conducting material of dry method etch technology etching
Formed.Carrier donor layer 22 can include the compound semiconductor of such as III-V semi-conducting materials etc, such as III-N half
Conductor material, such as BwAlxInyGazN, wherein w, x, y and z each have the desired value between 0 and 1 (including), and w
+ x+y+z=1, and form so that III-N semi-conducting materials can be etched using dry method etch technology.Such as Fig. 2A to Fig. 2 D
Shown, barrier layer 28 can include carrier donor layer 22, upper barrier layer 10 and lower barrierlayer 12.
In certain embodiments, carrier donor layer 22 can be to the electric field of (such as in channel region) in semiconductor structure
Carry out shaping.Doping density can be adjusted as needed to carry out shaping to electric field.In certain embodiments, carrier donor layer
22 may be used as passivation layer.Carrier donor layer 22 can have any suitable thickness.In certain embodiments, carrier supplies
The thickness of body layer 22 can be more than 5nm.
As shown in Figure 2 B, carrier donor layer can be etched away using the first etch process of such as dry method etch technology
22 and the region of upper barrier layer 10.As shown in Figure 2 C, wet etching process can be used to remove the region of lower barrierlayer 12.Such as figure
Shown in 2D, gate-dielectric 18 and grid 20 can be formed in gate recess.Source area and the leakage of transistor can also be formed
Polar region S and D.
In certain embodiments, semiconductor structure can include the band deflection layer 32 between channel layer 6 and lower barrierlayer 12.
The band offset between barrier layer 38 and channel layer 6 can be increased with deflection layer 32.As shown in Fig. 3 A to Fig. 3 D, barrier layer 38 can be with
Including upper barrier layer 10, lower barrierlayer 12 and with deflection layer 32.
As shown in Figure 3B, upper barrier layer 10 can be etched away using the first etch process of such as dry method etch technology
Region.Then wet etching process can be used to remove the region of lower barrierlayer 12, as shown in Figure 3 C.In certain embodiments,
Band deflection layer 32 can be very thin, has the thickness less than critical thickness, so as to when forming grid in 32 upside of band deflection layer
Produce and often close transistor.In certain embodiments, band deflection layer 32 can be thicker than critical thickness.When band deflection layer 32 is than critical
When thickness is thicker, the thickness that at least a portion with deflection layer 32 causes remainder can be removed by using wet etching process
Degree often closes transistor less than critical thickness to produce.Gate-dielectric 18 and grid 20 can be formed in gate recess, such as schemed
Shown in 3D.The source area and drain region S and D of transistor can be formed.Alternatively, the embodiment as shown in Fig. 3 A to Fig. 3 D can be with
Including carrier donor layer 22 (not shown in Fig. 3 A to Fig. 3 D).
In certain embodiments, semiconductor structure can include multiple " bilayer " barrier structures.It is any suitable to include
" bilayer " barrier structure of quantity.For example, as shown in figure 4, semiconductor structure 40 can include the first bilayer barrier structure 8a with
Second double-deck barrier structure 8b, each bilayer barrier structure have upper barrier layer 10 and lower barrierlayer 12.Potential barrier in fig. 4, the upper
Layer and lower barrierlayer are expressed as 10a and 12a for double-deck barrier structure 8a, for double-deck barrier structure 8b, represent respectively
For 10b and 12b.Double-deck barrier structure 8a and 8b can have identical structure and/or composition, or different structure and/or group
Into.In order to form the depression of such as gate recess, the first etch process (for example, dry method etch technology) can be performed to remove layer
The region of 10a, then can perform the second etch process (for example, wet etching process) to remove the region of layer 12a.Then,
The first etch process (for example, dry method etch technology) can be performed to remove the region of layer 10b, and the second etching can be performed
Technique (for example, wet etching process) is to remove the region of layer 12b.As described above, gate-dielectric 18 and grid 20 can be with shapes
Into in gate recess.The source area and drain region S and D of transistor can also be formed.It can include in semiconductor structure 40
Band deflection layer 32 and/or carrier donor layer 22.However, technique described herein is unrestricted in this regard, because with offset
Layer 32 and carrier donor layer 22 are optional.
Description provided above is the concave technology of formation for the gate recess that can be applied to be formed transistor.This skill
Art can be applied to the transistor of any suitable type, including such as MISFET (conductor insulator semiconductor fet)
With any kind of field-effect transistor of MESFET (metal-semiconductor field effect transistor) etc.
Technique described herein is not limited to be formed the technology of gate recess.This technology can be used for needing not damaged,
Any other application of even and/or reproducible etching.One example be to be formed ohm depression with reduce ohm contact resistance and/
Or form the ohm contact without gold.Another example is to form one or more depressions to approach GaN light emitting diodes or laser
N doped layers in device.Another example is to form one or more depressions to approach the base stage in III-N bipolar transistors
And/or collector layer.
Fig. 5 shows the unrestricted of the transistor with gate recess that is produced according at least some technologies described herein
Property example.In this exemplary embodiment, upper barrier layer 10 can be formed by GaN, and lower barrierlayer 12 can be formed by AlN, band
Deflection layer 32 can be by Al0.15Ga0.85N is formed.The upper barrier layers of GaN can by based on the dry etching of fluorine in AlN lower barrierlayers
Upside is etched selectively to.The alkali of such as potassium hydroxide (KOH) and/or tetramethyl ammonium hydroxide (TMAH) etc can be used to lead to
Wet etching process is crossed, or by digital etch process, barrier layer and Al on GaN0.15Ga0.85Selection on the upside of N band deflection layers
Etch AlN lower barrierlayers to property.Digital etch process is understood by ordinary skill in the art, and this will not be detailed here.However,
These are only example, and can use any suitable etchant.
Fig. 5 shows the structure 500 of example transistor according to some embodiments of the invention.Having manufactured has Fig. 5
The exemplary means of shown structure.The structure is grown by metal organic chemical vapor deposition on 4 inches of silicon substrate.The knot
Structure includes having 3-6 × 10 on p-type Si (III) substrate18cm-3The 22-nm GaN of Si doping:Si cap rocks, 1.5-nm potential barriers
AlN layers, 3-nm Al0.15Ga0.85N bands deflection layer, 1.2- μm of i-GaN channel layer and 2.8- μm of cushion.Hall measurement result table
Bright, sheet resistance is 579 ± 11 Ω/sq, and two-dimensional electron gas (2DEG) mobility is 1529 ± 18cm2V-1s-1, thin layer electric charge is close
Spend for 7.1 ± 0.1 × 1012cm-2.Device manufacture is since being formed mesa-isolated and Ti/Al/Ni/Au ohm contacts, at 870 DEG C
Lower annealing 30 seconds.In order to manufacture recessed gate transistor, by the electron cyclotron resonace reactive ion etching (ECR-RIE) based on fluorine,
The n-GaN lids being etched selectively on the upside of AlN layers in recessed grid region.Due to aluminum fluoride (AlF3) it is non-volatile, for 5sccm
BCl3/35sccm SF6Gas flow rate under 35 millitorrs, 100W ECR power and 100V Dc biases, realizes on the upside of AIN
The very high etching selectivity of GaN.N-GaN layers uniform and complete is realized using being etched with overetched 350 seconds 70 seconds
Full removal.Then AlN layers of surface is aoxidized by low energy oxygen plasma, and by the surface at room temperature by hydroxide
Dipping carries out wet etching for 1 minute to remove dry etching damage in tetramethyl-ammonium (TMAH).After tmah wet etch, do
The presence of fluorine substantially reduces in method etching step.After UV ozone and HCl surface cleaning, then pass through the original at 250 DEG C
Sublayer is deposited to deposit the Al of 10nm2O3Gate-dielectric, and it is annealed 1 minute at 500 DEG C in forming gas.Such as figure
Shown in 5B, the Ni/Au gate electrodes in recessed grid region are covered with 2.5 μm of overhang length depositions.Then by shaping gas of the sample at 400 DEG C
5 minutes are annealed in body to reduce Al2O3In positive fixed charge.Obtained recessed gate transistor is recessed with what is changed from 3 μm to 20 μm
Gate length Lrec-g。
DC (direct current) characteristic of recessed grid GaN MISFET 500 can be studied.Device threshold voltage VTIt can be defined as VT=
Vgsi-0.5Vds.Wherein VgsiIt is Id-VgsThe interception voltage of curve linear extrapolation, is not shown here.Low drain pole tension can be applied
(Vds=0.1V) device is placed in linear operating region.It is averaged to 13 devices, recessed grid GaN MISFET have equal
The V of 0.30 even ± 0.04VT.Average sub-threshold slope is 62 ± 1mV/ logarithmic scales.Two-way grid voltage in transmission characteristic
Threshold voltage of the scanning display less than 10mV lags.Recessed gate transistor and the flat grate with identical source and drain spacing (Lsd=11 μm)
Transistor has similar conducting resistance (Ron=10 Ω mm).Both recessed gate transistor peace gate transistors it is relatively low
Maximum drain current is due to the larger grid length and grid source distance, relatively low 2DEG density (7.1 of unoptimizable ohm contact
×1012) and higher contact resistance (1.2 Ω mm) cm-2.
Fig. 6 A show another multilayer epitaxial structure 600 of " bilayer " barrier structure 40 shown in further extension bitmap 4.
Fig. 6 B show another multilayer epitaxial structure 650, it, which has, is arranged on the other optional wall 632 with deflection layer 630.
In addition to semiconductor structure 40, semiconductor structure 600 and semiconductor structure 650 may be used to manufacture and have not
Same threshold voltage (VT) polytype transistor.The threshold voltage of transistor is that transistor is changed into turning off shape from conducting state
The grid voltage that state is passed through, vice versa.Semiconductor structure 600 can include substrate layer 602, cushion 604, channel layer
606th, band deflection layer 630 and cap rock 608.Substrate layer 602, cushion 604, channel layer 606 and with each layer in deflection layer 630
Can the embodiment according to Figure 1A to Fig. 1 D, Fig. 2A to Fig. 3 D, Fig. 3 A to Fig. 3 D and Fig. 4 respectively description, using with
Substrate layer 2, cushion 4, channel layer 6 are formed with the similar material of deflection layer 32 and technique.Cap rock 608 can be according to Figure 1A
To the description of the embodiment shown in Fig. 1 D, Fig. 2A to Fig. 3 D and Fig. 4, using similar to barrier layer 8,8a, 8b or barrier layer 28
Material and technique are formed.For example, each layer or sublayer shown in Fig. 6 A can include III-N materials BwAlxInyGazN。
Instead of upper barrier layer and lower barrierlayer pair, epitaxial structure 600 includes cap rock 608, and it is optional that cap rock 608 includes more of n
The sublayer of etching is selected, such as with thickness t1Sublayer 611, there is thickness t2Sublayer 612, there is thickness tn-1Sublayer 618
With with thickness tnSublayer 619, wherein according to the present invention each embodiment, n may be greater than or any even number equal to 2 or
Odd number.For example, the multilayer semiconductor structure 600 of the cap rock 608 with n=4 sublayer and optional carrier donor layer is Fig. 4 institutes
The illustrative semiconductor structure 40 shown.Thickness t1, t2..., tnCan between 2 angstroms and 500 nanometers, and the present invention it is each
It can be the same or different in embodiment.For example, tnThe gross thickness of every other sublayer can be greater than or equal to.At another
In example, all odd number or odd number sublayers can grow into first thickness, and all even numbers or even number sublayer can grow into
Two thickness.
In certain embodiments, each i-th sublayer (1≤i<N) it is that certain etching technique can be used relative to the of lower section
(i+1) sublayer is etched selectively to, therefore (i+1) sublayer of lower section can be as the i-th sublayer under given etching technique
Etching stopping layer.N-th sublayer, which can also be, deflection layer 630, wall 632 or to be set directly at the n-th sublayer relative to band
Etch lower section and/or any layer-selective for being contacted with the n-th sublayer.Wall 632 may or may not be can be
Selectively etched with the upside of deflection layer 630.In certain embodiments, each sublayer is that such as dry etching, wet method can be used
Etching or certain etching technique of the combination of dry etching and wet etching, select relative to both top sublayer and lower section sublayer
Etch to property.For example, selectively etchable sublayer can be divided into two types.Counted from the first sublayer 611 all strange
Number sublayers can be by the material that can be etched selectively to by the first etching technique of such as dry etching relative to even number sublayer
Formed, and all even number sublayers counted from the second sublayer 612 can be by that can pass through the second etching technique of such as wet etching
The material being etched selectively to relative to odd number sublayer is formed, and vice versa.N-th sublayer can also be usable dry etching work
Skill, wet etching process or its combination, relative to band deflection layer 630, wall 632 or be set directly at below the n-th sublayer and/
Or any layer-selective for being contacted with the n-th sublayer etch.N-th sublayer can be etched with speed more faster than the layer of lower section,
And the selectivity of etch process can be more than 3:1 so that the speed that the layer that the speed of the n-th sublayer etching is more than lower section etches
Three times.Wall 632 may or may not be selectively to be etched in sublayer 619 and/or with the upside of deflection layer 630.
May or may not be to be etched selectively in sublayer 619 and/or the upside of wall 632 with deflection layer 630.It is each strange
Number sublayer can have identical structure, composition and/or thickness.Alternatively, each odd number sublayer can have different structures, group
Into and/or thickness.Similarly, each even number sublayer can have identical structure, composition and/or thickness, or different structures,
Composition and/or thickness.In other other embodiment, each sublayer can be used one or more etching techniques opposite
It is etched selectively in the selection subsets of every other sublayer.For example, in certain embodiments, selectively etchable sublayer
Three types can be categorized as, wherein every three Seed Layer repeats each type, and each type is that one or more can be used
What etching technique was etched selectively in other two types.
More specifically, as discussed on Figure 1A, can be by making sub-layer material in the group of two or more types
Replace between to realize the selectively etchable property of the sublayer in cap rock 608.In certain embodiments, from the first sublayer 611
Count all odd number sublayers can include or comprising can in dry method etch technology selective etch semi-conducting material, it is all
Such as GaN, or another nitride semi-conductor material BwAlxInyGazN, wherein w, x, y and z each have (0 between 0 and 1
≤ w, x, y, z≤1) desired value, and form so that nitride semi-conductor material dry etching can be used optionally to lose
Carve.In one example, odd number sublayer can be by semi-conducting material BwAlxInyGazN is formed, and wherein x is less than 0.25.In difference
Embodiment in, w, x, y can be added equal to 1 or not equal to 1 with the value of z.In certain embodiments, odd number sublayer can be by half
Conductor materials A lxInyGazN is formed, wherein x, the desired value of y and z each with (0≤x, y, z≤1) between 0 and 1, and its
Middle x, y can be added equal to 1 or not equal to 1 with z.Similarly, all even number sublayers counted from the second sublayer 612 can include
Or comprising can in wet etching process selective etch semi-conducting material, such as AlN, or another nitride semi-conductor material
BwAlxInyGazN, wherein w, x, y and z each have the desired value between 0 and 1 (including) (0≤w, x, y, z≤1), and should
Composition is so that wet etching process can be used to be etched selectively in nitride semi-conductor material.The value of w, x, y and z can be added
Equal to 1 or not equal to 1.In one example, even number sublayer can be by semi-conducting material BwAlxInyGazN is formed, and wherein x is more than
0.5.In certain embodiments, even number sublayer can be by semi-conducting material AlxInyGazN is formed, wherein x, and y and z each have 0
The desired value of (0≤x, y, z≤1) between 1, and wherein x, y can be added equal to 1 or not equal to 1 with z.In these implementations
In example, at least one in selectively etchable sublayer can have so that the easier non-zero Ga contents (0 of epitaxial process
<z≤1)., can when successive, the adjacent or continuous sublayer of cap rock 608 has the alternate material composition between GaN and AlN
To carry out dry etching GaN without etching AlN using fluorine based chemistry product, and wet method can be carried out using tetramethylammonium hydroxide (TMAH)
AlN is etched without etching GaN.In certain embodiments, odd-level can include or comprising can be selected in wet etching process
Property etching semi-conducting material, such as AlN, and even level can include or comprising can in dry method etch technology selective etch
Semi-conducting material, such as GaN.
B is referred to hereinwAlxInyGazN。“BwAlxInyGazN materials " or " III-N materials " refer to nitride and
One or more semi-conducting materials in boron, aluminium, indium and gallium.AlxInyGazN materials are the wherein B of w=0wAlxInyGazN materials
Material.For example, BwAlxInyGazThe example of N materials include but not limited to GaN, AlN, AlGaN, AlInGaN, InGaN and
BalInGaN、Al0.15Ga0.85N and Al0.65Ga0.35N。BwAlxInyGazN materials can include except nitride, boron, aluminium, indium and/
Or the other materials outside gallium.For example, BwAlxInyGazN materials can be adulterated with suitable dopant, such as silicon or germanium.
In certain embodiments, the selectively etchable property of the sublayer in cap rock 608 is by making adjacent or successive sublayer
Aluminium content or composition replace between of a relatively high value or percentage and relatively low value or percentage to realize.Change sentence
Talk about, can be by replacing or adjusting as described above material B between light Al and the sublayer of richness AlwAlxInyGazN or
AlxInyGazThe value of the x of N realizes selectively etchable property.In one example, the successive or adjacent sublayers of cap rock 608 can be with
With less than 0.5 (including) and being more than for 0.5 (not including), less than 0.5 (not including) with being more than 0.5 (including), or less than 0.5
(not including) and more than alternate A1 contents between 0.5 (not including).In other instances, the successive or adjacent son of cap rock 608
Layer can have less than 0.25 with more than 0.5, less than 0.35 with more than 0.5, or less than 0.35 with (including or not more than 0.65
Comprising) between alternate Al content.In certain embodiments, in multiple selectively etchable sublayers it is at least one have be more than
0.5 Al content.In addition, at least one in selectively etchable sublayer can have non-zero Ga contents (0<z≤1).Moreover,
B, Al, In and Ga composition in each type of sublayer may be not necessarily identical.For example, when n is odd number, the first sublayer 611
There can be x=0.1 and x=0.2 respectively with the n-th sublayer 619, and the second layer 612 and (n-1) sublayer 618 can have respectively
There are x=0.6 and x=0.7.Similarly, when n is even number, the first sublayer 611 and (n-1) sublayer 618 can have x respectively
=0.1 and x=0.2, and the second sublayer 612 and the n-th sublayer 619 can have x=0.6 and x=0.7 respectively.
In fig. 6b, including optional wall 632.As in multilayer semiconductor structure 600 shown in fig. 6,
The each layer or sublayer of multilayer semiconductor structure 650, including optional wall 632, can include III-N materials
BwAlxInyGazN.For example, wall 632 can include BwInyGazThe III-N materials of zero Al content of N forms, including such as
The material of GaN and InGaN etc.Wall 632 can also be that N-shaped adulterates.In certain embodiments, band deflection layer 630 can
With the channel layer 606 with than lower section and the conduction band edge of 632 broader band gap of the wall of top or higher.In addition, interval
Layer 632 can have the band gap more narrower than immediately above sublayer 619 or lower conduction band edge.The narrower wall of band gap makes
It is negative to obtain wall and the net polarization charge with the interface between deflection layer, because the polarization of wall is less than with deflection layer
Polarization, so that threshold value electricity when helping to improve the sandwich construction 650 used in scene effect transistor with wall 632
Pressure.In certain embodiments, the one or more layers or sublayer shown in Fig. 6 B can include III-N materials, such as GaN,
AlN, AlGaN, InAlN and AlInGaN.For example, channel layer 606 can include GaN, band deflection layer 630 can include AlGaN,
Wall 632 can include GaN, and cap rock 606 can include the alternating layer of GaN and AlN.In certain embodiments, band deflection layer
630 can include the III-N materials with non-zero Al content.In certain embodiments, band deflection layer 630 can include III-N
Materials A lxInyGazN, wherein x+y+z=1,0≤x≤1,0≤y≤1 and 0≤z≤1.Band deflection layer in yet other embodiments,
630 can include III-N materials As lxGazN, wherein x+z=1,0.05<X≤0.4 and 0.6≤z<0.95.
In addition, the optional wall 632 shown in Fig. 6 B can have less than or equal to 20nm and/or be greater than or equal to
The thickness of 0.2nm.In various embodiments, layer or the thickness of sublayer can refer on the upper interface of layer or sublayer and lower interface
Average, the maximum or intermediate vertical distance measured between point.
Fig. 7 shows non-restrictive illustrative structure 700, and it includes using with according to some technologies described herein production
The epitaxial structure 650 shown in epitaxial structure 600 or Fig. 6 B shown in Fig. 6 A of raw gate recess, produce on a common substrate
Raw two kinds of transistor.More specifically, semiconductor structure 700 includes two transistors 710 and 720.Transistor 710
Be grid it is recessed and including with through whole cap rock 608 gate recess depth 713 grid 712.Transistor 720 has
There is planar gate.In certain embodiments, grid 712 can by the appropriate subset of selectively etchable sublayer and recessed, because
This is as shown in fig. 7, not fully remove cap rock 608 to form grid 712.
Similar to the exemplary crystal pipe shown in Fig. 5, face when the vertical thickness between gate recess and channel layer 606 is less than
During boundary's thickness, normally-off E mode transistors are formed with positive threshold voltage VT1.On the other hand, planar transistor 720 is that have negative threshold
Threshold voltage VT2Open type D mode transistor.In general, transistor threshold voltage monotonously depends on gate recess depth or in grid
The layer and/or the quantity of sublayer etched under pole, wherein dependence can be linear or nonlinear.Threshold voltage also depends on
In the layer of etching and/or the material type of sublayer and composition.For example, although alternate Al content realizes a sublayer another
Selectively etchable property on the upside of sublayer, but the higher average Al content of cap rock 608 would generally negatively be moved and made on it
The threshold voltage for the transistor made.Therefore, desired threshold voltage is given, when determining corresponding gate recess depth, can be examined
Consider the etching selectivity between the different semi-conducting materials for each sublayer.On the other hand, once grown sublayer, it is possible to
Etch depth is controlled with discrete step-length exactly, to reach or close to desired threshold voltage.
E/D Mode integratings shown in Fig. 7 can provide larger threshold voltage difference between two kinds of transistor.
In some embodiments, the threshold voltage difference between two kinds of transistor can be up to 35V.In certain embodiments, two
Transistor may each be E mode transistors, have different positive threshold voltages, or two transistors may each be D type crystal
Pipe, has different negative threshold voltages.In certain embodiments, VT1And VT2Scope that can respectively between -10V and+3V
It is interior.In certain embodiments, a part for optional wall 632 can be removed, whole walls 632, one with deflection layer 630
Partly and/or all with deflection layer 630 further to increase gate recess depth 713, with the higher threshold voltage V of realizationT1.Change
Sentence is talked about, and the bottom for the gate recess of transistor 710 can be in appointing with deflection layer 630, wall 632 or cap rock 608
Within what sublayer or on.
In order to form the depression of such as gate recess of transistor 710 etc, can be limited using suitable mask process
Surely the region to be etched.The first etch process can be performed to select with material relative to the second selectively etchable layer 612
Property etching the first selectively etchable layer 611 material.The selectivity of the etch process used in the first etching step can be with
More than one so that the first selectively etchable layer 611 is with than the 612 faster speed etching of the second selectively etchable layer.One
In a little embodiments, the selectivity of the etch process used in the first etching step can be more than 3:1 so that first is alternative
Etching layer 611 is etched with the speed of the three times more than the second selectively etchable 612 etch-rate of layer.First etching technique can be with
Including dry etch technique (such as dry plasma etch or reactive ion etching (RIE)).If the first alternative erosion
Carving layer 611 includes GaN, then can use the etch process based on fluorine.Second selectively etchable sublayer 612 may be used as etching
Stop-layer, stops dry method etch technology with surface on it.Dry method etch technology may damage the second selectively etchable sublayer
612 upper surface, so as to produce damaged zone.However, in certain embodiments, dry method etch technology may not produce any aobvious
The damage of work.
Next, the second etching step can be performed using the second etching technique, with by the first etching step
By removing the region of the first selectively etchable sublayer 611 the second selectively etchable sublayer is removed and the window formed
612 part.In certain embodiments, the etch process used in the second etching step can second can relative to covering
Selective etch sublayer 612 and the layer that can be contacted with the second selectively etchable sublayer 612, such as the first alternative erosion
Triplet layer 611, carrys out the selectively etchable sublayer 612 of selective etch second.In certain embodiments, in the second etching step
The etch process used can be relative to the second selectively etchable son that can be contacted with the second selectively etchable sublayer 612
The layer of the lower section of layer 612, such as the 3rd selectively etchable sublayer and/or wall 632 or with deflection layer 630 come optionally
Etch the second selectively etchable sublayer 612.Second selectively etchable sublayer 612 is relative to the first selectively etchable sublayer
611 and/or the 3rd selective etch sublayer, wall 632 or the etching selectivity with deflection layer 630 can be more than 1 so that the
The etch-rate of two selectively etchable sublayers 612 be more than such as first or the 3rd selectively etchable sublayer etch-rate.
In certain embodiments, 3 can be selectively more than:1 so that the second selectively etchable sublayer 612 is with more than first or the 3rd
The speed etching of selectively etchable sublayer three times.In certain embodiments, the etching technique used in the second etching step
It can be wet etch technique.
Once gate recess is formed by the first selectively etchable 611 and second selectively etchable sublayer 612 of sublayer,
The first and second etching techniques, or dry etching as described above and wet etching process can be then iteratively performed, to remove
Successive or adjacent selectively etchable sublayer, until reaching cup depth 713.Remove the last of a part for sublayer 619
Etching step can be dry etching or wet etching.In example arrangement 700, gate recess depth 713 is about thickness
Spend t1, t2..., and tnSummation.Can use be similar to shown in Fig. 1 D be used for deposit gate-dielectric 18 and grid 20
The technique of technique, forms gate-dielectric 714 and grid 712 in the gate recess for transistor 710 of gained.For flat
Gate transistor 720, gate-dielectric 724 and grid 722 can be with the gate-dielectrics 714 and grid 712 of transistor 710 at the same time
Formed or be formed separately with gate-dielectric 714 and grid 712.Source contact 716 and 726 and drain contact 718 and 728
It can be formed before or after it.
Fig. 8 shows another exemplary structure 800, and it includes using in the epitaxial structure 600 or Fig. 6 B shown in Fig. 6 A
The two kinds of transistor 810 and 820 that shown epitaxial structure 650 produces on the same substrate.810 and 820 quilt of transistor
The recessed different depth of grid and manufactured according to technique described herein.In this example, there is the crystalline substance of deeper gate recess
Body pipe 810 is with the threshold voltage V corrected than the transistor 820 with shallower gate recessT.Due to transistor threshold voltage VT
Value monotonously depend on gate recess depth, therefore change side's etching or the quantity of recessed layer and/or sublayer under the gate
Allow directly and precisely to control achievable threshold voltage.Further, since each selectively etchable sublayer can include list
Layer III-N atoms, therefore cup depth can be controlled with the spaced discrete of as low as 0.2nm to 0.5nm.Gate recess can stop
Only in any selectively etchable sublayer, wall 632, optional with deflection layer 630 or the one or more being not shown here
Within carrier donor layer or on.In this example, the gate recess of transistor 810 and 820 is in two different sublayers
Stop, and the two sublayers there may or may not be identical material to form.Gate-dielectric 814 and 824 and grid
Contact 812 and 822 is deposited on the upside of etching region.
In various embodiments, can with or without in the case of concave, and before gate regions are formed or
Ohm contact is made afterwards, to adapt to the consideration of other techniques such as heat budget, ohm contact performance and process complexity.Scheming
In example shown in 8, the ohm contact 816 and 818 of transistor 810 is made in the case of formation ohm is concave in cap rock 608.
Source electrode 816 and drain electrode 818 it is recessed run through whole cap rock, have identical ohm cup depth with simplify manufacture.It is commonly used for
Ohm depression of single transistor may or may not have identical cup depth.In certain embodiments, ohm contact can
With with the thickness between 1nm and 10,000nm.Moreover, although the ohm contact in Fig. 8 is rectangle, but they can also be
Alloy, wherein contact is without regular shape.
In order to manufacture the structure 800 shown in Fig. 8, the exposed epitaxial surface of sandwich construction 650 can be first with such as
SiO2Or the dielectric layer covering of SiN.The gate openings of transistor 810 can be limited by using photoetching, and in deposition
It is etched in dielectric.After removing photoresist, it can perform based on the dry etching of fluorine to remove light Al layers and stop at
In rich Al sublayers, and rich Al sublayers can be removed using TMAH or other alkaline solutions and are stopped on light Al layers.It can weigh
Multiple selective etch, the desired cup depth until reaching grid 812.First grid is recessed once being formed, and total can
It is usually identical with the first dielectric layer used before to be covered with another dielectric layer, and photoetching can be performed, then carry out light
Photoresist removes and the iteration selective etch of sublayer, the desired cup depth until reaching grid 822.Forming two grids
After depression, the gate contacts material of gate-dielectric and such as gate metal etc can be deposited to cover total.So
It is etched afterwards by lithographic definition gate electrode, the wherein grid metal outside gate electrode area.In certain embodiments, by using
Deposited selected from least one material of Ti, Mo, W, Ta, Pt, Ni, Al, Cu, polycrystalline Si, TiN, WN, TaN, TiW and silicide
Gate material is simultaneously then peeled off to form gate electrode.In certain embodiments, the gate electrode for different crystal pipe is by difference
Material be made.The another way of recessed grid 812 and grid 822 is to limit two gate openings at the same time, with two grid
It is etched selectively in the opening of pole, until reaching the first less gate depth, and is further selected in one of gate openings
Etch until reaching the second larger gate depth to property.
For ohm contact, can be formed before gate-dielectric and gate metal deposition for contact 816 and 818
Ohm depression.For example, if cup depth is identical, ohm depression can be formed together with one of gate recess or at the same time.Separately
Outside, ohmic metal deposition, figure can be performed before or after gate-dielectric and gate metal deposition or gate electrode are formed
Case and optional thermal anneal step, to allow to optimize heat budget and process complexity.In certain embodiments, in gate electrode and
Before ohm contact is deposited or formed, recessed structure is subjected to thermal annealing at a temperature of less than 1500 DEG C.In certain embodiments,
Deposition of metal is on the upside of ohm contact and the transistor formed, for interconnecting ohm contact, or as managing crystal
The field plate of electric field in pipe.
Fig. 9 shows two that include the selectively etchable sublayer with doping according to some embodiments of the present invention
The example arrangement 900 of recessed gate transistor 910 and 920.In this example, one piece between sublayer 611 and 617 (not including) or
One group of successive, adjacent or continuous sublayer is doped.Doping can carry out during epitaxial growth.Recess etch it
Afterwards, doped region is formed between grid and source electrode and between grid and drain electrode outside grid and ohm depression.The present invention's
In various embodiments, any subset of continuous or discrete selectively etchable sublayer can be doped with to channel layer
Supply carrier.Depending on gate recess depth, it can also adulterate and not etch sublayer below one or two recessed grid.Often
A doped region can be polarization doping, or can include the dopant of such as n-type dopant or p-type dopant.Each mix
Miscellaneous selectively etchable sublayer or each doped region can have any suitable doping concentration and distribution.For example, can be
The lower surface of sublayer, the upper surface of sublayer provide dopant through sublayer.Dopant profiles can be uniform or non-uniform.
In certain embodiments, at least 10 can be used16cm-3Doping concentration.In certain embodiments, single sublayer can be run through
Or successive sub-layers block uses increment dopant profiles.In order to adulterate one or more sublayers, any suitable doping can be used
Technology, such as injects or spreads.In one example, can the formation of cap rock 608 or growth period one group is selected can
The etchable sublayer of selectivity is etched.In certain embodiments, doping type can be with the class types of carrier in channel region
Type is identical.For example, the doping type in doped region shown in Fig. 9 can be N-shaped for n-channel transistor, for p-channel
Transistor can be p-type.In certain embodiments, doped region can be high doped.In certain embodiments, Ke Yi
The top of cap rock 608 deposits other carrier donor layer further below, all layers 22 as shown in Figure 2 A.In some implementations
, can be in the top deposit passivation layer of cap rock 608 in example, wherein passivating material can be silicon nitride, silica, aluminium oxide, nitrogen
Change aluminium, polyimides, benzocyclobutene, silicon oxynitride, aluminium oxynitride, polytetrafluoroethylene (PTFE) and phosphosilicate glass.
Figure 10 shows another example arrangement 1000 according to some embodiments of the present invention, and it includes two to be respectively provided with
The concave recessed gate transistor of ohm.In this specific example, the ohm contact 1016 and 1018 of transistor 1010 is arranged on tool
There is the concave upside of first pair of ohm of a certain depth and covered, and the ohm contact 1026 and 1028 of transistor 1020 is set
Put in the concave upside of second pair of ohm with same depth and covered.Recessed grid 1012 and 1022 is arranged on grid
The upside of dielectric 1014 and 1024, gate-dielectric 1014 and 1024 are successively set on the upper of the gate recess with different depth
Side is simultaneously covered.In various embodiments, each ohmic region can it is recessed with reach channel layer 606, band deflection layer 630,
Interlayer 632 or selectively etchable sublayer.Ohm depression for contact 1016,1018,1026 and 1028 can be formed at the same time,
Because they have identical depth.Transistor 1010 and 1020 can be E patterns, or one can be E patterns, and another
One can be D mode.
Relative to structure 700 in such as Fig. 7 including no gate recess or the concave planar transistor of ohm etc
Design, use one with 1000 etc structure in 900 and Figure 10 in the concave such as Fig. 9 of gate recess and ohm
A advantage is to make the thin slice electricity in these regions by keeping the maximum epitaxy layer thickness of the access areas between grid and S/D
Sub- density maximizes, and minimizes the sheet resistance in these regions.In addition, the top surface by keeping these regions
Away from raceway groove, the capture effect in these access areas can be mitigated.
Although only discussing two kinds of transistor in the illustrated examples shown in Fig. 7, Fig. 8, Fig. 9 and Figure 10,
In other embodiments, sandwich construction 600 or 650 is configurable to the transistor for including two or more types, every kind of transistor
With different threshold voltages.Accordingly, it may be desirable at least three selectively etchable sublayers are to realize different threshold value electricity
Pressure.
Although Fig. 7, Fig. 8, Fig. 9 and Figure 10 are provided for by the two kinds of transistor collection with different threshold voltages
, can be on the same substrate into one into the illustrated examples of semiconductor structure on a common substrate, but in certain embodiments
Step integrates other devices.Exemplary means include diode, capacitor, memory, memristor, optical modulator, waveguide, shine
Diode, photo-coupler, detector, transformer, resistor and inductor.In certain embodiments, semiconductor described herein
Structure is used for various applications, including analog circuit, mixed signal circuit, gate driving circuit and digital control circuit.
Figure 11 is shown forms concave illustrative processes according to manufacturing technology as described herein on semiconductor structure
Flow.The key feature of the recess etch process discussed is that etching sublayer may be selected until reaching desired depression in gradual remove
Depth.For example, in order to form depression on all 600 etc semiconductor structures as shown in Figure 6A, photoetching can be first carried out
To limit recessed openings.Next, two or more etching techniques can be iteratively applied to remove odd and even number sublayer,
Until reaching desired cup depth.Any successive, adjacent or continuous sublayer block can remove by this way.
More specifically, Figure 11 is shown forms concave technological process, wherein odd number on such as 600 semiconductor structure
Sublayer is light aluminium, and even number sublayer is rich aluminium.For example, odd number or odd number sublayer can be by the first semi-conducting materials
A1x1Iny1Gaz1N is formed, wherein x1, y1And z1Each there is (0≤x between 0 and 11, y1, and z1≤ 1) desired value, and x1
≤0.35；Even number or even number sublayer can be by the second semi-conducting material Alx2Iny2Gaz2N is formed, wherein x2, y2And z2Each tool
There is between 0 and 1 (0≤x2, y2, and z2≤ 1) desired value, and x2>0.5.Furthermore, it is assumed that in this example, desired depression
Depth covers the selectively etchable sublayer of even number sum.After initialization 1110, light is performed in step 1120 first
Carve.Specifically, first with the epitaxial surface of dielectric layer covered structure 600, and recessed openings are limited.Etch in the dielectric recessed
Opening is fallen into, then removes photoresist.Next, such as dry etching and wet can be iteratively applied by step 1140 and 1150
Two kinds of etching techniques of method etching, to remove odd and even number sublayer, until reaching desired cup depth in step 1160.
In step 1140, using dry etching to remove light Al sublayers and stop in rich Al sublayers；In step 1150, application is wet
Method is etched to remove rich Al sublayers and stop in light Al sublayers.Once reaching desired cup depth, then whole technique is in step
Stop at rapid 1190.If it is desire to cup depth cover the optional etching sublayer of odd number sum, then technological process 1100
Can correspondingly it modify so that the sum of selective etching step is also odd number.
Figure 12 is shown according to manufacturing technology as described herein to form the structure for including two kinds of recessed gate transistor
Exemplary process flow.In this example, distinguished in step 1220 and 1230 by the depression formation process shown in Figure 11
Form two gate recess.Then gate-dielectric and gate contacts can be deposited in step 1240 and 1250.In step
Formed in 1270 before a pair of of ohm depression, can be to be that gate stack deposits protective layer in step 1260.Although do not show herein
Go out, but further can form second pair of ohm at the same time with first pair of ohm depression and be recessed, if two pairs have identical depression
If depth；Or formed after first pair of ohm depression, if two pairs have different cup depths.Then in step
Deposit ohmic contact in rapid 1280.Whole technique terminates at step 1290.
Figure 13 is shown according to some embodiments of the present invention in the multilayer semiconductor with selectively etchable sublayer
The illustrative structures 1300 with two kinds of transistors of D mode and E patterns manufactured on structure.Figure 13 is also shown accordingly with logarithmic scale
Transfer curve or ID-VGSCharacteristic 1350.In structure 1300, there is the concave flat grid type D mode transistor of ohm to be constructed
In the row of top, and such as transistor 810,910,1010 and 1020 etc has the concave recessed grid-type E mode transistors of ohm
It is built into bottom row, with D mode crystal tube side-by-side, whole is on a common substrate.Grid and ohm depression have about 30nm
Depth, and can use such as on the described appropriate photoetching of Figure 11 and Figure 12 and gradual etching step simultaneously or
Concurrently formed.By by threshold voltage VTIt is defined as drain current IDFor 1e-3mA/mm when gate source voltage VGS, for D- moulds
The threshold voltage V of formula transistor acquisition -4.2VT, for the threshold voltage V of E mode transistors acquisition 0.5VT.As it was previously stated, threshold
Threshold voltage is that transistor becomes an OFF state passed through grid voltage from conducting state, and vice versa.
Show in figures 14 and 15 concave integrated with or without grid as shown in Figure 7 to 10 or ohm
Illustrative DC (direct current) characteristic of E/D mode transistors.Figure 14 shows the approximation of integrated E/D transistors on the same substrate
ID-VGSThe curve 1400 of characteristic.Drain current IDRepresented with arbitrary unit, and drain-source voltage is consolidated for each type of transistor
It is scheduled on 5V and 0.1V.The threshold voltage of two distinct types of transistor it is expected on the occasion of or negative range in.Similarly, scheme
15 show the I for representing integrated E/D transistors on the same substrateD-VGSThe curve 1500 and 1550 of characteristic.Drain current ID
Represented with arbitrary unit, and VGS- 10V is changed to from -1V with the step-length of -1V for D mode transistor, for E mode transistors
0V is changed to from 9V with the step-length of -1V.
As another example of integrated device that can be using multilayer semiconductor structure disclosed herein to realize, Figure 16 shows
Flat grate according to an embodiment of the invention, normally opened, D mode transistor 1600 are gone out, it has interval using shown in Fig. 6 B
The sandwich construction 650 of layer 632.Transistor 1600, which has, to be arranged on the top of gate dielectric 1614 and is located at recessed ohm contact
Planar gate 1612 between 1616 and 1618.
In the particular example, include special carrier donor layer 610, and carrier donor layer in sandwich construction
610 are formed in the upside of top sub-layer 611 of cap rock 608.However, in other cases, carrier donor layer 610 can be optional
And can be omitted.In addition, structure as described herein and technology are unrestricted in this regard, and one or more carriers
Donor layer, such as carrier donor layer 610, can be formed in cap rock 608, be inserted between selectively etchable sublayer, or
Person is in another location.In certain embodiments, carrier donor layer 610 can be formed by the material identical with top sub-layer 611.
Although in addition, be not shown in figure 16, when being removed there are a part for gate recess and carrier donor layer 610,
The reaming part of carrier donor layer 610 can supply carrier to the raceway groove 606 substantially under the gate outside square region.
In addition, although showing two selectively etchable sublayers 611 and 619 in this example for illustrative purposes,
But in various embodiments, there may be the selectively etchable sublayer of any non-zero quantity, wherein each sublayer can close to
Below or above sublayer upside or selectively etched relative to it, or can be selected in the upside of both above and below sublayers
Etch to selecting property.As discussed on Fig. 6 B, the top sublayer 619 placed close to wall 632 can be on wall 632
Side is etched selectively to relative to wall 632, and wherein wall 632 is used as etching stopping layer during manufacture.Wall
632 can have than with the narrower band gap of deflection layer 630 or lower conduction band edge.In certain embodiments, wall 632 has
There is the band gap identical with channel layer 606.It is in addition, selectively etchable through carrier donor layer 610 and one or more herein
Sublayer forms ohm depression, therefore the bottom of ohm contact 1616 and 1618 is placed on wall 632.In different embodiments
In, the bottom of each in ohm contact 1616 and 1618 can be located at cap rock 608, wall 632, band deflection layer 630 or
Within any selectively etchable sublayer of channel layer 606 or on.
In order to manufacture transistor 1600, can perform on the 710 and 720 described example of transistor shown in Fig. 7
Property technique, may be according to the technological process shown in Figure 11 and Figure 12.In addition, by using selectively etchable layer and sublayer,
Such as wall 632, conductivity gate contact and ohm contact, such as 1616 and 1618, can be made without gold and therefore
It can be reproduced with high yield on extensive chip.Most of low resistance ohmic contacts in III-N devices are made using golden (Au)
It is top layer to reduce the sheet resistance below ohm contact area, and oxidation is reduced during high-temperature annealing process.Based on Au's
Schottky contact also due to its low contact resistance and be usually used in III-N semiconductor device.However, in such as CMOS wafer factory
The presence of Au can cause serious pollution problem in silicon manufacturing facility, because gold is easy to be diffused into silicon.In order to preferably control
Manufacture without golden ohm contact 1616 and 1618 in transistor 1600 processed, can be optionally to carrier donor layer 610 and lid
The sublayer of layer 608 carries out wet etching and/or dry etching, in order to substantially reduce wall in a manner of simply and accurately
Etch damage or no any etch damage at 632.The defect-free surface of wall 632 then can be with ohmic metal alloy
Change to obtain the ohm contact with low contact resistance.Exemplary ohmic metal include but not limited to Ti, TiN, Al, Ta, TaN,
Mo, W, WN, Pt, Ni and Cu.In certain embodiments, ohm contact can have the thickness between 1nm and 10,000mm.
Figure 17 shows exemplary recessed grid according to an embodiment of the invention, Chang Guan, E mode transistor 1700, it makes
With the epitaxial structure 650 shown in Fig. 6 B, there is wall 632.Transistor 1700, which has, is arranged on the top of gate dielectric 1714
And the recessed grid 1712 between depression ohm contact 1716 and 1718.In the specific example, for grid 1712
The bottom of gate recess is located on wall 632, and between the concave bottom of ohm for being used for ohm contact 1716 and 1718 is located at
In interlayer 632.In various embodiments, grid and ohm depression can each have different depth, and grid and ohm
Concave bottom can be located at cap rock 608, wall 632, any selectively etchable with deflection layer 630 or channel layer 606
Within sublayer or on.Equally in this specific example, grid 1712 further extends over gate recess regions to form grid
Pole field plate 1713, grid field plate 1713 can help to reduce maximum field, realize desired electric field distribution on raceway groove, and increase
The breakdown voltage of III-N transistors.Equally, although for illustrative purposes show in this example two it is selectively etchable
Sublayer 611 and 619, but in various embodiments, there may be the selectively etchable sublayer of any non-zero quantity, wherein each
Sublayer can selectively be etched relative to adjacent below or above sublayer, or can be in both adjacent above and below sublayers
Upside is etched selectively to.Wall 632 is also used as etching stopping layer, and may or may not be can close to
Top sublayer 619 upside be etched selectively to.In addition, wall 632 can have it is more narrower than the band deflection layer 630 of lower section
Band gap or lower conduction band edge, and than top the narrower band gap of sublayer 619 or lower conduction band edge.
Figure 18 is the conduction band for showing the exemplary semiconductor structure according to an embodiment of the invention with wall
With the energy band diagram of valence band.In this illustrated examples, channel layer, band deflection layer and wall respectively include GaN, AlGaN and
GaN, and cap rock includes the sublayer of AlN and the sublayer of n-GaN.In general, can have than the channel layer of lower section and upper with deflection layer
The broader band gap of wall of side or the conduction band edge of higher.In addition, wall can be with than not only band deflection layer but also tightly
The adjacent narrower band gap of top sublayer or lower conduction band edge.The narrower wall of band gap cause wall with deflection layer it
Between the net polarization charge of interface be negative because the polarization of wall is less than the polarization with deflection layer, so as to help to improve
Threshold voltage when in scene effect transistor using this sandwich construction with wall.
Figure 19 shows exemplary integrated morphology 1900, and it includes using with wall 632 and according to described herein
Some technologies produce gate recess Fig. 6 B shown in epitaxial structure 650, produce on a common substrate it is two kinds of
Transistor.Semiconductor structure 1900 includes two transistors 1910 and 1920.Transistor 1910 has planar gate 1912.Crystal
Pipe 1920 is that grid is recessed and including with through carrier donor layer 610, cap rock 608, wall 632 and with deflection layer
The grid 1922 of 630 gate recess.Transistor 1910 and 1920 include respectively ohm contact to 1916,1918 and 1926,
1928.Ohm depression is formed in this example so that such ohm contact is positioned in wall 632.In different embodiments
In, grid and the concave bottom of ohm can be placed on cap rock 608, wall 632, times with deflection layer 630 or channel layer 606
Within what selectively etchable sublayer or on.Moreover, in such as 1900 integrated morphology, transistor can pass through table top
Etching, ion realize or both combination and it is electrically isolated from one.In certain embodiments, transistor 1910 is normally opened, has negative threshold
Threshold voltage, and transistor 1920 often closes, and has positive threshold voltage.
In addition to the transistor being discussed herein, disclosed multilayer semiconductor structure can also be applied to other integrators
Part.Figure 20 shows the exemplary Xiao Te of the epitaxial structure 650 according to an embodiment of the invention using shown in Fig. 6 B
The cross-sectional view of based diode 2000.In this example, the cathode 2016 for etching into wall 632 is schottky contact, is passed through
The anode 2012 that dielectric 2014 etches is ohm contact.Both it is used for the metal knot for biasing schottky diode device
Structure.
One is not meant in itself using the ordinal term such as " first ", " second ", " the 3rd " in the claims
Claim elements are dynamic relative to any priority of another claim elements, prior to property or order or execution method
The order of work, they are used only as marking, by a claim elements with specific names with same names (if
Not using ordinal term) another key element distinguish to distinguish these claim elements.
Moreover, wording as used herein and term are for purposes of description, and it is not considered as restricted.Use
" comprising ", "comprising" or " having ", " containing ", " being related to " and its modification be intended to items listed thereafter and its equivalent with
And sundry item.For example, be enumerated as " comprising ", "comprising" or " having ", "comprising", the device of " being related to " certain material, structure,
Equipment, layer or region mean at least to cover the material and any other element or material that may be present listed.Portion separates
The phrase " substantially by ... form " of putting property means mainly to include cited material, and does not exclude the presence of relatively small amount
Other materials, including there are dopant.
The various aspects of device described herein and technology can be used alone, and be applied in combination, or with retouching above
The various arrangements being not specifically discussed in embodiment described in stating use, therefore its application is not limited to explain in description above
The details and arrangement for the component stated or be shown in the drawings.For example, the aspect described in one embodiment can be with any
Mode is combined with the aspect described in other embodiment.In other words, although being described by reference to specific exemplary embodiment
The present invention, but it will be apparent that these embodiments can be carried out with various modifications and changed without departing from the wider of the present invention
General scope.Therefore, specification and drawings are considered as illustrative and not restrictive.To those skilled in the art
It is readily apparent that above-described embodiment is the single specific example widely invented, the present invention can have than being taught
Any odd number describes the scope of bigger.Without departing from the scope of the invention, many changes can be made in the de-scription.
Claims (20)
1. one kind is used for the multilayer semiconductor structure in group III-nitride (III-N) semiconductor devices, including：
Channel layer, including for providing the first III-N materials of conduction；
The band deflection layer being arranged on the channel layer, the band deflection layer include the 2nd III-N materials, and with than described
The broader band gap of channel layer；
The wall with deflection layer is arranged on, the wall includes the 3rd III-N materials, and with than the band
The narrower band gap of deflection layer；And
The cap rock being arranged on the wall, the cap rock include at least two sublayers,
Wherein each sublayer can be etched selectively to relative to adjacent above and below sublayer,
Wherein each sublayer includes III-N materials As lxInyGazN, wherein 0≤x≤1,0≤y≤1 and 0≤z≤1,
Sublayer described in wherein at least one has non-zero Ga contents, wherein 0<Z≤1, and
Wherein there is band gap more broader than the wall close to the top sublayer of the wall.
2. multilayer semiconductor structure according to claim 1, further comprises Ga polar surfaces.
3. multilayer semiconductor structure according to claim 1, wherein the thickness of the wall is less than or equal to 20nm, and
And it is greater than or equal to 0.2nm.
4. multilayer semiconductor structure according to claim 1, wherein the wall is N-shaped doping.
5. multilayer semiconductor structure according to claim 1, wherein the top sublayer close to the wall is can
It is etched selectively to using wet etching process on the upside of the wall.
6. multilayer semiconductor structure according to claim 1, wherein the top sublayer close to the wall is with big
It is etched in the high speed of the wall three times.
7. multilayer semiconductor structure according to claim 1, wherein the adjacent sublayers of the cap rock have less than 50%
(0≤x≤0.5) is with being more than 50% (0.5<X≤1) between alternate Al content.
8. multilayer semiconductor structure according to claim 1, wherein including the wall of the 3rd III-N materials
With zero Al content.
9. multilayer semiconductor structure according to claim 1, wherein the offset of the band comprising the 2nd III-N materials
Layer has non-zero Al content.
10. multilayer semiconductor structure according to claim 9, wherein the second III-N materials are AlxGazN, wherein x+
Z=1,0.05<X≤0.4 and 0.6≤z<0.95.
11. multilayer semiconductor structure according to claim 1,
Wherein described first III-N materials are GaN,
Wherein described second III-N materials are AlxInyGazN, wherein x+y+z=1,0<X≤1,0≤y≤1 and 0≤z≤1, and
And
Wherein described 3rd III-N materials are GaN.
12. multilayer semiconductor structure according to claim 1, wherein in the first, second, and third III-N materials
Each is selected from the group being made of GaN, AlN, AlGaN, InAlN and AlInGaN.
13. multilayer semiconductor structure according to claim 1, further comprises be arranged on the channel layer at least one
Carrier donor layer above point, to provide carrier to the channel layer.
14. multilayer semiconductor structure according to claim 13, wherein the carrier donor layer has at least 0.2nm's
Thickness and at least 1016cm-3Doping concentration.
15. multilayer semiconductor structure according to claim 1, further comprises：
Gate regions including the grid dielectric material being arranged on above at least a portion of the channel layer；And
A pair of of the ohm contact being arranged on outside the gate regions.
16. multilayer semiconductor structure according to claim 15, further comprises the gate recess in the gate regions, its
Described in grid dielectric material be arranged on the upside of the gate recess, and the bottom of wherein described gate recess is from by described
Channel layer, the sublayer composition with deflection layer, the wall and the cap rock group within the layer that selects or on.
17. multilayer semiconductor structure according to claim 16, further comprises：
It is arranged on above the gate recess and covers the gate contacts of the gate recess, and
It is arranged on the upside of the grid dielectric material, the gate field extension board outside the gate recess.
18. multilayer semiconductor structure according to claim 15, wherein each bottom of the pair of ohm contact from
Within the layer selected in the group being made of the channel layer, the sublayer with deflection layer, the wall and the cap rock
On or.
19. multilayer semiconductor structure according to claim 1, further comprises：
Anode region including the anode dielectric material being arranged on above at least a portion of the channel layer；And
The ohmic cathode electrode being arranged on outside the gate regions.
20. multilayer semiconductor structure according to claim 19, wherein the bottom of the ohmic cathode electrode is from by institute
State in the group of channel layer, the sublayer composition with deflection layer, the wall and the cap rock within the layer that selects or it
On.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562203438P | 2015-08-11 | 2015-08-11 | |
| US62/203,438 | 2015-08-11 | ||
| US15/094,985 US9502535B2 (en) | 2015-04-10 | 2016-04-08 | Semiconductor structure and etch technique for monolithic integration of III-N transistors |
| US15/094,985 | 2016-04-08 | ||
| PCT/US2016/046546 WO2017027704A1 (en) | 2015-08-11 | 2016-08-11 | Semiconductor structure with a spacer layer |
Publications (1)
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| CN107924939A true CN107924939A (en) | 2018-04-17 |
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| Country | Link |
|---|---|
| EP (1) | EP3335242A4 (en) |
| CN (1) | CN107924939A (en) |
| WO (1) | WO2017027704A1 (en) |
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| US20140306235A1 (en) * | 2013-04-16 | 2014-10-16 | Imec | Method for Producing a Semiconductor Device Comprising a Schottky Diode and a High Electron Mobility Transistor |
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Also Published As
| Publication number | Publication date |
|---|---|
| EP3335242A1 (en) | 2018-06-20 |
| EP3335242A4 (en) | 2019-04-10 |
| WO2017027704A1 (en) | 2017-02-16 |
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