CN107923856B - Non-visual grid for range-based real-time scanning electron microscope - Google Patents

Abstract

A technique for identifying non-visual defects, such as SEM non-visual defect SNV, includes: generating an image of a layer of a wafer; evaluating at least one attribute of the image using a classifier; and identifying the non-visual defect on the layer of the wafer. A controller may be configured to identify the non-visual defect using the classifier. The controller may communicate with a defect review tool, such as a Scanning Electron Microscope (SEM).

Description

Non-visual grid for range-based real-time scanning electron microscope

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims application on 5/8/2015 and assigned priority to indian provisional patent application No. 4069/CHE/2015 and application on 23/9/2015 and provisional patent application No. 62/222,647, 2015, the disclosure of which is hereby incorporated by reference.

Technical Field

The present invention relates to classification of defects, and more particularly, to classification of non-visual defects.

Background

Wafer inspection systems help semiconductor manufacturers increase and maintain Integrated Circuit (IC) chip yield by detecting defects that occur during the manufacturing process. One purpose of the detection system is to monitor whether the manufacturing process is in compliance with specifications. If the manufacturing process is outside of the established specifications, the inspection system indicates the problem and/or the source of the problem, which can then be resolved by the semiconductor manufacturer.

The development of the semiconductor manufacturing industry has placed increasing demands on yield management and, in particular, metrology and inspection systems. Critical dimensions are increasingly shrinking and wafer sizes are increasing. Economic factors drive the industry to reduce the time for achieving high yield, high value production. Thus, minimizing the total time from detecting yield problems to solving the problems determines the return on investment for the semiconductor manufacturer.

Prior techniques for classifying defects, including manual classification and automatic layer-based classification, involve excessive time and effort. As devices become more complex, manual classification of defects in semiconductor manufacturing facilities requires increasing time and effort. Even after a significant amount of time is spent classifying, defect classifications may remain inaccurate and inconsistent due to human error. Current techniques in the art for automatically classifying defects require many instances of the defect and sometimes also human resources for training the classifier. Furthermore, training classifiers for each defect type of each layer can be cumbersome, as the total number of classifiers to be trained will be the number of defect types multiplied by the number of layers.

Manual classification involves: each defect image is manually observed at multiple viewing angles, defect identification is performed with a set of known reference defect images, and a category code is manually assigned for each defect site. Manual classification of defects requires a significant amount of time to complete. This is again extremely expensive. Furthermore, using human judgment during classification can introduce inaccuracies and inconsistencies in the results.

Automatic layer-based classification involves custom classifiers built for each layer that separate all critical defect types present. The classifier can be established manually or automatically. Automatic classification on a layer basis implements the building of layer-specific custom classifiers. Training the classifiers for all layers requires a lot of resources like training data, human resources and time. For example, training the classifiers for each layer requires training data. The training data should have enough defect instances for each critical defect to be classified by the classifier. Some classifier building schemes used in the field require manual classifier building. This also leads to inconsistencies in the performance of the established classifiers due to inaccuracies in determining the best set of attributes for establishing the classifiers, along with the large time investment involved. Due to the large duplication in building classifiers for the same defect type across layers at a particular site and also across multiple customer sites, a significant amount of time is spent building, training, and maintaining classifiers.

Accordingly, there is a need for a system and technique that reduces the time and effort required to classify wafer defects.

Disclosure of Invention

In a first embodiment, a system is provided. The system comprises: a defect review tool; and a controller configured to communicate with the defect review tool. The defect review tool has an object stage configured to hold a wafer. The controller is configured to identify non-visual defects on a layer of the wafer using a classifier. The defect review tool may be a Scanning Electron Microscope (SEM). The non-visual defect may be an SEM non-visual defect (SNV).

The controller may include: a processor configured to communicate with the defect review tool; a storage device in electronic communication with the processor containing the classifier; and a communication port in electronic communication with the processor to communicate with the defect review tool.

The controller may identify non-visual defects by filtering at least one of topographical defects, intensity attributes, or energy attributes using the classifier.

In a second embodiment, a method is provided. The method comprises the following steps: generating an image of a layer on a wafer using a defect review tool; evaluating, using a processor, at least one attribute of the image with a classifier; and utilizing the classifier to identify non-visual defects on the layer of the wafer using the processor.

The method may further comprise: defining, using the processor, an upper limit and a lower limit for non-visual defects, wherein the non-visual defects identified are between the upper limit and the lower limit.

The classifier can be configured to filter topographical defects, intensity attributes, and/or energy attributes.

The sorter may be configured to be used on each layer of the wafer.

The generation may use a Scanning Electron Microscope (SEM). The non-visual defect may be an SEM non-visual defect (SNV).

The comparison and identification may be performed in real time with the generation.

Drawings

For a fuller understanding of the nature and objects of the present invention, reference should be made to the following detailed description taken together with the accompanying figures wherein:

FIG. 1 is a flow chart according to an embodiment of the present invention;

FIG. 2 is a graph showing exemplary upper and lower limits of scanning electron microscope non-visual (SNV) spread;

FIG. 3 is a schematic diagram of an exemplary SNV classifier; and

FIG. 4 is an embodiment of a defect review tool according to the present invention.

Detailed Description

Although claimed subject matter will be described in terms of particular embodiments, other embodiments, including embodiments that do not provide all of the advantages and features set forth herein, are also within the scope of the present disclosure. Various structural, logical, process step, and electrical changes may be made without departing from the scope of the present invention. The scope of the invention is, therefore, defined only by reference to the appended claims.

Scanning Electron Microscopy (SEM) non-visual (referred to as "SNV") defines a review site that is defective but does not contain any truly defined defects. A truly defined defect may be a damage on the wafer compared to the reference. For example, a truly defined defect may be a particle, scratch, or void. Thus, SNVs will have similar properties compared to their reference sites, which can make them difficult to identify manually. As disclosed herein, the defect attribute may be calculated after subtracting the reference image (i.e., defect-reference image) from the defect image. This results in common attribute values for the SNVs across layers and results in establishing a single classifier or a real-time SNV (RT-SNV) classifier to bin out (bin out) the SNVs over multiple layers. Binning refers to one or more methods of grouping a number of generally continuous values into a smaller number of subgroups. The classifier may "bin" the SNVs for specific purposes (e.g., defect classification and detection) by identifying homonymous groups of SNVs.

Non-visual defects (e.g., SNV) can cause electrical failure of the device even in the absence of easily viewable physical residue or visible defects. Examples of non-visual defects include: inter-chip or inter-chip variations in resistance, capacitance, or timing; stress induced dislocations; local crystalline defects; or a local bonding defect. Non-visual defects affect yield, which makes non-visual defects of interest to semiconductor manufacturers, and identifying non-visual defects challenging.

Some defect types (such as SNV or grain) are common and consistent across multiple layers of one or more wafers. This has resulted in a transition from layer-based classifier building to defect-based classifier building. Defect-based classifiers establish a single classifier that involves implementing a common defect type that divides out multiple layers across one or more wafers. The common defect type has a similar range of defect attribute values across multiple layers.

The SNV can be found when the defect maps from all the inspectors are reviewed. The inspectors may include automatic, semi-automatic, and manual wafer inspection tools and processes. The semiconductor manufacturer may not want to miss any real defects, which results in a detection scan with a lower threshold. The lower threshold in turn leads to false positives (false positives) and other nuisance. Separating these false positives or other nuisance from real defects after inspection is a formidable task, as layers with high SNV percentages will require a lot of time and manpower to review. Embodiments of the present invention relate to attribute ranges of SNVs across multiple layers of one or more wafers to build a classifier to separate SNVs from real defects across all layers and all nodes found in all sites.

As disclosed herein, attribute ranges for SNVs on multiple layers may be used to: 1) understanding the physical properties of SNVs across a large number of layers, which would enable procedural separation of SNVs from other real defects; and 2) understand that attributes and attribute ranges are the same for SNVs across a large number of layers, such that such attributes and attribute ranges can be used to programmatically isolate SNVs. The presently disclosed systems and methods also generate and use classifiers to bin out SNVs using a common attribute range of SNVs across all layers. The presently disclosed systems and methods may also generate and use a single classifier for different examples (e.g., chain testing, discovery streams, etc.) to bin out SNVs across all layers. Furthermore, the present invention may use a common (i.e., shared) range of attributes across multiple layers to define a cutoff point for a classifier.

The RT-SNV classifier may reduce costs and increase throughput at the semiconductor manufacturer. In addition, faster classification of defects may help semiconductor manufacturers to solve their yield problems faster, which reduces the time to produce results. These advantages result in significant capital savings for semiconductor manufacturers.

FIG. 1 is a flow chart according to an embodiment of the present invention. Each of the steps of the method may be performed as further described herein. The method may also include any other steps that may be performed by the image acquisition subsystem and/or the computer subsystem or system described herein. The steps are performed by one or more computer systems, which may be configured in accordance with any of the embodiments described herein. Additionally, the methods described above may be performed by any of the system embodiments described herein.

As seen in fig. 1, at 100, an image of a layer on a wafer is generated. The image may be generated or captured using an image capture device, such as a Scanning Electron Microscope (SEM). The images may include one or more images that have been programmatically stitched together. The image may contain multiple views of the wafer, such as views generated using various wavelengths of light. The images may be digitized and stored into a temporary memory (RAM) or a permanent memory, such as a hard drive. The images may be stored in a curation database that is accessible by one or more systems via the internet or an internal network. At 101, at least one attribute of an image is evaluated using a classifier. For example, the images may be retrieved for evaluation by a classification processor. The classification processor may request the image from temporary memory or permanent memory. In one embodiment, the classification processor may request images from a curation database. The classification processor may use a classifier to evaluate the image. Thus, at 102, a classifier is used to identify non-visual defects (e.g., SNVs) on a layer of a wafer.

Classifiers can be built or generated based on defect attributes extracted on SEM review images across multiple layers and/or multiple wafers (and across multiple sites using an associated (assisted) tool). This may be performed using a checking or metering algorithm. The collected SEM review images may be manually classified into different types of defects and SNVs. In some embodiments, the collected SEM review images may be imported from previous tests and known sources.

Defect review and classification software (e.g., Impact XP from KLA-Tencor) was used to determine attribute value ranges for SNVs. The defect review and classification software may include automatic defect classification. The upper and lower limits of the SNV spread for a particular attribute are generated at the boundary within which most SNVs (excluding outliers) co-exist. See, for example, the upper and lower limits in fig. 2. The spread of attribute values for most SNVs lies within a range around the ideal value of the SNV. For example, for SNV, attribute 1-1, attribute 2-0, attribute 3-0, and so on.

Similar data is collected across the various review batches for multiple layers to determine or further analyze attributes useful for defining and classifying SNVs. SNV range data (including upper and lower limits) may be collected for a plurality of attributes. Different imaging conditions may be used across different layers and/or different wafers.

Attribute range values of the SNVs are programmatically analyzed for a common range of layers across one or more wafers. Because the attributes may show a common range of values for the SNV across multiple layers, the common range of attributes for the SNV may be used to implement a single classifier to bin the SNV across multiple layers. These common ranges will be used to define the attribute boundaries of the RT-SNV classifier. The performance of the RT-SNV classifier thus formed was confirmed across multiple wafers.

Various attributes may be used to filter different types of defects from SNV bins using classifiers. These include some or all of the following. The morphology attributes filter out morphology defects, such as particles, scratches, and the like. The strength properties separate high material contrast or high GL difference defects, such as residue, scum, etc. The energy properties filter high energy and high energy density defects such as voids or large defects. Similarly, other types of attributes may be used to separate different types of defects from the SNV.

The extracted attribute range may be plotted. The real-time automatic defect classification (RT-ADC) attributes, the range of SNVs, mentioned below are similar for the various layers.

TABLE 1

The boundary of the common attribute range of the SNVs on all layers may be used as a cutoff point for the corresponding attribute node of the classifier. After which conventional training of the classifier may not be required and the classifier should be ready for deployment in any layer of any node in any customer site. However, in some embodiments, the cut-off point may need to be adjusted away from the common attribute range to compensate for a particular instrument or use.

The following attributes of the nodes may be used by the classifier to separate the SNV from the real defects. Attributes 2, 3, 6, and 5 separate topographical real defects (e.g., particles and scratches) from the SNV. The property 5 may for example relate to an energy measurement. Attribute 2 may, for example, compare peak heights. Attribute 3 and attribute 6 may be a positive measurement and a negative measurement, respectively. Attribute 7 separates high material contrast real defects (such as residue) from SNVs. Attribute 8 separates high density real defects (e.g., voids) from SNVs. Attribute 4 may encompass significance and may separate unique individual defects (such as bumps, small particles, small pits, and openings) from SNVs. Attribute 1 separates any other defects that are not similar to background from the SNV.

See, for example, fig. 3 for an exemplary SNV classifier.

After the classifier is ready, it may be deployed to identify SNVs on layers of other wafers.

As used herein, the term "wafer" generally refers to a substrate formed of a semiconductor or non-semiconductor material. Examples of such semiconductor or non-semiconductor materials include, but are not limited to, single crystal silicon, gallium nitride, gallium arsenide, indium phosphide, sapphire, and glass. Such substrates may typically be found and/or processed in a semiconductor manufacturing facility.

The wafer may include one or more layers formed on a substrate. For example, such layers may include, but are not limited to, photoresists, dielectric materials, conductive materials, and semiconductive materials. Many different types of such layers are known in the art, and the term wafer as used herein is intended to encompass wafers that include all types of such layers.

One or more layers formed on the wafer may be patterned or unpatterned. For example, a wafer may include a plurality of dies, each having a feature or periodic structure that may be repeatedly patterned. The formation and processing of such material layers can ultimately result in a complete device. Many different types of devices can be formed on a wafer, and the term "wafer" as used herein is intended to encompass wafers on which any type of device known in the art is fabricated.

FIG. 4 is an embodiment of a defect review tool 200. Defect review tool 200 may be an SEM, another defect review tool using an electron beam, or other equipment configured to inspect wafers.

The defect review tool 200 includes an object stage 204 configured to hold a wafer 203. The stage 204 may be configured to move or rotate in one, two, or three axes.

As seen in fig. 4, wafer 203 includes a plurality of layers, including layers 209 and 210. Layer 210 is formed after layer 209. Although layer 210 is illustrated in fig. 4 as being imaged, layer 209 may already be imaged prior to forming layer 210. More or fewer layers than the three illustrated in fig. 4 are possible.

The defect review tool 200 also includes an image generation system 201 configured to generate an image of the surface of the wafer 203. The image may be directed to a particular layer of wafer 203. In this example, the image generation system 201 generates an electron beam 202 to generate an image of a wafer 203. Other image generation systems 201 are possible, such as those using broadband plasma or laser scanning.

In a particular example, the defect review tool 200 is part of or is a Scanning Electron Microscope (SEM). An image of the wafer 203 is generated by scanning the wafer 203 with the focused electron beam 202. The electrons are used to generate signals containing information about the surface topography and composition of the wafer 203. The electron beam 202 may be scanned in a raster scan mode, and the position of the electron beam 202 and the detected signals may be combined to generate an image.

The defect review tool 200 communicates with the controller 205. For example, the controller 205 may be in communication with the image generation system 201 or other components of the defect review tool 200. The controller 205 may include a processor 206, a storage device 207 in electronic communication with the processor 206, and a communication port 208 in electronic communication with the processor 206. It should be appreciated that the controller 205 may be implemented by virtually any combination of hardware, software, and firmware. Further, their functions as described herein may be performed by one unit or distributed among different components, each of which in turn may be implemented by any combination of hardware, software, and firmware. The program code or instructions of the controller 205 to implement the various methods and functions described herein may be stored in a controller-readable storage medium (e.g., memory) within the controller 205, external to the controller 205, or a combination thereof.

The controller 205 may also use the classifier to identify non-visual defects, such as SNVs, on the layers of the wafer. For example, the controller 205 may perform the steps of fig. 1. The controller 205 may also perform other steps or techniques disclosed herein.

The controller 205 may be coupled to the detectors of the defect review tool 200 in any suitable manner (e.g., via one or more transmission media, which may include "wired" and/or "wireless" transmission media) such that the controller 205 may receive outputs generated by the detectors (e.g., detectors in the image generation system 201). The controller 205 may be configured to use the output of the detector to perform several functions. For example, the controller 205 may be configured to detect defects on the wafer 203 using the output of the detector. Detecting defects on the wafer 203 may be performed by the controller 205 by applying some defect detection algorithm and/or method to the output generated by the detector. The defect detection algorithms and/or methods may include any suitable algorithms and/or methods disclosed herein or known in the art. For example, the controller 205 may compare the output of the detector to a threshold. Any output having a value above the threshold may be identified as a possible defect (e.g., SNV or other non-visual defect), while any output having a value below the threshold may not be identified as a possible defect. In another example, the controller 205 may be configured to send the output of the detector to the storage device 207 or another storage medium without performing defect detection on the output. The controller 205 may be further configured as described herein.

The controller 205, other systems, or other subsystems described herein may take various forms, including a personal computer system, image computer, host computer system, workstation, network appliance, internet appliance, or other device. In general, the term "controller" may be broadly defined to encompass any device having one or more processors that execute instructions from a memory medium. The subsystem or system may also include any suitable processor known in the art, such as a parallel processor. Additionally, a subsystem or system may include a platform with high speed processing and software, either as a standalone tool or a networked tool.

If a system includes more than one subsystem, the different subsystems may be coupled to each other so that images, data, information, instructions, etc., may be sent between the subsystems. For example, one subsystem may be coupled to additional subsystems by any suitable transmission medium (which may include any suitable wired and/or wireless transmission medium known in the art). Two or more of such subsystems may also be effectively coupled by a shared computer-readable storage medium (not shown).

Additional embodiments relate to a non-transitory computer-readable medium storing program instructions executable on a controller to perform a computer-implemented method for identifying a non-visual defect (e.g., SNV) as disclosed herein. In particular, as shown in fig. 4, the storage device 207 or other storage medium may contain a non-transitory computer-readable medium comprising program instructions executable on the controller 205. A computer-implemented method may include any step of any method described herein.

Program instructions implementing methods such as those described herein may be stored on a computer-readable medium, such as in storage device 207 or other storage medium. The computer readable medium may be a storage medium such as a magnetic or optical disk, a tape, or any other suitable non-transitory computer readable medium known in the art.

The program instructions may be implemented in any of a variety of ways, including program-based techniques, component-based techniques, and/or object-oriented techniques, among others. For example, program instructions may be implemented using ActiveX controls, C + + objects, JavaBeans, Microsoft Foundation classes ("MFC"), SSE (streaming SIMD extensions), or other techniques or methodologies, as desired.

The controller 205 may be configured according to any of the embodiments described herein. Other configurations or functions of the controller 205 are possible, such as those described in U.S. application No. 14/991,901, the disclosure of which is incorporated by reference in its entirety.

Although disclosed as part of a defect review system, the controller described herein may be configured for use with an inspection system. In another embodiment, the controller described herein may be configured for use with a metering system. Thus, embodiments as disclosed herein describe some configurations of classifications that can be customized in several ways for systems with different imaging capabilities more or less suited to different applications.

Embodiments disclosed herein may also be configured for inspection, defect review, and metrology of other specimens, such as reticles. For example, the embodiments described herein may be configured for mask inspection, wafer inspection, and wafer metrology purposes. In particular, the embodiments described herein may be installed on a computer node or computer cluster that is a component of or coupled to an output acquisition subsystem (e.g., a broadband plasma inspector, an electron beam inspector or defect review tool, a mask inspector, a virtual inspector, etc.). In this manner, the embodiments described herein may generate output that may be used for a variety of applications including, but not limited to, wafer inspection, mask inspection, e-beam inspection and review, metrology, and the like. The controller may be modified as described above based on the sample for which the actual output is to be generated.

Embodiments disclosed herein are advantageous over manual classification. RT-SNV assists in manual classification of defects. It automatically filters SNVs using RT-ADC attributes. Which reduces defect classification effort and time. It also reduces human error present in manual classification methods.

Embodiments disclosed herein also have advantages over layer-based automatic classification. A generic defect-based classifier may be used across all layers, with the layer-based classifier acting only on individual layers. The RT-SNV classifier saves the time it takes to build a different SNV classifier on each layer. The RT-SNV classifier may require less training data than a layer-based classifier in which each layer requires training data. The RT-SNV classifier is ready to use, gives consistent results, and does not require any training, while the layer-based classifier needs to be re-tuned, for example, when a new lot with a different defect type or process variation is encountered.

While the invention has been described with respect to one or more particular embodiments, it will be understood that other embodiments of the invention may be made without departing from the scope of the invention. Accordingly, the invention is to be considered limited only by the following claims and the reasonable interpretation thereof.

Claims (16)

1. A wafer inspection system, comprising:

a defect review tool, wherein the defect review tool has an object stage configured to hold a wafer; and

a controller configured to communicate with the defect review tool, wherein the controller is configured to identify non-visual defects on a layer of the wafer using a classifier, wherein the controller identifies non-visual defects by filtering at least one of topographical defects, intensity attributes, or energy attributes using the classifier, wherein the topographical defects comprise particles or scratches, wherein the intensity attributes comprise residue or scum, and wherein the energy attributes comprise voids,

wherein the classifier is established based on defect attributes extracted on the defect review tool review image across multiple layers and/or multiple wafers of the wafer.

2. The wafer inspection system of claim 1, wherein said controller comprises: a processor configured to communicate with the defect review tool; a storage device in electronic communication with the processor containing the classifier; and a communication port in electronic communication with the processor to communicate with the defect review tool.

3. The wafer inspection system of claim 1, wherein the defect review tool is a Scanning Electron Microscope (SEM).

4. The wafer inspection system of claim 1, wherein the non-visual defect is an SEM non-visual defect, SNV.

5. The wafer inspection system of claim 1, wherein the classifier is configured to filter the topographical defects.

6. The wafer inspection system of claim 1, wherein the classifier is configured to filter the intensity attributes.

7. The wafer inspection system of claim 1, wherein the classifier is configured to filter the energy attribute.

8. A wafer inspection method, comprising:

generating an image of a layer on a wafer using a defect review tool;

evaluating, using a processor, at least one attribute of the image with a classifier; and

utilizing the classifier to identify non-visual defects on the layer of the wafer using the processor, wherein the processor identifies non-visual defects by filtering at least one of topographical defects, intensity attributes, or energy attributes using the classifier, wherein the topographical defects comprise particles or scratches, wherein the intensity attributes comprise residue or scum, and wherein the energy attributes comprise voids,

wherein the method further comprises: the classifier is established based on defect attributes extracted on the defect review tool review image across multiple layers and/or multiple wafers of the wafer.

9. The wafer inspection method of claim 8, further comprising defining, using the processor, an upper limit and a lower limit for non-visual defects, wherein the non-visual defects identified are between the upper limit and the lower limit.

10. The wafer inspection method of claim 8, wherein the classifier filters the topographical defects.

11. The wafer inspection method of claim 8, wherein said classifier filters said intensity attributes.

12. The wafer inspection method of claim 8, wherein said classifier filters said energy attributes.

13. The wafer inspection method of claim 8, wherein the classifier is configured to be used on each layer of the wafer.

14. The wafer inspection method of claim 8, wherein the generating uses a Scanning Electron Microscope (SEM).

15. The wafer inspection method of claim 8, wherein the non-visual defect is an SEM non-visual defect, SNV.

16. The wafer inspection method of claim 8, wherein comparing and identifying can be performed in real time with the generating.

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