CN107919871B - Oversampling analog-to-digital converter - Google Patents
Oversampling analog-to-digital converter Download PDFInfo
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- CN107919871B CN107919871B CN201711117832.1A CN201711117832A CN107919871B CN 107919871 B CN107919871 B CN 107919871B CN 201711117832 A CN201711117832 A CN 201711117832A CN 107919871 B CN107919871 B CN 107919871B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/54—Input signal sampled and held with linear return to datum
Abstract
The invention discloses an oversampling analog-to-digital converter, which comprises a subtracter, a loop filter, a quantizer and a feedback digital-to-analog converter which are connected to form a loop, and further comprises an analog jitter signal generating circuit, an analog differentiator, a first analog adder and a second analog adder; the analog jitter signal generating circuit is used for generating a jitter signal only containing noise, and the bandwidth of the jitter signal exceeds the sampling frequency of the oversampling analog-to-digital converter; a first analog adder for adding the dither signal to the input of the quantizer; the input end of the analog differentiator is used for receiving the jitter signal, the transfer function of the analog differentiator and the transfer function of the loop filter are reciprocal, and the analog differentiator is used for carrying out differential processing on the jitter signal; the second analog adder is used for adding the output of the analog differentiator to the output of the feedback digital-to-analog converter. The oversampling analog-to-digital converter has the advantages of good linearity, small area and power consumption and strong stability.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to an oversampling analog-to-digital converter.
[ background of the invention ]
In an electronic circuit, an analog-to-digital converter (ADC) is an important module, and is responsible for converting analog signals such as voice, image, and radio waves into digital signals, and transmitting the digital signals to a subsequent digital circuit for various signal processing. The metrics for measuring the analog-to-digital converter mainly include bandwidth (speed), accuracy and power consumption. An oversampling analog-to-digital converter is an important structure of an analog-to-digital converter, and the basic structure of the oversampling analog-to-digital converter is, as shown in fig. 1, composed of a subtractor, a loop filter 1, a quantizer 2, and a feedback digital-to-analog converter 3. In fig. 1, X denotes an input analog signal, and Y denotes an output digital signal. Compared with other analog-to-digital converters, the continuous-time oversampling analog-to-digital converter has an endogenous anti-aliasing filtering function, and can reduce the design difficulty and power consumption of a front-end filter. The bandwidth of the oversampling analog-to-digital converter is jointly determined by a sampling rate (Fs) and an over-sampling rate (OSR); the accuracy of the oversampling analog-to-digital converter is determined by the oversampling rate OSR, the quantization bit number B, and the noise shaping order L.
The oversampling analog-to-digital converter can be divided into single-bit and multi-bit types according to the difference of the quantization bit number B of the oversampling analog-to-digital converter. The quantizer and feedback digital-to-analog converter of the single-bit type oversampling analog-to-digital converter are single-bit and are naturally linear. The disadvantage of the single-bit type oversampling analog-to-digital converter is that its accuracy is relatively low under the condition that other parameters are the same; quantization noise is relatively large; the requirement for operational amplifiers in the filter is high; is more sensitive to clock jitter (clock jitter) of the feedback digital-to-analog converter. Today, the bandwidth requirement of the oversampling analog-to-digital converter is higher, the oversampling ratio OSR of the converter is limited by the circuit technology, and the noise shaping order L of the converter is limited by the stability, so that the adoption of the multi-bit type oversampling analog-to-digital converter is more and more preferred by people, and the above-mentioned disadvantages of the single-bit type oversampling analog-to-digital converter are avoided in the process. However, both the quantizer and the feedback dac of the multi-bit oversampling adc are multi-bit, and the linearity of the multi-bit adc directly limits the linearity of the adc, and how to improve the linearity of the multi-bit adc is a concern.
The above background disclosure is only for the purpose of assisting understanding of the inventive concept and technical solutions of the present invention, and does not necessarily belong to the prior art of the present patent application, and should not be used for evaluating the novelty and inventive step of the present application in the case that there is no clear evidence that the above content is disclosed at the filing date of the present patent application.
[ summary of the invention ]
The technical problem to be solved by the invention is as follows: the shortcomings of the prior art are overcome, and the linearity of the oversampling analog-to-digital converter is better than that of the conventional multi-bit oversampling analog-to-digital converter, the area and the power consumption are smaller, and the stability is stronger.
The technical problem of the invention is solved by the following technical scheme:
an oversampling analog-to-digital converter comprises a subtracter, a loop filter, a quantizer and a feedback digital-to-analog converter which are connected to form a loop, and further comprises an analog jitter signal generating circuit, an analog differentiator, a first analog adder and a second analog adder; the analog jitter signal generating circuit is used for generating an analog jitter signal only containing noise, and the bandwidth of the analog jitter signal exceeds the sampling frequency of the oversampling analog-to-digital converter; the first analog adder is configured to add the analog dither signal to an input of the quantizer; the input end of the analog differentiator is used for receiving the analog jitter signal, the transfer function of the analog differentiator and the transfer function of the loop filter are reciprocal, and the analog differentiator is used for performing differentiation processing on the analog jitter signal; the second analog adder is used for adding the output of the analog differentiator to the output of the feedback digital-to-analog converter.
Compared with the prior art, the invention has the advantages that:
the oversampling analog-to-digital converter of the present invention is a multi-bit oversampling analog-to-digital converter, and improves the linearity of the multi-bit oversampling analog-to-digital converter through an analog dither signal. Due to the randomness in the amplitude of the analog dither signal, the digital output of the multi-bit quantizer correspondingly exhibits randomness. Because the output of the multi-bit quantizer corresponds to the input of the feedback digital-to-analog converter one by one, the randomness of the digital output of the multi-bit quantizer enables the probability of activation of each unit of the feedback digital-to-analog converter to be equal, namely, the first-order shaping is performed on the mismatch of each unit of the feedback digital-to-analog converter, so that the problem of linearity caused by the mismatch of the feedback digital-to-analog converter units is solved, and the linearity of the multi-bit oversampling analog-to-digital converter is improved. Because the circuit structure adopts simple signal generating circuit, differentiator, analog adder and the like, the analog-digital converter does not need to be redesigned, the circuit area and the power consumption can still be ensured to be small, and the loop delay cannot be introduced into the circuit structure, so the stability is good. The improved scheme of the invention can be widely applied to analog-to-digital converters with various sampling frequencies, and even to analog-to-digital converters with high-speed sampling.
[ description of the drawings ]
FIG. 1 is a schematic diagram of a multi-bit oversampling analog-to-digital converter in the prior art;
FIG. 2 is a circuit diagram of a multi-bit oversampling analog-to-digital converter in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram of an analog dither signal generating circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a frequency spectrum of an analog dither signal in accordance with an embodiment of the present invention;
fig. 5 is a circuit configuration diagram of a differentiator in the embodiment of the present invention.
[ detailed description ] embodiments
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.
The conception of the invention is as follows: for the linearity problem of the digital-to-analog converter in the multi-bit type oversampling analog-to-digital converter, there are several solutions, but each has advantages and disadvantages: 1, the linearity of the multi-bit digital-to-analog converter is improved by improving the circuit design of the multi-bit digital-to-analog converter, the method needs to pay a huge price of circuit area and power consumption, and the upper limit of the precision of the method is 13 bits. And 2, inserting a Dynamic Element Matching (DEM) module between the output of the quantizer and the feedback digital-to-analog converter, and randomly processing the unit selection process in the feedback digital-to-analog converter to ensure that the utilization rate of each feedback digital-to-analog converter unit is equal. The method can effectively eliminate the influence of nonlinearity in the feedback digital-to-analog converter on the linearity of the analog-to-digital converter. The problem with this approach is that the Dynamic Element Matching (DEM) module introduces additional loop delay that affects the overall stability of the oversampling analog-to-digital converter. And 3, randomly inverting (buffering) each reference level of the multi-bit quantizer to achieve the purpose of randomizing the digital output of the quantizer. The method has the effect of being equivalent to a Dynamic Element Matching (DEM) module to a certain extent, and has the advantages that the circuit delay is out of a loop, the stability of the oversampling analog-to-digital converter cannot be influenced, but the overturning circuit cannot complete the overturning of the reference level within one clock period under the condition of high sampling frequency. And 4, processing the digital output of the oversampling analog-to-digital converter and calibrating the nonlinearity of the feedback digital-to-analog converter. The calibration method can be a foreground calibration method or a background calibration method, and for the foreground calibration method, a high-precision analog sine wave input signal is required. A disadvantage of this approach is that the delay (latency) from the analog-to-digital input to the digital output of the oversampling analog-to-digital converter is increased.
The invention starts from a random processing process, and generates an analog jitter signal through an analog circuit so as to improve the linearity of the multi-bit oversampling analog-to-digital converter. The analog dither signal is added to the input end of the quantizer through the adder, meanwhile, the analog dither signal is subjected to differential processing through the differentiator and added to the output of the feedback digital-to-analog converter, so that the analog dither signal injected into the input end of the quantizer is offset, and the accuracy of oversampling analog-to-digital conversion is not influenced by the added circuit module.
Fig. 2 is a circuit diagram of the multi-bit oversampling analog-to-digital converter according to the present embodiment, which uses analog jitter to improve linearity. A block 4 is added on the basis of the conventional multi-bit oversampling analog-to-digital converter shown in fig. 1. The basic working principle is as follows:
the module 4.1 is an analog dither signal generating circuit for generating a dither signal containing only noise. There are various ways to implement the jitter signal generating circuit, and the circuit structure shown in fig. 3 is a scheme with simple structure and convenient implementation. As shown in fig. 3, firstly, the resistor voltage divider divides the voltage of the power supply Vdd to obtain a voltage signal Vr with a large amount of resistance thermal noise; and then subtracting the standard voltage Vbg generated by the band-gap reference source from the voltage signal Vr, and amplifying the result by an amplifier to obtain the jitter signal Vjitter. That is, the jitter signal Vdither ═ k × (Vbg-Vr), where k denotes the amplification factor at the time of amplification. In this way, the dc voltage in the voltage Vr is completely removed, thereby obtaining a dither signal containing only noise. The amplitude of the dither signal can be adjusted by adjusting the resistance of the resistor divider and the amplification factor of the amplifier. The bandwidth of the dither signal may be adjusted by adjusting the bandwidth of the amplifier. Through adjustment, the bandwidth of the output analog jitter signal Vjitter exceeds the sampling frequency of the oversampling analog-to-digital converter, so that the analog jitter signal can have sufficient randomness in the time domain, and the digital output of the analog jitter signal can have sufficient randomness after the analog jitter signal is subsequently added into a quantizer, so that the problem of linearity caused by mismatch of a feedback link can be sufficiently eliminated. Preferably, the bandwidth of the analog dither signal is adjusted to have an amplitude between-40 dB and-60 dB. If the bandwidth is higher than-40 dB, the quantizer is saturated; if the bandwidth is lower than-60 dB, it is not enough to randomize the cells of the digital-to-analog converter, so it is preferable to control them between-40 dB and-60 dB. The graph of the simulated jittered signal spectrum in the present embodiment is shown in fig. 4.
In the multi-bit oversampling analog-to-digital converter shown in fig. 2, the output of the analog dither signal generating circuit 4.1 is added to the input of the multi-bit quantizer 2 via a first analog adder 4.3. Due to the randomness in the amplitude of the analog dither signal, the digital output of the multi-bit quantizer 2 will exhibit randomness accordingly. Because the output of the multi-bit quantizer 2 corresponds to the input of the feedback digital-to-analog converter 3 one by one, the randomness of the digital output of the multi-bit quantizer 2 enables the probability of each unit in the feedback digital-to-analog converter 3 being activated to be equal, which is equivalent to performing first-order shaping on the mismatch of each unit in the feedback digital-to-analog converter 3, thereby eliminating the problem of linearity caused by the mismatch of each unit of the feedback digital-to-analog converter 3. In a specific circuit design, the first analog adder 4.3 may be combined with the multi-bit quantizer 2, thereby simplifying the circuit.
In order that the analog dither signal injected by the first analog adder 4.3 does not affect the accuracy of the overall oversampling analog-to-digital conversion, a block is provided at the output of the feedback digital-to-analog converter to cancel the analog dither signal. In order to completely cancel the analog dither signal injected at the input of the quantizer 2, the output of the analog dither signal generating circuit 4.1 is differentiated by an analog differentiator 4.2, so as to obtain a corresponding signal for canceling the analog dither signal at the output of the feedback dac, and the signal is added to the output of the feedback dac 3 by a second analog adder 4.4. The transfer function of the analog differentiator 4.2 and the transfer function of the loop filter 1 in the oversampled analog to digital converter are inverse to each other, so that the effect of the dither signal is cancelled out in the digital output of the overall oversampled analog to digital converter.
The circuit implementation of the analog differentiator 4.2 is shown in fig. 5 and is formed by an analog amplifier, an input capacitor and a feedback resistor. The forward input end of the analog amplifier is grounded, the reverse input end of the analog amplifier receives the dither signal through the input capacitor, the feedback resistor is connected with the reverse input end and the output end of the analog amplifier, and the output end of the analog amplifier is used as the output end of the analog differentiator 4.2 and is connected to one input end of the second analog adder 4.4. For convenience, the analog amplifier, the resistor and the capacitor in the analog differentiator 4.2 may multiplex the corresponding devices of the loop filter 1, and the positions of the resistor and the capacitor may be simply changed. In the design, the second analog adder 4.4 can be integrated with the front-end subtracter of the whole oversampling analog-to-digital converter and the loop filter 1, which greatly simplifies the design.
In the oversampling adc according to the embodiment, the analog dither signal is generated by the analog circuit to improve the linearity of the multi-bit oversampling adc, and the accuracy of the multi-bit oversampling adc is not affected. There are advantages in area and power consumption compared to the aforementioned manner 1 of improving linearity; compared with the mode 2, the loop delay is not introduced, and the stability problem is avoided; compared with the mode 3, the method can be used in some analog-to-digital converters with high-speed sampling; compared with foreground calibration of the mode 4, the method can be operated in the background all the time, and compared with background calibration of the mode 4, the method has no problem of convergence rate.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several alternatives or obvious modifications can be made without departing from the spirit of the invention, and all equivalents in performance or use should be deemed to fall within the scope of the invention.
Claims (5)
1. An oversampled analog to digital converter comprising a subtractor, a loop filter, a quantizer, and a feedback digital to analog converter connected to form a loop, characterized in that: the analog jitter signal generation circuit, the analog differentiator, the first analog adder and the second analog adder are arranged in the loop; the analog jitter signal generating circuit is used for generating an analog jitter signal only containing noise, and the bandwidth of the analog jitter signal exceeds the sampling frequency of the oversampling analog-to-digital converter; the first input end of the first analog adder is used for receiving the analog jitter signal, the second input end of the first analog adder is connected with the output end of the loop filter, the output end of the first analog adder is connected with the input end of the quantizer, the first input end of the second analog adder is connected with the output end of the analog differentiator, the second input end of the second analog adder is connected with the output end of the feedback digital-to-analog converter, and the output end of the second analog adder is connected with the subtraction end of the subtractor; the first analog adder is configured to add the analog dither signal to an input of the quantizer; the input end of the analog differentiator is used for receiving the analog jitter signal, the transfer function of the analog differentiator and the transfer function of the loop filter are reciprocal, and the analog differentiator is used for performing differentiation processing on the analog jitter signal; the second analog adder is used for adding the output of the analog differentiator to the output of the feedback digital-to-analog converter; the randomness of the digital output of the quantizer enables the probability of activation of each unit in the feedback digital-to-analog converter to be equal, so that the problem of linearity caused by mismatching of each unit of the feedback digital-to-analog converter is solved; the analog jitter signal generating circuit comprises a resistor voltage divider and an amplifying circuit; the resistance voltage divider is used for dividing voltage to obtain a voltage signal, the amplifying circuit is used for receiving the voltage signal, subtracting the voltage signal from a reference voltage generated by the band-gap reference source and then amplifying the voltage signal, and an analog jitter signal Vjitter (Vbg-Vr) is output, wherein k represents the amplification factor during amplification, Vbg represents the reference voltage, and Vr represents the voltage signal.
2. The oversampling analog-to-digital converter of claim 1, wherein: the bandwidth amplitude of the analog dither signal is between-40 dB and-60 dB.
3. The oversampling analog-to-digital converter of claim 1, wherein: the analog differentiator comprises an analog amplifier, an input capacitor and a feedback resistor, wherein the forward input end of the analog amplifier is grounded, the reverse input end of the analog amplifier receives the analog jitter signal through the input capacitor, the feedback resistor is connected with the reverse input end and the output end of the analog amplifier, and the output end of the analog amplifier is used as the output end of the analog differentiator.
4. The oversampling analog-to-digital converter of claim 1, wherein: the first analog adder is integrated with the quantizer.
5. The oversampling analog-to-digital converter of claim 1, wherein: the second analog adder is integrated with the subtracter and the loop filter.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103929184A (en) * | 2014-04-16 | 2014-07-16 | 中国科学技术大学 | Delta-sigma modulator based on digital-noise coupling technology |
| CN104518797A (en) * | 2015-01-26 | 2015-04-15 | 中国电子科技集团公司第二十四研究所 | Jitter circuit for high-precision analogue to digital converter |
| CN104716964A (en) * | 2013-12-17 | 2015-06-17 | 瑞萨电子株式会社 | Delta-sigma modulator |
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| US6462685B1 (en) * | 2001-04-05 | 2002-10-08 | Nokia Corporation | Dither signal insertion inversely proportional to signal level in delta-sigma modulators |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716964A (en) * | 2013-12-17 | 2015-06-17 | 瑞萨电子株式会社 | Delta-sigma modulator |
| CN103929184A (en) * | 2014-04-16 | 2014-07-16 | 中国科学技术大学 | Delta-sigma modulator based on digital-noise coupling technology |
| CN104518797A (en) * | 2015-01-26 | 2015-04-15 | 中国电子科技集团公司第二十四研究所 | Jitter circuit for high-precision analogue to digital converter |
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