CN107919143B - Solid-state storage device and temperature control method thereof - Google Patents

Solid-state storage device and temperature control method thereof Download PDF

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Publication number
CN107919143B
CN107919143B CN201610886067.9A CN201610886067A CN107919143B CN 107919143 B CN107919143 B CN 107919143B CN 201610886067 A CN201610886067 A CN 201610886067A CN 107919143 B CN107919143 B CN 107919143B
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power
value
solid
pool
state storage
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CN107919143A (en
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曹定尊
路向峰
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Beijing Memblaze Technology Co Ltd
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Beijing Memblaze Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

Provided are a solid-state storage device and a temperature control method thereof. The control method of the solid-state storage device comprises the following steps: s1, measuring a current temperature value; s2, updating the value of the power limit pool according to the difference between the current temperature value and the target temperature value; s3, responding to the operation of accessing the NVM chip, and applying for a power credit from the power credit pool; s4, according to the applied power limit, executing the operation of accessing the NVM chip; and S5, responding to the completion of the execution of the operation of accessing the NVM chip, and returning the power credit.

Description

Solid-state storage device and temperature control method thereof
Technical Field
The application relates to the technical field of solid-state storage, in particular to a solid-state storage device and a control method thereof.
Background
FIG. 1 is a block diagram of a solid-state storage device of the prior art. The solid-state storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.
NAND flash Memory, phase change Memory, feRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), etc. are common NVM.
The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.
The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the firmware memory 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof; the control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands; the control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110; FTL tables and/or cached IO command data may be stored in the DRAM.
Control section 104 includes a flash interface controller (or referred to as a flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to the interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. The interface protocol of the NVM chip 105 includes well-known interface protocols or standards such as "Toggle", "ONFI", etc.
The memory Target (Target) is one or more Logic units (Logic units) sharing a Chip Enable signal (CE) within the NAND flash memory package. Each logical Unit has a Logical Unit Number (LUN). One or more dies (Die) may be included within the NAND flash memory package. Typically, the logic corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logical unit may be accessed in parallel, while multiple logical units within a NAND flash memory chip may execute commands and report status independently of each other.
In a solid state memory device, different operations accessing NVM chip 105 consume different amounts of energy corresponding to different power consumption. The NVMe protocol defines the power consumption state of the solid-state storage device (see table 1). A plurality of power consumption states are defined in table 1, and each power consumption state has a different maximum power consumption. The operating temperature of solid-state storage devices also needs to be effectively controlled. Either too high or too low a temperature can affect the operation of the electronic device. The temperature is affected by factors such as power consumption and environmental heat dissipation capability of the solid-state storage device. The operation of the electronic device is affected by the temperature of the solid-state storage device being too high or too low.
TABLE 1
State of power consumption Maximum power consumption Entry delay Exit delay
0 25W 5μs 5μs
1 18W 5μs 7μs
2 18W 5μs 8μs
3 15W 20μs 15μs
4 10W 20μs 30μs
5 8W 20μs 50μs
6 5W 20μs 5000μs
Disclosure of Invention
Solid-state storage devices that conform to the NVMe protocol need to implement multiple power consumption states. To achieve the power consumption states required by the NVMe protocol, the temperature and power consumption of the solid-state storage device need to be controlled within specified values or ranges. The invention aims to provide a solid-state storage device and a control method thereof. For controlling power and temperature of the solid-state storage device.
According to a first aspect of the present invention, there is provided a control method of a first solid-state storage device according to the first aspect of the present invention, comprising the steps of: s1, measuring a current temperature value; s2, updating the value of the power limit pool according to the difference between the current temperature value and the target temperature value; s3, responding to the operation of accessing the NVM chip, and applying for a power credit from the power credit pool; s4, according to the applied power limit, executing the operation of accessing the NVM chip; and S5, responding to the completion of the operation of accessing the NVM chip, and returning the power quota.
According to the control method of the first solid-state storage device of the first aspect of the present invention, there is provided the control method of the second solid-state storage device of the first aspect of the present invention, if the current temperature value is greater than the target temperature value, the value of the rated power pool is decreased; and if the current temperature value is smaller than the target temperature value, the value of the power limit pool is increased.
According to the control method of the second solid-state storage device in the first aspect of the invention, there is provided the control method of the third solid-state storage device in the first aspect of the invention, wherein an amount of the decrease or the increase of the value of the power credit pool is proportional to a difference between the current temperature value and the target temperature value.
According to the control method of the second solid-state storage device in the first aspect of the present invention, there is provided the control method of the fourth solid-state storage device in the first aspect of the present invention, wherein the amount of decrease or increase of the value of the power credit pool is obtained according to a difference between the current temperature value and the target temperature value.
According to one of the control methods of the first to fourth solid-state storage devices of the first aspect of the present invention, there is provided the control method of the fifth solid-state storage device according to the first aspect of the present invention, further comprising: measuring the current power value, and if the current power value is larger than the target power value, reducing the value of the rated power pool; if the current power value is smaller than the target power value, the value of the power limit pool is increased.
According to one of the control methods of the first to fifth solid-state storage devices of the first aspect of the present invention, there is provided the control method of the sixth solid-state storage device of the first aspect of the present invention, the applying for the power credit from the power credit pool further includes: and responding to the success of the power limit application, and executing the step S4.
According to one of the control methods of the first to sixth solid-state storage devices of the first aspect of the present invention, there is provided the control method of the seventh solid-state storage device according to the first aspect of the present invention, the step S2 is periodically performed.
According to one of the control methods of the first to seventh solid-state storage devices of the first aspect of the present invention, there is provided the control method of the eighth solid-state storage device of the first aspect of the present invention, wherein updating the value of the power credit pool according to a difference between the current temperature value and the target temperature value includes: judging whether the solid-state storage device is in a power unlimited mode at present; if yes, the power available quota of the power quota pool is set to the maximum value, and the value of the power quota pool is updated.
According to one of the control methods of the first to eighth solid-state storage devices of the first aspect of the present invention, there is provided the control method of the ninth solid-state storage device according to the first aspect of the present invention, if the solid-state storage device is not currently in the power unlimited mode; judging whether the period for acquiring the temperature value is reached; if so, reading the current temperature value, updating the power available limit of the power limit pool according to the difference between the current temperature value and the target temperature value, and updating the value of the power limit pool.
According to one of the control methods of the first to ninth solid-state storage devices of the first aspect of the present invention, there is provided the control method of the tenth solid-state storage device according to the first aspect of the present invention, which adjusts down the target power value in response to an operation of accessing the NVM chip in which a burst occurs.
According to a control method of a tenth solid-state storage device of the first aspect of the present invention, there is provided the control method of the eleventh solid-state storage device of the first aspect of the present invention, the operation of accessing the NVM chip in which the burst occurs includes that there is a read operation, a write operation, or an erase operation exceeding a first threshold value, or that the total amount of the three operations exceeds a second threshold value, in a unit time.
According to a control method of a tenth solid-state storage device of the first aspect of the present invention, there is provided the control method of the twelfth solid-state storage device of the first aspect of the present invention, the operation of accessing the NVM chip in a burst refers to an increment of the operation of accessing the NVM chip per unit time exceeding a third threshold.
According to one of the control methods of the tenth to twelfth solid-state storage devices of the first aspect of the present invention, there is provided the control method of the thirteenth solid-state storage device according to the first aspect of the present invention, the solid-state storage device including a plurality of command queues, an operation in one command queue to access the NVM chip accessing a logical unit corresponding to the command queue.
According to the thirteenth solid-state memory device control method of the first aspect of the present invention, there is provided the fourteenth solid-state memory device control method of the first aspect of the present invention, wherein if the value of the power credit pool is not enough to be allocated to the plurality of operations accessing the NVM chip, the credit values are alternately allocated to the operations accessing the NVM chip in different command queues.
According to one of the control methods of the first to fourteenth solid-state storage devices of the first aspect of the present invention, there is provided the control method of the fifteenth solid-state storage device according to the first aspect of the present invention, the credit values required to perform the read operation, the program operation, or the erase operation are different.
The control method of the solid-state storage device enables the temperature and the power of the solid-state storage device to be controlled, the power consumption of the solid-state storage device to be managed more reasonably, and the use times and the service life of the solid-state storage device are prolonged.
According to a second aspect of the present invention, there is provided a control method of a first solid-state storage device according to the second aspect of the present invention, comprising the steps of: measuring the current power value, and updating the power available limit of the power limit pool according to the difference between the current power value and the target power value; measuring a current temperature value; calculating a second power available credit of the power credit pool according to the difference between the current temperature value and the target temperature value; if the second power available quota is smaller than the power available quota of the power quota pool, updating the power available quota of the power quota pool with the second power available quota.
According to the control method of the first solid-state storage device of the second aspect of the present invention, there is provided the control method of the second solid-state storage device according to the second aspect of the present invention, in response to there being an operation of accessing the NVM chip, applying for a power credit from the power credit pool; according to the applied power limit, executing the operation of accessing the NVM chip; the power credit is returned in response to completion of performance of the operation to access the NVM chip.
According to one of the control methods of the first to second solid-state storage devices of the second aspect of the present invention, there is provided the control method of the third solid-state storage device according to the second aspect of the present invention, which adjusts down the target power value in response to an operation of accessing the NVM chip in which a burst occurs.
According to a control method of a third solid-state storage device of the second aspect of the present invention, there is provided the control method of the fourth solid-state storage device of the second aspect of the present invention, the operation of accessing the NVM chip in which the burst occurs includes a presence of a read operation, a write operation, or an erase operation exceeding a first threshold value per unit time, or a total amount of the three operations exceeding a second threshold value.
According to a control method of a third solid-state storage device of the second aspect of the present invention, there is provided the control method of the fifth solid-state storage device of the second aspect of the present invention, the operation of accessing the NVM chip in a burst refers to an increment of the operation of accessing the NVM chip per unit time exceeding a third threshold.
According to one of the control methods of the third to fifth solid-state storage devices of the second aspect of the present invention, there is provided the control method of the sixth solid-state storage device according to the second aspect of the present invention, the solid-state storage device including a plurality of command queues, an operation in one command queue to access the NVM chip accessing a logical unit corresponding to the command queue.
According to the control method of the sixth solid-state storage device in the second aspect of the invention, a control method of the seventh solid-state storage device in the second aspect of the invention is provided, if the value of the power credit pool is not enough to be allocated to a plurality of operations for accessing the NVM chip, credit values are alternately allocated to the operations for accessing the NVM chip in different command queues.
According to one of the control methods of the first to seventh solid-state storage devices of the second aspect of the present invention, there is provided the control method of the eighth solid-state storage device according to the second aspect of the present invention, the operation of accessing the NVM chip includes a read operation, a program operation, or an erase operation.
According to the control method of the eighth solid-state storage device of the second aspect of the present invention, there is provided the control method of the ninth solid-state storage device of the second aspect of the present invention, the credit values required to perform the read operation, the program operation, or the erase operation are different.
The control method of the solid-state storage device enables the temperature and the power of the solid-state storage device to be controlled, the power consumption of the solid-state storage device to be managed more reasonably, and the use times and the service life of the solid-state storage device are prolonged.
According to a third aspect of the present invention, there is provided a first solid-state storage device according to the third aspect of the present invention, comprising: the system comprises an NVM chip, a control management system, a power sensor and a temperature sensor, wherein the NVM chip is coupled with the control management system, and the power sensor and the temperature sensor are both coupled with the control management system; the power sensor is used for measuring the current power value of the solid-state storage device; the temperature sensor is used for measuring the current temperature value of the solid-state storage device; the control management system is used for scheduling and accessing the operation of the NVM chip through the current power value of the solid-state storage device measured by the power sensor and the current temperature value of the solid-state storage device measured by the temperature sensor.
According to a first solid-state storage device of a third aspect of the present invention, there is provided a second solid-state storage device according to the third aspect of the present invention, the control management system comprising: the power limit management system comprises a power control unit, a power limit pool and a power limit manager, wherein the power limit pool is respectively coupled with the power limit manager and the power control unit, the power limit manager is coupled with an NVM chip, and the power control unit is coupled with a power sensor and a temperature sensor, wherein the power control unit is used for controlling the current temperature value to be below a target temperature value while meeting a target power value according to the current temperature value and the target temperature value; setting the value of a power limit pool according to the current power value and the target power value; the power limit manager is used for applying for the limit to the power limit pool, allowing the operation of accessing the NVM chip to be executed, and returning the limit to the power limit pool after the operation execution is finished.
According to the second solid-state storage device of the third aspect of the present invention, there is provided the third solid-state storage device of the third aspect of the present invention, wherein when the power credit manager fails to apply credit to the power credit pool, the operation of accessing the NVM chip is suspended until the credit application to the power credit pool is successful.
According to the first or second solid-state storage device of the third aspect of the present invention, there is provided the fourth solid-state storage device of the third aspect of the present invention, the power control unit is further configured to recognize an operation of accessing the NVM chip in a burst and adjust down the target power value.
The solid-state storage device provided by the invention has the advantages that the temperature and the power of the solid-state storage device are controlled, the power consumption management of the solid-state storage device is more reasonable, and the use times and the service life of the solid-state storage device are prolonged.
According to a fourth aspect of the present invention, there is provided a power control method of a first solid-state storage device according to the fourth aspect of the present invention, comprising the steps of: s1, responding to the operation of accessing the NVM chip, and applying for a power credit from a power credit pool; s2, according to the applied power limit, executing the operation of accessing the NVM chip; and S3, returning the power credit to the power credit pool in response to the completion of the operation of accessing the NVM chip.
According to a power control method of a first solid-state storage device of a fourth aspect of the present invention, there is provided a power control method of a second solid-state storage device according to the fourth aspect of the present invention, further comprising: step R1, obtaining a current power value of the solid-state storage device; and step R2, updating the value of the power limit pool according to the difference between the current power value and the target power value.
According to one of the power control methods of the first to second solid-state storage devices of the fourth aspect of the present invention, there is provided the power control method of the third solid-state storage device of the fourth aspect of the present invention, the applying for the power credit from the power credit pool further includes: and responding to the success of the power limit application, and executing the step S2.
According to one of the power control methods of the first to second solid-state storage devices of the fourth aspect of the present invention, there is provided the power control method of the fourth solid-state storage device according to the fourth aspect of the present invention, wherein the applying for the power credit from the power credit pool further includes, in response to a failure of the power credit application, temporarily handling the operation of accessing the NVM chip until the power credit application succeeds.
According to one of the power control methods of the first to third solid-state storage devices of the fourth aspect of the present invention, there is provided the power control method of the fifth solid-state storage device according to the fourth aspect of the present invention, periodically performing step R2.
According to one of the power control methods of the first to third solid-state storage devices of the fourth aspect of the present invention, there is provided the power control method of the sixth solid-state storage device of the fourth aspect of the present invention, wherein the updating the value of the power credit pool according to the difference between the current power value and the target power value in step R2 includes: judging whether the solid-state storage device is in a power unlimited mode at present; if yes, the power available quota of the power quota pool is set to the maximum value, and the value of the power quota pool is updated.
According to one of the power control methods of the first to sixth solid-state storage devices of the fourth aspect of the present invention, there is provided the power control method of the seventh solid-state storage device of the fourth aspect of the present invention, wherein updating the value of the power credit pool according to the difference between the current power value and the target power value comprises: if the current power value is larger than the target power value, reducing the value of the power limit pool; if the current power value is smaller than the target power value, the value of the power limit pool is increased.
According to a power control method of a seventh solid-state storage device of a fourth aspect of the present invention, there is provided the power control method of the eighth solid-state storage device of the fourth aspect of the present invention, an amount of decrease or increase of the value of the power credit pool is proportional to a difference between the current power value and the target power value.
According to one of the power control methods of the first to eighth solid-state storage devices of the fourth aspect of the present invention, there is provided the power control method of the ninth solid-state storage device according to the fourth aspect of the present invention, further comprising: the target power value is adjusted down in response to an operation to access the NVM chip in which a burst occurs.
According to a ninth solid-state storage device power control method of a fourth aspect of the present invention, there is provided the tenth solid-state storage device power control method of the fourth aspect of the present invention, the operation of accessing the NVM chip in which the burst occurs includes: there is a read operation, a write operation, or an erase operation exceeding the first threshold value in the unit time, or the total of the three operations exceeds the second threshold value.
According to a power control method of a ninth solid-state storage device of the fourth aspect of the present invention, there is provided the power control method of the eleventh solid-state storage device of the fourth aspect of the present invention, the operation of accessing the NVM chip in a burst refers to an increment of the operation of accessing the NVM chip per unit time exceeding a third threshold.
According to one of the power control methods of the ninth to eleventh solid-state storage devices of the fourth aspect of the present invention, there is provided the power control method of the twelfth solid-state storage device according to the fourth aspect of the present invention, the solid-state storage device including a plurality of command queues, an operation in one command queue to access the NVM chip accessing a logical unit corresponding to the command queue.
According to a power control method of a twelfth solid-state storage device of the fourth aspect of the present invention, there is provided the power control method of the thirteenth solid-state storage device of the fourth aspect of the present invention, if the value of the power credit pool is not sufficiently allocated to the plurality of operations accessing the NVM chip, allocating credit values to the operations accessing the NVM chip in different command queues in turn.
According to one of the power control methods of the first to thirteenth solid-state storage devices of the fourth aspect of the present invention, there is provided the power control method of the fourteenth solid-state storage device according to the fourth aspect of the present invention, the operation of accessing the NVM chip includes a read operation, a program operation, or an erase operation.
According to a power control method of a fourteenth solid-state storage device of a fourth aspect of the present invention, there is provided the power control method of the fifteenth solid-state storage device of the fourth aspect of the present invention, the credit values required to perform a read operation, a program operation, or an erase operation are different.
The power control method of the solid-state storage device enables the power of the solid-state storage device to be controlled, power consumption management of the solid-state storage device is more reasonable, and the use times and service life of the solid-state storage device are prolonged.
According to a fifth aspect of the present invention, there is provided a first solid-state storage device according to the fifth aspect of the present invention, comprising: the system comprises an NVM chip, a power management system and a power sensor, wherein the NVM chip is coupled with the power management system, and the power sensor is coupled with the power management system; the power sensor is used for measuring the current power value of the solid-state storage device; the power management system is used for scheduling the operation of accessing the NVM chip through the current power value of the solid-state storage device measured by the power sensor.
According to a fifth aspect of the present invention, there is provided a second solid-state storage device according to the fifth aspect of the present invention, the power management system comprising: the power limit management system comprises a power control unit, a power limit pool and a power limit manager, wherein the power limit pool is respectively coupled with the power limit manager and the power control unit, the power limit manager is coupled with an NVM (non-volatile memory) chip, the power control unit is coupled with a power sensor, and the power control unit is used for setting the value of the power limit pool according to the current power value and a target power value; the power limit manager is used for applying for the limit to the power limit pool, allowing the operation of accessing the NVM chip to be executed, and returning the limit to the power limit pool after the operation execution is finished.
According to the second solid-state storage device of the fifth aspect of the present invention, there is provided the third solid-state storage device of the fifth aspect of the present invention, wherein when the power credit manager fails to apply credit to the power credit pool, and when the credit in the power credit pool is used up, the operation of accessing the NVM chip is suspended until the credit application to the power credit pool is successful.
According to a second or third solid-state storage device of the fifth aspect of the invention, there is provided a fourth solid-state storage device of the fifth aspect of the invention, the power control unit further being configured to identify a burst of operations to access the NVM chip and to adjust the target power value down.
The power control method of the solid-state storage device enables the power of the solid-state storage device to be controlled, power consumption management of the solid-state storage device is more reasonable, and the use times and service life of the solid-state storage device are prolonged.
According to a sixth aspect of the present invention, there is provided a power control apparatus of a first solid-state storage device according to the sixth aspect of the present invention, comprising: the power credit applying module is used for responding to the operation of accessing the NVM chip and applying for the power credit from the power credit pool; the execution module is used for executing the operation of accessing the NVM chip according to the applied power limit; and a power credit return module for returning the power credit to the power credit pool in response to completion of execution of the operation for accessing the NVM chip.
The power control device of the first solid-state storage device according to the sixth aspect of the present invention provides the power control device of the second solid-state storage device according to the sixth aspect of the present invention, and the power obtaining module is configured to obtain a current power value of the solid-state storage device; and the power limit updating module is used for updating the value of the power limit pool according to the difference between the current power value and the target power value.
According to the power control device of the first or second solid-state storage device of the sixth aspect of the invention, the power control device of the third solid-state storage device of the sixth aspect of the invention is provided, and in response to the success of the power credit application module applying for the power credit, the execution module executes the operation of accessing the NVM chip.
According to the power control device of the first or second solid-state storage device of the sixth aspect of the invention, the power control device of the fourth solid-state storage device of the sixth aspect of the invention is provided, and in response to the failure of the power credit application module to apply for the power credit, the execution module suspends the processing of the operation of accessing the NVM chip until the power credit application module successfully applies for the power credit.
According to one of the power control means of the first to third solid-state storage devices of the sixth aspect of the present invention, there is provided the power control means of the fifth solid-state storage device of the sixth aspect of the present invention, wherein the power credit update module periodically updates the value of the power credit pool.
According to one of the power control apparatuses of the first to third solid-state storage devices of the sixth aspect of the present invention, there is provided the power control apparatus of the sixth solid-state storage device of the sixth aspect of the present invention, wherein the updating the value of the power credit pool by the power credit update module according to the difference between the current power value and the target power value includes: judging whether the solid-state storage device is in a power unlimited mode at present; if yes, the power available quota of the power quota pool is set to the maximum value, and the value of the power quota pool is updated.
According to one of the power control apparatuses of the first to sixth solid-state storage devices of the sixth aspect of the present invention, there is provided the power control apparatus of the seventh solid-state storage device of the sixth aspect of the present invention, wherein the updating the value of the power credit pool by the power credit update module according to the difference between the current power value and the target power value includes: if the current power value is larger than the target power value, reducing the value of the rated power pool; and if the current power value is smaller than the target power value, increasing the value of the rated power limit pool.
According to the power control apparatus of the seventh solid-state storage device of the sixth aspect of the present invention, there is provided the power control apparatus of the eighth solid-state storage device of the sixth aspect of the present invention, an amount of decrease or increase of the value of the power credit pool is proportional to a difference between the current power value and the target power value.
According to one of the power control means of the first to eighth solid-state storage devices of the sixth aspect of the present invention, there is provided the power control means of the ninth solid-state storage device according to the sixth aspect of the present invention, wherein the power credit update module lowers the target power value in response to an operation of accessing the NVM chip in which a burst occurs.
According to one of the power control apparatuses of the first to ninth solid-state storage devices of the sixth aspect of the present invention, there is provided the power control apparatus of the tenth solid-state storage device according to the sixth aspect of the present invention, the solid-state storage device including a plurality of command queues, an operation in one command queue to access the NVM chip accessing a logic unit corresponding to the command queue.
According to the tenth solid-state storage device power control apparatus of the sixth aspect of the present invention, there is provided the eleventh solid-state storage device power control apparatus of the sixth aspect of the present invention, wherein if the value of the power credit pool is not sufficiently allocated to the plurality of operations accessing the NVM chip, credit values are alternately allocated to the operations accessing the NVM chip in different command queues.
The power control device of the solid-state storage equipment controls the power of the solid-state storage equipment, manages the power consumption of the solid-state storage equipment more reasonably, and prolongs the use times and the service life of the solid-state storage equipment.
According to a seventh aspect of the present invention there is provided a program comprising program code which, when loaded into and executed on a storage device, causes the storage device to perform a method according to the first, second or fourth aspects of the present invention.
The program of the program code of the solid-state storage device enables the temperature and the power of the solid-state storage device to be controlled, the power consumption of the solid-state storage device is managed more reasonably, and the use times and the service life of the solid-state storage device are prolonged.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the description below are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to these drawings.
FIG. 1 is a block diagram of a solid-state storage device of the prior art;
FIG. 2 is a block diagram of a power management system according to an embodiment of the present invention;
FIG. 3 is a block diagram of a power management system according to yet another embodiment of the invention;
FIG. 4 is a flow diagram of a power control process according to yet another embodiment of the invention;
FIG. 5 is a flow diagram of a power control process according to yet another embodiment of the invention;
FIG. 6 is a block diagram of a power management system according to yet another embodiment of the invention;
FIG. 7 is a block diagram of a power management system according to yet another embodiment of the present invention;
FIG. 8 is a block diagram of a power management system according to another embodiment of the present invention;
FIG. 9 is a flow chart of a temperature-power control process according to another embodiment of the present invention;
FIG. 10 is a flow chart of a temperature-power control process according to yet another embodiment of the present invention;
FIG. 11 is a block diagram of a power management system according to another embodiment of the invention; and
fig. 12 is a flowchart of a temperature-power control process according to still another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The power consumption of the solid-state memory device mainly comes from reading, programming and erasing operations of the NVM chip. Each operation consumes different amounts of energy. For example, in one configuration (clock frequency, physical page size, etc.), the power consumption for a single NVM read operation is about 90mW (milliwatts), for a single program operation is about 150mW, and for a single erase operation is about 180mW. Multiple NVM chips may be included in a solid state storage device, and the Logical Units (LUNs) of the NVM chips may be accessed in parallel, so that read, program, or erase operations may be performed in parallel on the multiple logical units of the solid state storage device. The number of operations performed in parallel on multiple logic units also directly affects the power consumption of the solid-state storage device.
In embodiments according to the present invention, the desired power consumption state is achieved by controlling the number of read, program, erase, etc. operations issued to the NVM chip.
Example 1
Fig. 2 is a block diagram of a power management system according to embodiment 1 of the present invention. The solid-state storage device has different target power values, such as 25 watts, at different power states. As shown in fig. 2, a power management system 200 of a solid-state storage device includes a power manager 210 and a power sensor 230. The power manager 210 is coupled to the NVM chip 105 (see also fig. 1) for controlling whether IO operations in the command queue 240 accessing the NVM chip are sent to the NVM chip 105 depending on a power consumption control target. The power sensor 230 detects or collects power of the solid-state storage device, for example, by detecting current and/or voltage of a power supply of the solid-state storage device to obtain a power value. Power management system 200 also maintains a target power 220. The target power 220 indicates an upper power limit of the solid-state storage device in the current power state. In one example, power manager 210 obtains the current power of the solid-state storage device from power sensor 230 and compares it to a value indicated by target power 220. If the current power is less than the target power, the power manager 210 allows the IO operations in the command queue 240 to be sent to the NVM chip 105; if the current power is not less than the target power, the power manager 210 performs power control and prohibits sending IO operations in the command queue 240 to the NVM chip 105. The power manager 210 may be implemented in the control section 104 (see also fig. 1) of the solid-state storage device, or by a CPU in the control section 104 by executing a program.
Fig. 3 is a block diagram of a power management system according to yet another embodiment of the invention. As shown in fig. 3, the power management system 300 includes: power control unit 320, power credit pool 330, and power credit manager 310. The power credit manager 310 controls whether to send the accessed NVM chip IO operations in the command queue 240 to the NVM chip 105 according to the power credit provided by the power credit pool 330. In response to pending operations in the command queue 240 to access the NVM chip 105 (see also FIG. 1), the power credit manager 310 applies for power credits from the power credit pool 330. The power rating values required for different types of IO operations are different.
The power control unit 320 is coupled to the power sensor 230 and compares the current power provided by the power sensor 230 with the target power 220 to update the power rating value of the power rating pool 330. For example, when the current power is less than the target power 220, more power credits may be provided to the pool of power credits 330, and when the current power is greater than the target power, the value of the pool of power credits 330 may be decremented. The power rating of pool of power credits 330 determines the number of IO operations that may be concurrently run in the solid state storage device. When there is an IO operation to be sent to the NVM chip 105 in the command queue 240, the power line manager 310 applies for a power line to the power line pool 330, and returns the applied power line to the power line pool 330 after the IO operation is completed.
In one example, the initial credit value of the power credit pool 330 is 100, the credit value required for read operation of each NVM chip is 3, the credit value required for program operation of each NVM chip is 14, and the credit value required for erase operation of each NVM chip is 15. When there are reads in the command queue 240 to process, the power credit manager 310 requests credit value 3 from the power credit pool 330. In response to power credit manager 310 applying for credit 3, the credit of power credit pool 330 changes from 100 to 97. In response to completion of the read command execution, power credit manager 310 returns a credit value of 3 to power credit pool 330. Taking the initial value of power credit pool 330 as 100 for example, the solid-state storage device may process 33 read operations, 7 program operations, or 6 erase operations in parallel.
Alternatively, when the power credit of power credit pool 330 runs out, power credit manager 310 will suspend IO operations in process command queue 240.
For example, the power credit pool 330 has a power credit value of 7, and a program operation in the command queue 240 needs to be processed, and the required credit value is 14. Since the remaining value of power credit pool 330 is less than 14, it indicates that the remaining value is not sufficient to support the programming operation. The power credit manager 310 cannot get credit for the program operation, and thus temporarily processes the program operation of the command queue 240 until a power credit value sufficient for allocation to the program operation appears in the power credit pool 330. Optionally, power credit manager 310 schedules read operations in command queue 240. The credit required for the read is 3, which is less than the remaining credit of 7 of power credit pool 330, so that power credit manager 310 can obtain enough power credit from power credit pool 330 for the read and send the read to NVM chip 105.
Optionally, during the power control of the solid-state storage device, the current power is periodically obtained from the power sensor 230, compared with the target power 220, and the power rating value of the power rating pool 330 is updated.
Fig. 4 is a flow chart of a power control process according to yet another embodiment of the present invention. As shown in fig. 4, the process of controlling power of the solid-state storage device includes: the power control unit 320 obtains the current power value from the power sensor 230 and obtains the target power 220. The power control unit 320 updates the power rating of the power rating pool 330 according to the difference between the current power value and the target power value. In response to an IO operation accessing an NVM chip, power credit manager 310 applies for power credits to power credit pool 330. The amount of power required may be different for different types of IO operations. Generally, if the power quota value of power quota pool 330 is not less than the power quota required for IO operation, the power quota application will be successful, and the power quota value of power quota pool 330 is accordingly reduced by the requested quota value. If the power credit application is successful, the power credit manager 310 allows the IO operation to be sent to the NVM chip 105; if the power line application is unsuccessful, the processing of the IO operation is temporarily stopped, and the power line manager 310 continues to apply for the power line for the IO operation until the power line application is successful. In response to completion of the execution of the IO operation to access the NVM chip, the power credit is returned to the pool of power credits 330. In response to returning the power credit, the value of power credit pool 330 is increased by the returned credit value.
Fig. 5 is a flow diagram of a power control process according to yet another embodiment of the invention. As shown in fig. 5, the process of controlling power of the solid-state storage device includes: the power control unit 320 determines whether the power status is power status without limit, and sets the power available credit of the power credit pool 330 as the maximum value and updates the power credit of the power credit pool 330 in the power status without limit. The host may set the solid-state storage device to a power-unlimited power state. In one example, power control unit 320 and power credit manager 310 may still operate even in power-unlimited power states. The power control unit 320 updates the value of the power credit pool 330 according to the power available credit of the power credit pool 330. For example, the maximum value of the power credit of power credit pool 330 is 210, the current power credit is 100, and the current power credit is 50 since a portion of the power credits are applied for IO operations. Then the current value of power credit may be increased by the same amount, i.e., from 50 to 160, in response to the available credit of pool of power credits 330 being modified from current value 100 to maximum value 210.
The host may also set the solid-state storage device to other power states. Corresponding to each power state, has a respective target power 220. Optionally, the target power 220 is also specified by the host.
If not, the current power value is periodically obtained from the power sensor 230, and the power rating value of the power rating pool 330 is periodically updated. For example, in response to a timer event or interrupt, or polling a timer, the power control unit 320 reads the current power value from the power sensor 230 at the beginning or end of the period of obtaining power, and calculates the power available amount of the power credit pool 320 according to the difference between the current power value and the target power 220 at the beginning or end of the control period, and updates the power credit value of the power credit pool 330. The period for acquiring power and the control period may be the same or different. Reducing the period of power acquisition and/or the control period helps to improve the sensitivity or accuracy of power control.
As an example, during the period in which power is acquired, the current power value is not acquired from the power sensor 230. Therefore, in the period of obtaining power, if the control period is up, the power control unit 320 calculates the power available limit according to the last power value obtained from the power sensor 230.
For example, when the power control unit 320 updates the rating of the power rating pool 330, if the current power value is greater than the target power value, the power rating of the power rating pool 330 is decreased; if the current power value is smaller than the target power value, the power rating of the power rating pool 330 is increased. The amount of increase or decrease in the power credit of power credit pool 330 is proportional to the difference between the current power value and the target power value.
In another example, the power control unit 320 calculates the increment of the power usage amount according to the difference between the current power value and the target power value. For example, if the current power value is smaller than the target power value, the power credit is increased; if the current power value is larger than the target power value, the power available quota is reduced. And correspondingly updating the power quota value of the power quota pool 330 according to the increment of the power quota.
For example, let the power available quota be P, P (t) 0 ) Is the last moment (t) 0 Time of day) and P (t) 1 ) The power available credit to be updated currently is set as P c And the value of the power credit pool is an indication of the credit actually owned by the power credit pool, then:
P(t 1 )＝P(t 0 )-f(P m -P t ) Formula (1)
P m Is the current power value, P, obtained from the power sensor 230 t Is a target power 220, f represents a function, e.g. f (P) m -P t )＝(P m -P t ) K, k are coefficients.
When applying for a power credit (e.g. 10), only P c Is equal to the requested power limit (e.g., 10), and when P is reached c If the value is less than 10, the application fails.
Power credit pool 330 maintains power credit P of power credit pool 330 and power credit P of power credit pool 330 c 。
In order to update the power rating value P c In one example, the power control unit 320 reads the power credit P (t) from the power credit pool 330 0 ) P (t) is calculated by formula (1) 1 ) (ii) a The available power limit P (t) 1 ) To power credit pool 330. Power credit pool 330 based on received power credit P (t) 1 ) By P (t) 1 ) And P (t) 0 ) Is taken as the power rating value P c The increment of (c).
As an updated power rating value P c For another example, power control unit 320 may be configured to limit power from a power limitPool 330 reads power headroom P (t) 0 ) P (t) is calculated by formula (1) 1 ) P (t) 1 ) And P (t) 0 ) The difference value of (c) is provided to power credit pool 330. And power credit pool 330 updates the power credit value (P) of power credit pool 330 based on the received difference c ＝P c +(P(t 1 )-P(t 0 ))). And the power credit pool 330 also obtains and records the updated power credit (P (t) by the difference 1 )。
When applying for the credit, if the power credit Pc of the power credit pool 330 is not less than the power credit critical applied, the credit is successfully applied, and the power credit of the power credit pool is updated (Pc = Pc-critical). And when the quota is released, updating the power quota value (Pc = Pc + credit) of the power quota pool, wherein credit is the power quota value required by one IO operation.
In another embodiment according to the present invention, the read, program, and erase operations accessing NVM chip 105 are counted to identify a burst of IO operations. The burst of the IO operation refers to that there is a read operation, a write operation, or an erase operation exceeding a threshold value in a unit time, or the total amount/weighted total amount of the three IO operations exceeds the threshold value, or may refer to that the increment of the IO operation exceeds the threshold value in the unit time. Optionally, different thresholds are specified for each operation to identify a burst of IO operations.
In response to identifying a burst of IO operations, power control unit 320 reduces the value of target power 220, thereby inhibiting a large increase in solid state storage device power caused by a burst of large number of operations.
FIG. 6 is a block diagram of a power management system according to yet another embodiment of the invention. Power management system 600, shown in FIG. 6, is similar to power management system 300, shown in FIG. 3, except that power credit manager 610 also makes statistics of IO operations and provides statistics of read operations, program operations, and/or erase operations to power control unit 620. Based on the statistics of the IO operations, power control unit 620 identifies bursts of IO operations and modifies (lowers) target power 220 in response to the bursts of IO operations.
According to still another embodiment of the present invention, the temperature of the solid-state storage device is controlled by using the power management system, so as to prevent the solid-state storage device from operating at an excessively high temperature. Temperature is a byproduct of power consumption, and thus heat generation of the solid-state storage device is controlled by managing power consumption of the solid-state storage device.
Fig. 7 is a block diagram of a power management system according to another embodiment of the invention, the power management system 700 including a power manager 710 and a temperature sensor 730. The power manager 710 is coupled to the NVM chip 105 (see also fig. 1) for controlling whether IO operations in the command queue 240 accessing the NVM chip are sent to the NVM chip 105 depending on the temperature control target. The temperature sensor 730 detects or collects the temperature of the solid state storage device, for example by acquiring temperature values through temperature sensors disposed at one or more locations of the solid state storage device. The power management system 700 also maintains a target temperature 720. The target temperature 720 indicates an upper operating temperature limit for the solid-state storage device.
In one example, power manager 710 obtains a current temperature of the solid-state storage device from temperature sensor 730, which is compared to a value indicated by target temperature 720. If the current temperature is less than the target temperature 720, the power manager 710 allows the IO operations in the command queue 240 to be sent to the NVM chip 105; if the current temperature is not less than the target temperature 720, the power manager 710 performs power control and inhibits IO operations in the command queue 240 from being sent to the NVM chip 105.
Fig. 8 is a block diagram of a power management system according to another embodiment of the invention. As shown in fig. 8, power management system 800 includes: power control unit 820, power credit pool 830, and power credit manager 810. The power credit manager 810 controls whether to send the IO operations in the command queue 240 accessing the NVM chip to the NVM chip 105 according to the power credit provided by the power credit pool 830. In response to pending operations in the command queue 240 to access the NVM chip 105 (see also FIG. 1), the power credit manager 810 applies for power credits from the power credit pool 830.
Power control unit 820 is coupled to temperature sensor 840 and compares the current temperature provided by temperature sensor 840 with target temperature 842 to update the power rating of power rating pool 830. For example, when the current temperature is less than target temperature 842, more power credit may be provided to power credit pool 830, and when the current temperature is greater than the target temperature, the value of power credit pool 830 may be decremented. When there are IO operations to be sent to the NVM chip 105 in the command queue 240, the power line manager 810 applies for power lines from the power line pool 830, and returns the applied power lines to the power line pool 830 after the IO operations are completed.
When the power credit of power credit pool 830 runs out, power credit manager 810 will suspend IO operations in process command queue 240.
Further, power control unit 820 is also coupled to power sensor 850 to compare the current power provided by power sensor 850 with target power 852 to update the power rating value of power rating pool 830. For example, when the current power is less than target power 852, more power credits may be provided to power credit pool 830, and when the current power is greater than target power 852, the value of power credit pool 830 may be decremented.
Optionally, during the power control of the solid-state storage device, the power control unit 820 periodically obtains the current power from the power sensor 850, compares the current power with the target power 852, and updates the power rating value of the power rating pool 830.
Still further, if the power control unit 820 considers that the power rating value is to be added to the power rating pool 830 according to one of the temperature or the power, and considers that the power rating value of the power rating pool 830 is to be reduced according to the other of the temperature or the power, the reduction of the power rating value is performed without performing the increase of the power rating value, so as to ensure the security of the solid-state storage device.
Optionally, the host may set different target temperature values to the solid-state storage device, so as to adapt the solid-state storage device to different operating environments, for example, a host with a stronger heat dissipation capability or a host with a general heat dissipation capability.
Fig. 9 is a flow chart of a temperature-power control process according to another embodiment of the present invention. As shown in fig. 9, the process of controlling the temperature and power of the solid-state storage device includes: power control unit 820 obtains a current temperature value from temperature sensor 840 and obtains a target temperature 842. The power control unit 820 updates the power rating of the power rating pool 830 according to the difference between the current temperature value and the target temperature value provided by the temperature sensor 840. In response to there being an IO operation in command queue 240 to access the NVM chip, power credit manager 810 applies for power credits from power credit pool 830. If the power credit application is successful, the power credit manager 810 allows the IO operation to be sent to the NVM chip 105; if the power credit is not applied successfully, the processing of the IO operation is temporarily stopped, and the power credit manager 810 continues to apply for the power credit for the IO operation until the power credit is applied successfully. In response to the completion of the execution of the operation to access the NVM chip, the power credit is returned to the pool of power credits 830. In response to returning the power credit, the value of power credit pool 830 is increased by the returned credit value.
Optionally, according to the difference between the current temperature value and the target temperature value, the value of the updated power credit pool 830 is: if the current temperature value is greater than the target temperature value, reducing the value of the rated power pool 830; if the current temperature value is smaller than the target temperature value, the value of the power credit pool 830 is increased. For example, the amount by which power credit pool 830 is decreased or increased is proportional to the difference between the current temperature value and the target temperature value. In another example, the amount of decrease or increase in the value of power credit pool 830 is obtained based on the difference between the current temperature value and the target temperature value. For example, the difference between the current temperature value and the target temperature value is integrated over time to obtain the increment of power credit pool 830. Such that if the temperature of the solid-state storage device is lower than the target temperature value for a long period of time, there may be a large increase in the value of the power rating value 830.
Optionally, the power credit value of the power credit pool 22 is updated periodically during the power control of the solid-state storage device.
Fig. 10 is a flow chart of a temperature-power control process according to yet another embodiment of the present invention. As shown in fig. 10, the process of controlling the temperature and power of the solid-state storage device includes: power control unit 820 determines whether a power-unlimited power state is currently present. In the power state with unlimited power, the power credit of the power credit pool 830 is set to be the maximum value, and the power credit of the power credit pool 830 is updated. The host may set the solid-state storage device to a power-unlimited power state, and the host may set the solid-state storage device to other power states, corresponding to the respective power states, having respective target temperatures 842 and/or target powers 852. Optionally, the target power 852 and/or target temperature 842 are also specified by the host.
If the power state is not a power-unlimited state, a current temperature value is periodically obtained from the temperature sensor 840, and the power quota value of the power quota pool 830 is updated based on the power quota of the temperature. For example, in response to a timer event or interrupt, or polling a timer, at the beginning or end of a temperature acquisition cycle, power control unit 820 reads a current temperature value from temperature sensor 840, calculates a temperature-based power credit based on the difference between the current temperature value and target temperature 842, and updates the power credit value of power credit pool 830.
Further, the power credit value of the power credit pool 830 is updated when the temperature-based power credit is less than the power-based power credit to avoid the power of the solid-state storage device exceeding the target power. Wherein, the power-based power available limit is calculated according to the difference between the current power value and the target power 852. Alternatively, at the beginning or end of the control period, the power quota value of the power quota pool 830 is updated according to the smaller of the temperature-based power quota and the power-based power quota. If the smaller of the two is higher, the power quota value of the power quota pool 830 is increased; if the smaller of the two decreases, the power credit value of power credit pool 830 is decreased.
FIG. 11 is a block diagram of a power management system according to another embodiment of the present invention, the power management system 1100 shown in FIG. 11 is similar to the power management system 800 shown in FIG. 8 except that the power line manager 1110 controls the plurality of command queues, namely the command queue 240, the command queue 250, and the command queue 260, whether to send IO operations in the command queue 240, the command queue 250, and the command queue 260 to the NVM chip 105 to access the NVM chip. Power credit manager 1110 also counts IO operations and provides statistics for read operations, program operations, and/or erase operations to power control unit 1120. Based on the statistics of the IO operations, power control unit 1120 identifies bursts of IO operations and modifies (lowers) target temperature 842 and target power 852 in response to the bursts of IO operations.
Further, power credit manager 1110 selects one of the command queues and processes the IO operations of the selected command queue to avoid waiting too long for the IO operations in a command queue to be processed. For example, when the power quota value of power quota pool 830 is insufficient to support the simultaneous processing of multiple IO operations, power quota manager 1110 may alternatively apply for power quota for IO operations in multiple command queues.
Fig. 12 is a flowchart of a temperature-power control process according to still another embodiment of the present invention. As shown in fig. 12 (see also fig. 11), the process of controlling the temperature and power of the solid-state storage device includes: the power control unit 1120 determines whether the power status is power status without limit, and sets the power available credit of the power credit pool 830 as the maximum value and updates the power credit of the power credit pool 830 in the power status without limit. The host may set the solid-state storage device to a power-unlimited power state. In one example, power control unit 1120 and power credit manager 1110 may still operate even in power-unlimited power states. The power control unit 1120 updates the power quota value of the power quota pool 830 according to the power available quota of the power quota pool 830.
If not in the power-unlimited power state, power control unit 1120 periodically obtains the current temperature value from temperature sensor 840 and periodically updates the power rating value of power rating pool 830. For example, in response to a timer event or interrupt, or based on polling a timer, power control unit 1120 reads the current temperature value from temperature sensor 840 at the beginning or end of the period to obtain the temperature, and updates the power rating value of power rating pool 830 at the beginning or end of the control period based on the current temperature value and target temperature 842.
Further, at the beginning or end of the control period, power control unit 1120 updates statistics on read operations, program operations, and/or erase operations accessing NVM chip 105 in command queue 240, command queue 250, and/or command queue 260 to identify whether a burst of IO operations occurred. In response to identifying a burst of an IO operation, control unit 1120 adjusts the target power value down. And skipping the adjustment of the target power value in the case of no burst of IO operation.
Power control unit 1120 updates the power credit value of power credit pool 830 according to the current power value and the target power value obtained from power sensor 850 and/or the current temperature value and the target temperature value obtained from temperature sensor 840. For example, a power-based power availability credit is calculated based on a difference between a current power value and a target power value, and a temperature-based power availability credit is calculated based on a difference between a current temperature value and a target temperature value. And updates the power quota value of the power quota pool 830 according to a change in the smaller of the temperature-based power quota and the power-based power quota.
In another example, if the power control unit 1120 considers that the power rating of the power credit pool 830 is to be increased according to one of temperature or power, and considers that the power rating of the power credit pool 830 is to be decreased according to the other of temperature or power, the decrease of the power rating is performed without performing the increase of the power rating, so as to ensure the security of the solid state storage device.
The embodiment of the invention controls the temperature and the power of the solid-state storage device, more reasonably manages the power consumption of the solid-state storage device, and improves the reliability and the service life of the solid-state storage device.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (9)

1. A control method of a solid-state storage device is characterized by comprising the following steps:
s1, measuring a current temperature value;
s2, updating the value of the power limit pool according to the difference between the current temperature value and the target temperature value;
s3, responding to IO operation for accessing the NVM chip, and applying for power limit from the power limit pool for different types of IO operation; responding to the success of the power credit application, and correspondingly reducing the applied credit by the power credit value of the power credit pool; different types of IO operations require different power rating values;
s4, according to the applied power limit, executing the operation of accessing the NVM chip;
and S5, in response to the completion of the execution of the IO operation for accessing the NVM chip, returning the power limit, and increasing the returned limit value by the value of the power limit pool.
2. The method for controlling a solid-state storage device according to claim 1, wherein if the current temperature value is greater than the target temperature value, the value of the power credit pool is decreased; and if the current temperature value is smaller than the target temperature value, the value of the power limit pool is increased.
3. The method as claimed in claim 1 or 2, wherein updating the value of the power credit pool according to the difference between the current temperature value and the target temperature value comprises:
judging whether the solid-state storage device is in a power unlimited mode at present;
if yes, the power available quota of the power quota pool is set to the maximum value, and the value of the power quota pool is updated.
4. A control method of a solid-state storage device is characterized by comprising the following steps:
measuring the current power value, calculating the increment of the power available limit according to the difference between the current power value and the target power value, and updating the power available limit of the power limit pool;
measuring a current temperature value;
calculating a second power available limit of the power limit pool according to the difference between the current temperature value and the target temperature value;
if the second power available quota is smaller than the power available quota of the power quota pool, updating the power available quota of the power quota pool by using the second power available quota;
and correspondingly updating the power quota value of the power quota pool according to the increment of the power available quota of the power quota pool.
5. The method for controlling a solid-state storage device according to claim 4, further comprising:
applying for a power credit from the power credit pool in response to the presence of an operation to access the NVM chip;
executing the operation of accessing the NVM chip according to the applied power limit;
the power credit is returned in response to completion of performance of the operation to access the NVM chip.
6. The method of controlling a solid-state storage device according to claim 4 or 5, wherein the target power value is turned down in response to an operation of accessing the NVM chip in which a burst occurs.
7. A solid state storage device, comprising: the system comprises an NVM chip, a control manager and a temperature sensor, wherein the NVM chip is coupled with the control manager, and the temperature sensor is coupled with a control management system;
the temperature sensor is used for measuring the current temperature of the solid-state storage device;
the control manager is used for scheduling and accessing IO operation of the NVM chip according to the difference between the current temperature and the target temperature of the solid-state storage device measured by the temperature sensor;
the control manager includes: a power control unit, a power credit pool and a power credit manager, the power credit pool is coupled with the power credit manager and the power control unit respectively, the power credit manager is coupled with the NVM chip, the power control unit is coupled with the temperature sensor, wherein,
the power control unit is used for setting a power quota value of the power quota pool according to the current temperature value and the target temperature value and according to the current temperature value and the target temperature value;
the power quota manager is used for responding to IO operations for accessing the NVM chip, applying for power quota for different types of IO operations to the power quota pool, allowing the operation for accessing the NVM chip to be executed, responding to successful application of the power quota, correspondingly reducing the applied quota value of the power quota pool, and returning the power quota to the power quota pool after the operation execution is completed;
different types of IO operations require different power rating values.
8. The solid-state storage device of claim 7, wherein the power control unit is further to identify a burst of IO operations accessing the NVM chip and adjust the target power value lower.
9. The solid-state storage device of claim 7, further comprising a power sensor for measuring a current power of the solid-state storage device and coupled to the power control unit;
the power control unit calculates a power-based power available amount according to a difference between the current power and the target power, calculates a temperature-based power available amount according to a difference between the current temperature and the target temperature, and updates a power amount value of the power amount pool according to a smaller one of the power-based power available amount and the temperature-based power available amount.
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